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authorKanoj Sarcar <kanoj@engr.sgi.com>2000-11-29 22:00:30 +0000
committerKanoj Sarcar <kanoj@engr.sgi.com>2000-11-29 22:00:30 +0000
commitc646de67cdaa3d75b7c7d06bfd0e3eb763c50ce5 (patch)
tree00cfc79eba30b492c981da7fc6a11b0143805cf5 /include/asm-mips64
parent7f242fee790824c50972ffd73aaa5f43b4ceeca7 (diff)
Use the same definition of flush_icache_page() that is used in stock
Linux 2.4.
Diffstat (limited to 'include/asm-mips64')
-rw-r--r--include/asm-mips64/pgtable.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h
index af0c7b4c9..ab9279aa8 100644
--- a/include/asm-mips64/pgtable.h
+++ b/include/asm-mips64/pgtable.h
@@ -44,7 +44,7 @@ extern void (*_flush_page_to_ram)(struct page * page);
#define flush_icache_range(start, end) _flush_cache_l1()
-#define flush_icache_page(vma, page, address) \
+#define flush_icache_page(vma, page) \
do { \
unsigned long addr; \
addr = (unsigned long) page_address(page); \
@@ -60,16 +60,16 @@ do { \
* are io coherent. The only place where we might be overoptimizing
* out icache flushes are from mprotect (when PROT_EXEC is added).
*/
-extern void andes_flush_icache_page(unsigned long, unsigned long);
+extern void andes_flush_icache_page(unsigned long);
#define flush_cache_mm(mm) do { } while(0)
#define flush_cache_range(mm,start,end) do { } while(0)
#define flush_cache_page(vma,page) do { } while(0)
#define flush_page_to_ram(page) do { } while(0)
#define flush_icache_range(start, end) _flush_cache_l1()
-#define flush_icache_page(vma, page, address) \
+#define flush_icache_page(vma, page) \
do { \
if ((vma)->vm_flags & VM_EXEC) \
- andes_flush_icache_page(page_address(page), address); \
+ andes_flush_icache_page(page_address(page)); \
} while (0)
#endif /* !CONFIG_CPU_R10000 */