Merge with 2.3.99-pre9.

10 files changed, 386 insertions, 133 deletions

diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 17108905d..df6d51225 100644
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -14,8 +14,4 @@
 #define        L1_CACHE_BYTES  32
 #endif
 
-extern void cache_flush_area(unsigned long start, unsigned long end);
-extern void cache_purge_area(unsigned long start, unsigned long end);
-extern void cache_wback_area(unsigned long start, unsigned long end);
-
 #endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sh/checksum.h b/include/asm-sh/checksum.h
index 846e64509..6e1a728bf 100644
--- a/include/asm-sh/checksum.h
+++ b/include/asm-sh/checksum.h
@@ -72,16 +72,16 @@ unsigned int csum_partial_copy( const char *src, char *dst, int len, int sum);
 static __inline__ unsigned int csum_fold(unsigned int sum)
 {
 	unsigned int __dummy;
-	__asm__("clrt\n\t"
-		"mov	%0, %1\n\t"
-		"shll16	%0\n\t"
-		"addc	%0, %1\n\t"
-		"movt	%0\n\t"
-		"shlr16	%1\n\t"
-		"add	%1, %0"
+	__asm__("swap.w %0, %1\n\t"
+		"extu.w	%0, %0\n\t"
+		"extu.w	%1, %1\n\t"
+		"add	%1, %0\n\t"
+		"swap.w	%0, %1\n\t"
+		"add	%1, %0\n\t"
+		"not	%0, %0\n\t"
 		: "=r" (sum), "=&r" (__dummy)
 		: "0" (sum));
-	return ~sum;
+	return sum;
 }
 
 /*
@@ -93,31 +93,26 @@ static __inline__ unsigned int csum_fold(unsigned int sum)
  */
 static __inline__ unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl)
 {
-	unsigned int sum, __dummy;
+	unsigned int sum, __dummy0, __dummy1;
 
 	__asm__ __volatile__(
 		"mov.l	@%1+, %0\n\t"
-		"add	#-4, %2\n\t"
-		"clrt\n\t"
 		"mov.l	@%1+, %3\n\t"
-		"addc	%3, %0\n\t"
-		"mov.l	@%1+, %3\n\t"
-		"addc	%3, %0\n\t"
-		"mov.l	@%1+, %3\n\t"
-		"addc	%3, %0\n"
+		"add	#-2, %2\n\t"
+		"clrt\n\t"
 		"1:\t"
-		"mov.l	@%1+, %3\n\t"
 		"addc	%3, %0\n\t"
-		"movt	%3\n\t"
+		"movt	%4\n\t"
+		"mov.l	@%1+, %3\n\t"
 		"dt	%2\n\t"
 		"bf/s	1b\n\t"
-		" cmp/eq #1, %3\n\t"
-		"mov	#0, %3\n\t"
+		" cmp/eq #1, %4\n\t"
 		"addc	%3, %0\n\t"
+		"addc	%2, %0"	    /* Here %2 is 0, add carry-bit */
 	/* Since the input registers which are loaded with iph and ihl
 	   are modified, we must also specify them as outputs, or gcc
 	   will assume they contain their original values. */
-	: "=r" (sum), "=r" (iph), "=r" (ihl), "=&z" (__dummy)
+	: "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
 	: "1" (iph), "2" (ihl));
 
 	return	csum_fold(sum);
diff --git a/include/asm-sh/hitachi_se.h b/include/asm-sh/hitachi_se.h
new file mode 100644
index 000000000..282bbce8f
--- /dev/null
+++ b/include/asm-sh/hitachi_se.h
@@ -0,0 +1,53 @@
+#ifndef __ASM_SH_HITACHI_SE_H
+#define __ASM_SH_HITACHI_SE_H
+
+/*
+ * linux/include/asm-sh/hitachi_se.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine support
+ */
+
+/* Box specific addresses.  */
+
+#define PA_ROM		0x00000000	/* EPROM */
+#define PA_ROM_SIZE	0x00400000	/* EPROM size 4M byte */
+#define PA_FROM		0x01000000	/* EPROM */
+#define PA_FROM_SIZE	0x00400000	/* EPROM size 4M byte */
+#define PA_EXT1		0x04000000
+#define PA_EXT1_SIZE	0x04000000
+#define PA_EXT2		0x08000000
+#define PA_EXT2_SIZE	0x04000000
+#define PA_SDRAM	0x0c000000
+#define PA_SDRAM_SIZE	0x04000000
+
+#define PA_EXT4		0x12000000
+#define PA_EXT4_SIZE	0x02000000
+#define PA_EXT5		0x14000000
+#define PA_EXT5_SIZE	0x04000000
+#define PA_PCIC		0x18000000	/* MR-SHPC-01 PCMCIA */
+
+#define PA_83902	0xb0000000	/* DP83902A */
+#define PA_83902_IF	0xb0040000	/* DP83902A remote io port */
+#define PA_83902_RST	0xb0080000	/* DP83902A reset port */
+
+#define PA_SUPERIO	0xb0400000	/* SMC37C935A super io chip */
+#define PA_DIPSW0	0xb0800000	/* Dip switch 5,6 */
+#define PA_DIPSW1	0xb0800002	/* Dip switch 7,8 */
+#define PA_LED		0xb0c00000	/* LED */
+#define PA_BCR		0xb1400000	/* FPGA */
+
+#define PA_MRSHPC	0xb83fffe0	/* MR-SHPC-01 PCMCIA controler */
+
+#define BCR_ILCRA	(PA_BCR + 0)
+#define BCR_ILCRB	(PA_BCR + 2)
+#define BCR_ILCRC	(PA_BCR + 4)
+#define BCR_ILCRD	(PA_BCR + 6)
+#define BCR_ILCRE	(PA_BCR + 8)
+#define BCR_ILCRF	(PA_BCR + 10)
+#define BCR_ILCRG	(PA_BCR + 12)
+
+#define IRQ_STNIC	10
+
+#endif  /* __ASM_SH_HITACHI_SE_H */
diff --git a/include/asm-sh/ide.h b/include/asm-sh/ide.h
index 95a385596..ec82befa2 100644
--- a/include/asm-sh/ide.h
+++ b/include/asm-sh/ide.h
@@ -17,7 +17,7 @@
 #include <linux/config.h>
 
 #ifndef MAX_HWIFS
-#define MAX_HWIFS	1	/* XXX: For my board -- gniibe */
+#define MAX_HWIFS	1
 #endif
 
 #define ide__sti()	__sti()
@@ -25,8 +25,8 @@
 static __inline__ int ide_default_irq(ide_ioreg_t base)
 {
 	switch (base) {
-		case 0xba0001f0: return 14;
-		case 0xba000170: return 14;
+		case 0x01f0: return 14;
+		case 0x0170: return 15;
 		default:
 			return 0;
 	}
@@ -36,9 +36,9 @@ static __inline__ ide_ioreg_t ide_default_io_base(int index)
 {
 	switch (index) {
 		case 0:	
-			return 0xba0001f0;
+			return 0x01f0;
 		case 1:	
-			return 0xba000170;
+			return 0x0170;
 		default:
 			return 0;
 	}
@@ -69,6 +69,7 @@ static __inline__ void ide_init_default_hwifs(void)
 	int index;
 
 	for(index = 0; index < MAX_HWIFS; index++) {
+		memset(&hw, 0, sizeof(hw_regs_t));
 		ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
 		hw.irq = ide_default_irq(ide_default_io_base(index));
 		ide_register_hw(&hw, NULL);
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 5a7b0468b..c6de2a42a 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -14,9 +14,6 @@
 
 #include <asm/cache.h>
 
-#define inb_p	inb
-#define outb_p	outb
-
 #define inw_p	inw
 #define outw_p	outw
 
@@ -53,103 +50,62 @@ extern __inline__ void writel(unsigned int b, unsigned long addr)
         *(volatile unsigned long*)addr = b;
 }
 
-extern __inline__ unsigned long inb_local(unsigned long addr)
-{
-	return readb(addr);
-}
-
-extern __inline__ void outb_local(unsigned char b, unsigned long addr)
-{
-	return writeb(b,addr);
-}
-
-extern __inline__ unsigned long inb(unsigned long addr)
-{
-	return readb(addr);
-}
-
-extern __inline__ unsigned long inw(unsigned long addr)
-{
-	return readw(addr);
-}
-
-extern __inline__ unsigned long inl(unsigned long addr)
-{
-	return readl(addr);
-}
-
-extern __inline__ void insb(unsigned long addr, void *buffer, int count)
-{
-	unsigned char *buf=buffer;
-	while(count--) *buf++=inb(addr);
-}
-
-extern __inline__ void insw(unsigned long addr, void *buffer, int count)
-{
-	unsigned short *buf=buffer;
-	while(count--) *buf++=inw(addr);
-}
-
-extern __inline__ void insl(unsigned long addr, void *buffer, int count)
-{
-	unsigned long *buf=buffer;
-	while(count--) *buf++=inl(addr);
-}
-
-extern __inline__ void outb(unsigned char b, unsigned long addr)
-{
-       return writeb(b,addr);
-}
-
-extern __inline__ void outw(unsigned short b, unsigned long addr)
-{
-       return writew(b,addr);
-}
-
-extern __inline__ void outl(unsigned int b, unsigned long addr)
-{
-       return writel(b,addr);
-}
+extern unsigned long inb(unsigned int port);
+extern unsigned long inb_p(unsigned int port);
+extern unsigned long inw(unsigned int port);
+extern unsigned long inl(unsigned int port);
+extern void insb(unsigned int port, void *addr, unsigned long count);
+extern void insw(unsigned int port, void *addr, unsigned long count);
+extern void insl(unsigned int port, void *addr, unsigned long count);
 
-extern __inline__ void outsb(unsigned long addr, const void *buffer, int count)
-{
-	const unsigned char *buf=buffer;
-	while(count--) outb(*buf++, addr);
-}
+extern void outb(unsigned long value, unsigned int port);
+extern void outb_p(unsigned long value, unsigned int port);
+extern void outw(unsigned long value, unsigned int port);
+extern void outl(unsigned long value, unsigned int port);
+extern void outsb(unsigned int port, const void *addr, unsigned long count);
+extern void outsw(unsigned int port, const void *addr, unsigned long count);
+extern void outsl(unsigned int port, const void *addr, unsigned long count);
 
-extern __inline__ void outsw(unsigned long addr, const void *buffer, int count)
-{
-	const unsigned short *buf=buffer;
-	while(count--) outw(*buf++, addr);
-}
-
-extern __inline__ void outsl(unsigned long addr, const void *buffer, int count)
-{
-	const unsigned long *buf=buffer;
-	while(count--) outl(*buf++, addr);
-}
+/*
+ * If the platform has PC-like I/O, this function gives us the address
+ * from the offset.
+ */
+extern unsigned long sh_isa_slot(unsigned long offset);
+
+#define isa_readb(a) readb(sh_isa_slot(a))
+#define isa_readw(a) readw(sh_isa_slot(a))
+#define isa_readl(a) readl(sh_isa_slot(a))
+#define isa_writeb(b,a) writeb(b,sh_isa_slot(a))
+#define isa_writew(w,a) writew(w,sh_isa_slot(a))
+#define isa_writel(l,a) writel(l,sh_isa_slot(a))
+#define isa_memset_io(a,b,c) \
+  memset((void *)(sh_isa_slot((unsigned long)a)),(b),(c))
+#define isa_memcpy_fromio(a,b,c) \
+  memcpy((a),(void *)(sh_isa_slot((unsigned long)(b))),(c))
+#define isa_memcpy_toio(a,b,c) \
+  memcpy((void *)(sh_isa_slot((unsigned long)(a))),(b),(c))
 
 #define ctrl_in(addr)		*(addr)
 #define ctrl_out(data,addr)	*(addr) = (data)
 
 extern __inline__ unsigned long ctrl_inb(unsigned long addr)
 {
-       return *(volatile unsigned char*)addr;
+	return *(volatile unsigned char*)addr;
 }
 
 extern __inline__ unsigned long ctrl_inw(unsigned long addr)
 {
-       return *(volatile unsigned short*)addr;
+	return *(volatile unsigned short*)addr;
 }
 
 extern __inline__ unsigned long ctrl_inl(unsigned long addr)
 {
-       return *(volatile unsigned long*)addr;
+	return *(volatile unsigned long*)addr;
 }
 
 extern __inline__ void ctrl_outb(unsigned char b, unsigned long addr)
 {
-       *(volatile unsigned char*)addr = b;
+	*(volatile unsigned char*)addr = b;
 }
 
 extern __inline__ void ctrl_outw(unsigned short b, unsigned long addr)
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index ab492fa5b..d013f35fc 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -5,15 +5,31 @@
  *
  * linux/include/asm-sh/irq.h
  *
- * Copyright (C) 1999  Niibe Yutaka
+ * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
+ * Copyright (C) 2000  Kazumoto Kojima
  *
  */
 
 #include <linux/config.h>
 
-#define TIMER_IRQ		16	/* Hard-wired */
-#define TIMER_IPR_OFFSET	12
-#define TIMER_PRIORITY		 2
+#if defined(__sh3__)
+#define INTC_IPRA  	0xfffffee2UL
+#define INTC_IPRB  	0xfffffee4UL
+#elif defined(__SH4__)
+#define INTC_IPRA	0xffd00004UL
+#define INTC_IPRB	0xffd00008UL
+#define INTC_IPRC	0xffd0000cUL
+#endif
+
+#define TIMER_IRQ	16
+#define TIMER_IPR_ADDR	INTC_IPRA
+#define TIMER_IPR_POS	 3
+#define TIMER_PRIORITY	 2
+
+#define RTC_IRQ		22
+#define RTC_IPR_ADDR	INTC_IPRA
+#define RTC_IPR_POS	 0
+#define RTC_PRIORITY	TIMER_PRIORITY
 
 #if defined(__SH4__)
 /*
@@ -37,8 +53,52 @@ extern void enable_irq(unsigned int);
 /*
  * Function for "on chip support modules".
  */
-extern void set_ipr_data(unsigned int irq, int offset, int priority);
-extern void make_onChip_irq(unsigned int irq);
+extern void set_ipr_data(unsigned int irq, unsigned int addr,
+			 int pos,  int priority);
+extern void make_ipr_irq(unsigned int irq);
 extern void make_imask_irq(unsigned int irq);
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7709)
+#define INTC_IRR0	0xa4000004UL
+#define INTC_IRR1	0xa4000006UL
+#define INTC_IRR2	0xa4000008UL
+
+#define INTC_ICR0  	0xfffffee0UL
+#define INTC_ICR1  	0xa4000010UL
+#define INTC_ICR2  	0xa4000012UL
+#define INTC_INTER 	0xa4000014UL
+
+#define INTC_IPRC  	0xa4000016UL
+#define INTC_IPRD  	0xa4000018UL
+#define INTC_IPRE  	0xa400001aUL
+
+#define IRQ0_IRQ	32
+#define IRQ1_IRQ	33
+#define IRQ2_IRQ	34
+#define IRQ3_IRQ	35
+#define IRQ4_IRQ	36
+#define IRQ5_IRQ	37
+
+#define IRQ0_IRP_ADDR	INTC_IPRC
+#define IRQ1_IRP_ADDR	INTC_IPRC
+#define IRQ2_IRP_ADDR	INTC_IPRC
+#define IRQ3_IRP_ADDR	INTC_IPRC
+#define IRQ4_IRP_ADDR	INTC_IPRD
+#define IRQ5_IRP_ADDR	INTC_IPRD
+
+#define IRQ0_IRP_POS	0
+#define IRQ1_IRP_POS	1
+#define IRQ2_IRP_POS	2
+#define IRQ3_IRP_POS	3
+#define IRQ4_IRP_POS	0
+#define IRQ5_IRP_POS	1
+
+#define IRQ0_PRIORITY	1
+#define IRQ1_PRIORITY	1
+#define IRQ2_PRIORITY	1
+#define IRQ3_PRIORITY	1
+#define IRQ4_PRIORITY	1
+#define IRQ5_PRIORITY	1
+#endif
+
 #endif /* __ASM_SH_IRQ_H */
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index ca6fffbca..f39d88aaa 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -22,7 +22,10 @@ extern void paging_init(void);
  *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
  *  - flush_cache_page(mm, vmaddr) flushes a single page
  *  - flush_cache_range(mm, start, end) flushes a range of pages
+ *
  *  - flush_page_to_ram(page) write back kernel page to ram
+ *  - flush_icache_range(start, end) flushes(invalidates) a range for icache
+ *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
  *
  *  Caches are indexed (effectively) by physical address on SH-3, so
  *  we don't need them.
@@ -43,8 +46,7 @@ extern void flush_cache_mm(struct mm_struct *mm);
 extern void flush_cache_range(struct mm_struct *mm, unsigned long start,
 			      unsigned long end);
 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr);
-extern void __flush_page_to_ram(unsigned long page_va);
-#define flush_page_to_ram(page)	__flush_page_to_ram(page_address(page))
+extern void flush_page_to_ram(struct page *page);
 extern void flush_icache_range(unsigned long start, unsigned long end);
 extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
 #endif
diff --git a/include/asm-sh/smc37c93x.h b/include/asm-sh/smc37c93x.h
new file mode 100644
index 000000000..585da2a8f
--- /dev/null
+++ b/include/asm-sh/smc37c93x.h
@@ -0,0 +1,190 @@
+#ifndef __ASM_SH_SMC37C93X_H
+#define __ASM_SH_SMC37C93X_H
+
+/*
+ * linux/include/asm-sh/smc37c93x.h
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * SMSC 37C93x Super IO Chip support
+ */
+
+/* Default base I/O address */
+#define FDC_PRIMARY_BASE	0x3f0
+#define IDE1_PRIMARY_BASE	0x1f0
+#define IDE1_SECONDARY_BASE	0x170
+#define PARPORT_PRIMARY_BASE	0x378
+#define COM1_PRIMARY_BASE	0x2f8
+#define COM2_PRIMARY_BASE	0x3f8
+#define RTC_PRIMARY_BASE	0x070
+#define KBC_PRIMARY_BASE	0x060
+#define AUXIO_PRIMARY_BASE	0x000	/* XXX */
+
+/* Logical device number */
+#define LDN_FDC			0
+#define LDN_IDE1		1
+#define LDN_IDE2		2
+#define LDN_PARPORT		3
+#define LDN_COM1		4
+#define LDN_COM2		5
+#define LDN_RTC			6
+#define LDN_KBC			7
+#define LDN_AUXIO		8
+
+/* Configuration port and key */
+#define CONFIG_PORT		0x3f0
+#define INDEX_PORT		CONFIG_PORT
+#define DATA_PORT		0x3f1
+#define CONFIG_ENTER		0x55
+#define CONFIG_EXIT		0xaa
+
+/* Configuration index */
+#define CURRENT_LDN_INDEX	0x07
+#define POWER_CONTROL_INDEX	0x22
+#define ACTIVATE_INDEX		0x30
+#define IO_BASE_HI_INDEX	0x60
+#define IO_BASE_LO_INDEX	0x61
+#define IRQ_SELECT_INDEX	0x70
+#define DMA_SELECT_INDEX	0x74
+
+#define GPIO46_INDEX		0xc6
+#define GPIO47_INDEX		0xc7
+
+/* UART stuff. Only for debugging.  */
+/* UART Register */
+
+#define UART_RBR	0x0	/* Receiver Buffer Register (Read Only) */
+#define UART_THR	0x0	/* Transmitter Holding Register (Write Only) */
+#define UART_IER	0x2	/* Interrupt Enable Register */
+#define UART_IIR	0x4	/* Interrupt Ident Register (Read Only) */
+#define UART_FCR	0x4	/* FIFO Control Register (Write Only) */
+#define UART_LCR	0x6	/* Line Control Register */
+#define UART_MCR	0x8	/* MODEM Control Register */
+#define UART_LSR	0xa	/* Line Status Register */
+#define UART_MSR	0xc	/* MODEM Status Register */
+#define UART_SCR	0xe	/* Scratch Register */
+#define UART_DLL	0x0	/* Divisor Latch (LS) */
+#define UART_DLM	0x2	/* Divisor Latch (MS) */
+
+#ifndef __ASSEMBLY__
+typedef struct uart_reg {
+	volatile __u16 rbr;
+	volatile __u16 ier;
+	volatile __u16 iir;
+	volatile __u16 lcr;
+	volatile __u16 mcr;
+	volatile __u16 lsr;
+	volatile __u16 msr;
+	volatile __u16 scr;
+} uart_reg;
+#endif /* ! __ASSEMBLY__ */
+
+/* Alias for Write Only Register */
+
+#define thr	rbr
+#define tcr	iir
+
+/* Alias for Divisor Latch Register */
+
+#define dll	rbr
+#define dlm	ier
+#define fcr	iir
+
+/* Interrupt Enable Register */
+
+#define IER_ERDAI	0x0100	/* Enable Received Data Available Interrupt */
+#define IER_ETHREI	0x0200	/* Enable Transmitter Holding Register Empty Interrupt */
+#define IER_ELSI	0x0400	/* Enable Receiver Line Status Interrupt */
+#define IER_EMSI	0x0800	/* Enable MODEM Status Interrupt */
+
+/* Interrupt Ident Register */
+
+#define IIR_IP		0x0100	/* "0" if Interrupt Pending */
+#define IIR_IIB0	0x0200	/* Interrupt ID Bit 0 */
+#define IIR_IIB1	0x0400	/* Interrupt ID Bit 1 */
+#define IIR_IIB2	0x0800	/* Interrupt ID Bit 2 */
+#define IIR_FIFO	0xc000	/* FIFOs enabled */
+
+/* FIFO Control Register */
+
+#define FCR_FEN		0x0100	/* FIFO enable */
+#define FCR_RFRES	0x0200	/* Receiver FIFO reset */
+#define FCR_TFRES	0x0400	/* Transmitter FIFO reset */
+#define FCR_DMA		0x0800	/* DMA mode select */
+#define FCR_RTL		0x4000	/* Receiver triger (LSB) */
+#define FCR_RTM		0x8000	/* Receiver triger (MSB) */
+
+/* Line Control Register */
+
+#define LCR_WLS0	0x0100	/* Word Length Select Bit 0 */
+#define LCR_WLS1	0x0200	/* Word Length Select Bit 1 */
+#define LCR_STB		0x0400	/* Number of Stop Bits */
+#define LCR_PEN		0x0800	/* Parity Enable */
+#define LCR_EPS		0x1000	/* Even Parity Select */
+#define LCR_SP		0x2000	/* Stick Parity */
+#define LCR_SB		0x4000	/* Set Break */
+#define LCR_DLAB	0x8000	/* Divisor Latch Access Bit */
+
+/* MODEM Control Register */
+
+#define MCR_DTR		0x0100	/* Data Terminal Ready */
+#define MCR_RTS		0x0200	/* Request to Send */
+#define MCR_OUT1	0x0400	/* Out 1 */
+#define MCR_IRQEN	0x0800	/* IRQ Enable */
+#define MCR_LOOP	0x1000	/* Loop */
+
+/* Line Status Register */
+
+#define LSR_DR		0x0100	/* Data Ready */
+#define LSR_OE		0x0200	/* Overrun Error */
+#define LSR_PE		0x0400	/* Parity Error */
+#define LSR_FE		0x0800	/* Framing Error */
+#define LSR_BI		0x1000	/* Break Interrupt */
+#define LSR_THRE	0x2000	/* Transmitter Holding Register Empty */
+#define LSR_TEMT	0x4000	/* Transmitter Empty */
+#define LSR_FIFOE	0x8000	/* Receiver FIFO error */
+
+/* MODEM Status Register */
+
+#define MSR_DCTS	0x0100	/* Delta Clear to Send */
+#define MSR_DDSR	0x0200	/* Delta Data Set Ready */
+#define MSR_TERI	0x0400	/* Trailing Edge Ring Indicator */
+#define MSR_DDCD	0x0800	/* Delta Data Carrier Detect */
+#define MSR_CTS		0x1000	/* Clear to Send */
+#define MSR_DSR		0x2000	/* Data Set Ready */
+#define MSR_RI		0x4000	/* Ring Indicator */
+#define MSR_DCD		0x8000	/* Data Carrier Detect */
+
+/* Baud Rate Divisor */
+
+#define UART_CLK	(1843200)	/* 1.8432 MHz */
+#define UART_BAUD(x)	(UART_CLK / (16 * (x)))
+
+/* RTC register definition */
+#define RTC_SECONDS             0
+#define RTC_SECONDS_ALARM       1
+#define RTC_MINUTES             2
+#define RTC_MINUTES_ALARM       3
+#define RTC_HOURS               4
+#define RTC_HOURS_ALARM         5
+#define RTC_DAY_OF_WEEK         6
+#define RTC_DAY_OF_MONTH        7
+#define RTC_MONTH               8
+#define RTC_YEAR                9
+#define RTC_FREQ_SELECT		10
+# define RTC_UIP 0x80
+# define RTC_DIV_CTL 0x70
+/* This RTC can work under 32.768KHz clock only.  */
+# define RTC_OSC_ENABLE 0x20
+# define RTC_OSC_DISABLE 0x00
+#define RTC_CONTROL     	11
+# define RTC_SET 0x80
+# define RTC_PIE 0x40
+# define RTC_AIE 0x20
+# define RTC_UIE 0x10
+# define RTC_SQWE 0x08
+# define RTC_DM_BINARY 0x04
+# define RTC_24H 0x02
+# define RTC_DST_EN 0x01
+
+#endif  /* __ASM_SH_SMC37C93X_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index ab5383e0a..3bb876274 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -165,18 +165,18 @@ do {					\
 /*
  * Back to P1 area.
  */
-#define back_to_P1()				\
-do {						\
-	unsigned long __dummy;			\
-	__asm__ __volatile__(			\
-		"nop;nop;nop;nop;nop;nop\n\t"	\
-		"mov.l	1f, %0\n\t"		\
-		"jmp	@%0\n\t"		\
-		" nop\n\t"			\
-		".balign 4\n"			\
-		"1:	.long 2f\n"		\
-		"2:"				\
-		: "=&r" (__dummy));		\
+#define back_to_P1()					\
+do {							\
+	unsigned long __dummy;				\
+	__asm__ __volatile__(				\
+		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
+		"mov.l	1f, %0\n\t"			\
+		"jmp	@%0\n\t"			\
+		" nop\n\t"				\
+		".balign 4\n"				\
+		"1:	.long 2f\n"			\
+		"2:"					\
+		: "=&r" (__dummy));			\
 } while (0)
 
 /* For spinlocks etc */
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index f927716b2..0594308fe 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -314,16 +314,16 @@ __syscall_return(type,__sc0); \
 #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
 type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
 { \
-register long __sc0 __asm__ ("$r3") = __NR_##name; \
+register long __sc3 __asm__ ("$r3") = __NR_##name; \
 register long __sc4 __asm__ ("$r4") = (long) arg1; \
 register long __sc5 __asm__ ("$r5") = (long) arg2; \
 register long __sc6 __asm__ ("$r6") = (long) arg3; \
 register long __sc7 __asm__ ("$r7") = (long) arg4; \
-register long __sc2 __asm__ ("$r0") = (long) arg5; \
+register long __sc0 __asm__ ("$r0") = (long) arg5; \
 __asm__ __volatile__ ("trapa	#0x15" \
 	: "=z" (__sc0) \
 	: "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7),  \
-	  "r" (__sc7), "r" (__sc2) \
+	  "r" (__sc3) \
 	: "memory" ); \
 __syscall_return(type,__sc0); \
 }