Merge with Linux 2.2.8.

1 files changed, 57 insertions, 9 deletions

diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index b9a900406..bad6a838a 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -1,4 +1,4 @@
-/* $Id: irq.h,v 1.10 1998/05/29 06:00:39 ecd Exp $
+/* $Id: irq.h,v 1.14 1998/12/19 11:05:41 davem Exp $
  * irq.h: IRQ registers on the 64-bit Sparc.
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
@@ -15,23 +15,71 @@ struct devid_cookie {
 	int dummy;
 };
 
-/* You should not mess with this directly. That's the job of irq.c. */
+/* You should not mess with this directly. That's the job of irq.c.
+ *
+ * If you make changes here, please update hand coded assembler of
+ * SBUS/floppy interrupt handler in entry.S -DaveM
+ *
+ * This is currently one DCACHE line, two buckets per L2 cache
+ * line.  Keep this in mind please.
+ */
 struct ino_bucket {
-	unsigned short ino;
-	short imap_off;
-	unsigned short pil;
-	unsigned short flags;
-	unsigned int *iclr;
+	/* Next handler in per-CPU PIL worklist.  We know that
+	 * bucket pointers have the high 32-bits clear, so to
+	 * save space we only store the bits we need.
+	 */
+/*0x00*/unsigned int irq_chain;
+
+	/* PIL to schedule this IVEC at. */
+/*0x04*/unsigned char pil;
+
+	/* If an IVEC arrives while irq_info is NULL, we
+	 * set this to notify request_irq() about the event.
+	 */
+/*0x05*/unsigned char pending;
+
+	/* Miscellaneous flags. */
+/*0x06*/unsigned char flags;
+
+	/* Unused right now, but we will use it for proper
+	 * enable_irq()/disable_irq() nesting.
+	 */
+/*0x07*/unsigned char __unused;
+
+	/* Reference to handler for this IRQ.  If this is
+	 * non-NULL this means it is active and should be
+	 * serviced.  Else the pending member is set to one
+	 * and later registry of the interrupt checks for
+	 * this condition.
+	 *
+	 * Normally this is just an irq_action structure.
+	 * But, on PCI, if multiple interrupt sources behind
+	 * a bridge have multiple interrupt sources that share
+	 * the same INO bucket, this points to an array of
+	 * pointers to four IRQ action structures.
+	 */
+/*0x08*/void *irq_info;
+
+	/* Sun5 Interrupt Clear Register. */
+/*0x10*/unsigned int *iclr;
+
+	/* Sun5 Interrupt Mapping Register. */
+/*0x18*/unsigned int *imap;
+
 };
 
-#define __irq_ino(irq) ((struct ino_bucket *)(unsigned long)(irq))->ino
+#define NUM_IVECS	8192
+extern struct ino_bucket ivector_table[NUM_IVECS];
+
+#define __irq_ino(irq) \
+        (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
 
 static __inline__ char *__irq_itoa(unsigned int irq)
 {
 	static char buff[16];
 
-	sprintf(buff, "%d,%x", __irq_pil(irq), __irq_ino(irq));
+	sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
 	return buff;
 }