Merge with Linux 2.3.43.

14 files changed, 17 insertions, 1440 deletions

diff --git a/include/asm-sparc/ap1000/DdvReqTable.h b/include/asm-sparc/ap1000/DdvReqTable.h
deleted file mode 100644
index 78ffacfd3..000000000
--- a/include/asm-sparc/ap1000/DdvReqTable.h
+++ /dev/null
@@ -1,107 +0,0 @@
-  /*
-   * Copyright 1996 The Australian National University.
-   * Copyright 1996 Fujitsu Laboratories Limited
-   * 
-   * This software may be distributed under the terms of the Gnu
-   * Public License version 2 or later
-  */
-/*
- *	Request table size
- */
-
-#define	TABLE_SIZE	200
-
-/*
- *	Indirect memory address table size
- */
-
-#define	MTABLE_SIZE	1000
-
-static inline int INC_T(int a)
-{
-	return (++a == TABLE_SIZE?0:a);
-}
-
-static inline int INC_ML(int a)
-{
-	return (++a == MTABLE_SIZE?0:a);
-}
-
-/*
- *	Status of requiest table
- */
-
-#define	DDV_ERROR_RETURN	0
-#define	DDV_NORMAL_RETURN	1
-#define	DDV_REQ_FREE		2
-#define DDV_DISKREAD_REQ	3
-#define	DDV_DISKWRITE_REQ	4
-#define DDV_RAWREAD_REQ		5
-#define	DDV_RAWWRITE_REQ	6
-#define DDV_CACHEPOSTALL_REQ    11
-#define DDV_CACHEFLUSHALL_REQ    12
-#define DDV_CAPACITY_REQ        13
-
-/*
- *      Specify type of interrupt (set by opiu in PBUF1)
- */
-
-#define DDV_PRINTK_INTR  1
-#define DDV_MLIST_INTR   2
-#define DDV_READY_INTR   3
-#define DDV_REQCOMP_INTR 4 
-
-struct  RequestInformation {
-	volatile int	status;
-	int rtn;
-	unsigned bnum;
-	int argv[8];
-};
-
-struct DiskInfo {
-  u_long blocks;
-  u_long blk_size;
-  int pad[8];
-  unsigned ptrs[4];
-};
-
-struct RequestTable{
-  volatile unsigned cell_pointer;	/* Cell requiest pointer */
-  volatile unsigned ddv_pointer;	/* DDV operation pointer */
-  struct  RequestInformation async_info[TABLE_SIZE];
-  volatile unsigned start_mtable;
-  volatile unsigned end_mtable;
-  unsigned mtable[MTABLE_SIZE];
-};
-
-#define PRINT_BUFS 32
-
-struct OPrintBuf {
-  char *fmt;
-  int args[6];
-};
-
-struct OPrintBufArray {
-  volatile unsigned option_counter;
-  volatile unsigned cell_counter;
-  struct OPrintBuf bufs[PRINT_BUFS];  
-};
-
-#define ALIGN_SIZE 16
-#define ALIGN_BUFS 128
-#define ALIGN_BUF_SIZE 1024
-
-struct AlignBuf {
-  char *dest;
-  unsigned size;
-  int offset;
-  char buf[ALIGN_BUF_SIZE+2*ALIGN_SIZE];
-};
-
-struct OAlignBufArray {
-  volatile unsigned option_counter;
-  volatile unsigned cell_counter;
-  struct AlignBuf bufs[ALIGN_BUFS];
-};
-
-
diff --git a/include/asm-sparc/ap1000/apbif.h b/include/asm-sparc/ap1000/apbif.h
deleted file mode 100644
index 6ef9bf0b6..000000000
--- a/include/asm-sparc/ap1000/apbif.h
+++ /dev/null
@@ -1,205 +0,0 @@
-  /*
-   * Copyright 1996 The Australian National University.
-   * Copyright 1996 Fujitsu Laboratories Limited
-   * 
-   * This software may be distributed under the terms of the Gnu
-   * Public License version 2 or later
-  */
-
-/*
-**	BIF data registers (system mode)
-*/
-#define BIF_DATA 	(BIF+0x0000)	/* BIF send and receive data registe	*/
-#define BIF_EDATA  	(BIF+0x0004)	/* BIF end data register 				*/
-/*
-**	BIF data registers (user mode) 
-*/
-#define UBIF_DATA 	(UBIF+0x0000)	/* BIF send and receive data registe	*/
-#define UBIF_EDATA  (UBIF+0x0004)	/* BIF end data register 				*/
-
-/*
-**	BIF scatter and gather parameter register (system mode) 
-*/
-#define BIF_X0SK 	(BIF+0x0010)	/* initial X-skip register 			*/
-#define BIF_XSK 	(BIF+0x0014)	/* X-skip register 					*/
-#define BIF_XSZ 	(BIF+0x0018)	/* X-size register 					*/
-
-#define BIF_Y0SK 	(BIF+0x001c)	/* initial Y-skip register 			*/
-#define BIF_YSK 	(BIF+0x0020)	/* Y-skip register 					*/
-#define BIF_YSZ 	(BIF+0x0024)	/* Y-size register 					*/
-
-#define BIF_CX0SK 	(BIF+0x0028)	/* initial counter of X-skip 		*/
-#define BIF_CXSK 	(BIF+0x002c)	/* X-skip counter 					*/
-#define BIF_CXSZ 	(BIF+0x0030)	/* X-size counter 					*/
-
-#define BIF_CY0SK 	(BIF+0x0034)	/* initial counter of Y-skip 		*/
-#define BIF_CYSK 	(BIF+0x0038)	/* Y-skip counter 					*/
-#define BIF_CYSZ 	(BIF+0x003c)	/* Y-size counter 					*/
-
-#define BIF_TTL 	(BIF+0x0040)	/* number of data transfer register */
-#define BIF_CTTL 	(BIF+0x0044)	/* number of data transfer counter	*/
-
-/*
-**	BIF scatter and gather parameter register (user mode) 
-*/
-#define UBIF_X0SK 	(UBIF+0x0010)	/* initial X-skip register 			*/
-#define UBIF_XSK 	(UBIF+0x0014)	/* X-skip register 					*/
-#define UBIF_XSZ 	(UBIF+0x0018)	/* X-size register 					*/
-
-#define UBIF_Y0SK 	(UBIF+0x001c)	/* initial Y-skip register 			*/
-#define UBIF_YSK 	(UBIF+0x0020)	/* Y-skip register 					*/
-#define UBIF_YSZ 	(UBIF+0x0024)	/* Y-size register 					*/
-
-#define UBIF_CX0SK 	(UBIF+0x0028)	/* initial counter of X-skip 		*/
-#define UBIF_CXSK 	(UBIF+0x002c)	/* X-skip counter 					*/
-#define UBIF_CXSZ 	(UBIF+0x0030)	/* X-size counter 					*/
-
-#define UBIF_CY0SK 	(UBIF+0x0034)	/* initial counter of Y-skip 		*/
-#define UBIF_CYSK 	(UBIF+0x0038)	/* Y-skip counter 					*/
-#define UBIF_CYSZ 	(UBIF+0x003c)	/* Y-size counter 					*/
-
-#define UBIF_TTL 	(UBIF+0x0040)	/* number of data transfer register */
-#define UBIF_CTTL 	(UBIF+0x0044)	/* number of data transfer counter	*/
-
-/*
-**	BIF control registers (system mode)
-*/
-#define BIF_CIDR0 	(BIF+0x0048)	/* cell-id register 0 					*/
-#define BIF_CIDR1 	(BIF+0x004c)	/* cell-id register 1 (for cell mode) 	*/
-#define BIF_CIDR2 	(BIF+0x0050)	/* cell-id register 2 					*/
-#define BIF_CIDR3 	(BIF+0x0054)	/* cell-id register 3 					*/
-#define BIF_HEADER 	(BIF+0x0058)	/* header register 						*/
-#define BIF_INTR 	(BIF+0x006c)	/* BIF interrupt control register 		*/
-#define BIF_SDCSR 	(BIF+0x0070)	/* BIF data control set register 		*/
-#define BIF_RDCSR 	(BIF+0x0074)	/* BIF data control reset reregister	*/
-#define BIF_MHOCR 	(BIF+0x0078)	/* BIF extentional control reregister 	*/
-
-/*
-**	BIF control registers (user mode)
-*/
-#define UBIF_CIDR0 	(UBIF+0x0048)	/* cell-id register 0 					*/
-#define UBIF_CIDR1 	(UBIF+0x004c)	/* cell-id register 1 (for cell mode) 	*/
-#define UBIF_CIDR2 	(UBIF+0x0050)	/* cell-id register 2 					*/
-#define UBIF_CIDR3 	(UBIF+0x0054)	/* cell-id register 3 					*/
-#define UBIF_HEADER (UBIF+0x0058)	/* header register 						*/
-#define UBIF_INTR 	(UBIF+0x006c)	/* BIF interrupt control register 		*/
-#define UBIF_SDCSR 	(UBIF+0x0070)	/* BIF data control set register 		*/
-#define UBIF_RDCSR 	(UBIF+0x0074)	/* BIF data control reset reregister	*/
-#define UBIF_MHOCR 	(UBIF+0x0078)	/* BIF extentional control reregister 	*/
-
-/*
-** bit assignment 
-*/
-#define BIF_HEADER_ID	 0xffff0000	/* cell-id   		*/
-#define BIF_HEADER_BR	 0x00008000	/* broad bit 		*/
-#define BIF_HEADER_IS	 0x00006000	/* ID select		*/
-#define BIF_HEADER_IS_00 0x00000000 
-#define BIF_HEADER_IS_01 0x00002000 
-#define BIF_HEADER_IS_10 0x00004000 
-#define BIF_HEADER_IS_11 0x00006000 
-#define BIF_HEADER_IN	 0x00001000	/* interrupt bit	*/
-#define BIF_HEADER_LS	 0x00000800	/* line send		*/
-#define BIF_HEADER_SC	 0x00000400	/* scatter bit 		*/
-#define BIF_HEADER_HS	 0x00000200	/* header strip		*/
-#define BIF_HEADER_RS	 0x00000100	/* bus release 		*/
-
-#define BIF_HEADER_ID_SHIFT 16
-
-#define BIF_INTR_GS		0x00020000	/* grant interrupt select 		*/
-#define BIF_INTR_GM		0x00010000	/* grant interrupt mask			*/
-#define BIF_INTR_GI		0x00008000	/* grant interrupt request		*/
-#define BIF_INTR_HS		0x00004000	/* header interrupt select		*/
-#define BIF_INTR_HM		0x00002000	/* header interrupt mask		*/
-#define BIF_INTR_HI		0x00001000	/* header interrupt request		*/
-#define BIF_INTR_SS		0x00000800	/* send interrupt select		*/
-#define BIF_INTR_SM		0x00000400	/* send interrupt mask			*/
-#define BIF_INTR_SI		0x00000200	/* send interrupt request		*/
-#define BIF_INTR_RS		0x00000100	/* receive interrupt select		*/
-#define BIF_INTR_RM		0x00000080	/* receive interrupt mask		*/
-#define BIF_INTR_RI		0x00000040	/* receive interrupt request	*/
-#define BIF_INTR_ES		0x00000020	/* error interrupt select 		*/
-#define BIF_INTR_EM		0x00000010	/* error interrupt mask 		*/
-#define BIF_INTR_EI		0x00000008	/* error interrupt request 		*/
-#define BIF_INTR_AS		0x00000004	/* attention interrupt select 	*/
-#define BIF_INTR_AM		0x00000002	/* attention interrupt mask 	*/
-#define BIF_INTR_AI		0x00000001	/* attention interrupt request  */
-
-#define BIF_SDCSR_ER    0x7fffc000  /* error  detected by BIF */
-#define BIF_SDCSR_PE	0x80000000	/* detect parity error in sync			*/
-#define BIF_SDCSR_SP	0x40000000	/* parity error in sync					*/
-#define BIF_SDCSR_LP	0x20000000	/* L-bus parity error					*/
-#define BIF_SDCSR_LR	0x10000000	/* */
-#define BIF_SDCSR_LW	0x08000000	/* */
-#define BIF_SDCSR_AL	0x04000000	/* specify end bit except of end data	*/
-#define BIF_SDCSR_SS	0x02000000	/* request bit but masked by slow sync	*/
-#define BIF_SDCSR_SC	0x01000000	/* clear bit but masked by slow sync	*/
-#define BIF_SDCSR_SY	0x00800000	/* set bit but masked by slow status	*/
-#define BIF_SDCSR_FS	0x00400000	/* request bit but masked by fast sync	*/
-#define BIF_SDCSR_FC	0x00200000	/* clear bit but masked by fast sync	*/
-#define BIF_SDCSR_FY	0x00100000	/* set bit but masked by fast status	*/
-#define BIF_SDCSR_CP	0x00080000	/* parity error in commnad bus			*/
-#define BIF_SDCSR_FP	0x00040000	/* execute scatter or gather but FN=0	*/
-#define BIF_SDCSR_PS	0x00020000	/* header receive error 				*/
-#define BIF_SDCSR_RA	0x00010000	/* change scatter,gather parameter		*/
-#define BIF_SDCSR_PA	0x00008000	/* check if send or receive error		*/
-#define BIF_SDCSR_DL	0x00004000	/* lost data							*/
-#define BIF_SDCSR_BB	0x00002000	/* check if some BIF use command bus	*/
-#define BIF_SDCSR_BG	0x00001000	/* check if command bus got				*/
-#define BIF_SDCSR_BR	0x00000800	/* request command bus					*/
-#define BIF_SDCSR_CN	0x00000400	/* release BIF from command bus			*/
-#define BIF_SDCSR_FN	0x00000200	/* scatter gather enable				*/
-#define BIF_SDCSR_EB	0x00000100	/* send data that have end bit			*/
-#define BIF_SDCSR_TB	0x000000E0	/* data in send FIFO					*/
-#define BIF_SDCSR_TB4	0x00000080
-#define BIF_SDCSR_TB2	0x00000040
-#define BIF_SDCSR_TB1	0x00000020
-#define BIF_SDCSR_RB	0x0000001c	/* data in receive FIFO					*/
-#define BIF_SDCSR_RB4	0x00000010
-#define BIF_SDCSR_RB2	0x00000008	
-#define BIF_SDCSR_RB1	0x00000004	
-#define BIF_SDCSR_DE	0x00000002	/* DMA interface enable bitr			*/
-#define BIF_SDCSR_DR	0x00000001	/* data transfer direction				*/
-
-#define BIF_RDCSR_ER    BIF_SDCSR_ER    /* error  detected by BIF */
-#define BIF_RDCSR_PE	BIF_SDCSR_PE	/* detect parity error in sync		*/
-#define BIF_RDCSR_SP	BIF_SDCSR_SP	/* parity error in sync	  */
-#define BIF_RDCSR_LP	BIF_SDCSR_LP	/* L-bus parity error	  */
-#define BIF_RDCSR_LR	BIF_SDCSR_LR	/* */
-#define BIF_RDCSR_LW	BIF_SDCSR_LW	/* */
-#define BIF_RDCSR_AL	BIF_SDCSR_AL	/* specify end bit except of end data */
-#define BIF_RDCSR_SS	BIF_SDCSR_SS	/* request bit but masked by slow sync	*/
-#define BIF_RDCSR_SC	BIF_SDCSR_SC	/* clear bit but masked by slow sync  */
-#define BIF_RDCSR_SY	BIF_SDCSR_SY	/* set bit but masked by slow status  */
-#define BIF_RDCSR_FS	BIF_SDCSR_FS	/* request bit but masked by fast sync*/
-#define BIF_RDCSR_FC	BIF_SDCSR_FC	/* clear bit but masked by fast sync  */
-#define BIF_RDCSR_FY	BIF_SDCSR_FY	/* set bit but masked by fast status  */
-#define BIF_RDCSR_CP	BIF_SDCSR_CP	/* parity error in commnad bus        */
-#define BIF_RDCSR_FP	BIF_SDCSR_FP	/* execute scatter or gather but FN=0 */
-#define BIF_RDCSR_PS	BIF_SDCSR_PS	/* header receive error 			*/
-#define BIF_RDCSR_RA	BIF_SDCSR_RA	/* change scatter,gather parameter		*/
-#define BIF_RDCSR_DL	BIF_SDCSR_DL	/* lost data					*/
-#define BIF_RDCSR_PA	BIF_SDCSR_PA	/* check if send or receive error	  */
-#define BIF_RDCSR_BB	BIF_SDCSR_BB	/* check if some BIF use command bus  */
-#define BIF_RDCSR_BG	BIF_SDCSR_BG	/* check if command bus got		*/
-#define BIF_RDCSR_BR	BIF_SDCSR_BR	/* request command bus			*/
-#define BIF_RDCSR_CN	BIF_SDCSR_CN	/* release BIF from command bus	*/
-#define BIF_RDCSR_EB	BIF_SDCSR_EB	/* send data that have end bit	*/
-#define BIF_RDCSR_TB	BIF_SDCSR_TB	/* data in send FIFO			*/
-#define BIF_RDCSR_RB	BIF_SDCSR_RB	/* data in receive FIFO			*/
-#define BIF_RDCSR_DE	BIF_SDCSR_DE	/* DMA interface enable bitr	*/
-#define BIF_RDCSR_DR	BIF_SDCSR_DR	/* data transfer direction		*/
-#define BIF_RDCSR_FN	BIF_SDCSR_FN	/* scatter gather enable		*/
-
-#define BIF_MHOCR_RS	0x00000800		/* bif reset						*/
-#define BIF_MHOCR_RC	0x00000400		/* commnad bus circuit reset		*/
-#define BIF_MHOCR_RI	0x00000200		/* remove input buffer data			*/
-#define BIF_MHOCR_RO	0x00000100		/* remove output buffer data		*/
-#define BIF_MHOCR_BA	0x00000008		/* command bus arbitlater reset		*/
-#define BIF_MHOCR_MD	0x00000006		/* command bus mode					*/
-#define BIF_MHOCR_AT	0x00000001		/* command bus attention signal		*/
-
-#define BIF_MHOCR_MD_NORMAL	0x00000006	/* command bus mode [normal]		*/
-#define BIF_MHOCR_MD_BUSWGR	0x00000004	/* command bus mode [bus gather]	*/
-#define BIF_MHOCR_MD_SETCID	0x00000002	/* command bus mode [set cid]		*/
-
-
diff --git a/include/asm-sparc/ap1000/aplib.h b/include/asm-sparc/ap1000/aplib.h
deleted file mode 100644
index 55e2f528d..000000000
--- a/include/asm-sparc/ap1000/aplib.h
+++ /dev/null
@@ -1,119 +0,0 @@
-  /*
-   * Copyright 1996 The Australian National University.
-   * Copyright 1996 Fujitsu Laboratories Limited
-   * 
-   * This software may be distributed under the terms of the Gnu
-   * Public License version 2 or later
-  */
-
-/* aplib kernel interface definition */
-
-#ifndef _APLIB_H_
-#define _APLIB_H_
-
-struct aplib_struct {
-	unsigned *ringbuf;
-	unsigned write_pointer, read_pointer; /* in words */
-	unsigned ringbuf_size; /* in words */
-	unsigned rbuf_counter; /* read messages */
-	unsigned rbuf_flag1, rbuf_flag2; /* received messages */
-	unsigned *physical_cid; /* logical to physical mapping */
-	unsigned *rel_cid;      /* logical to relative (RTC) mapping */
-	unsigned numcells; /* number of logical cells */
-	unsigned numcells_x; /* number of logical cells in x direction */
-	unsigned numcells_y; /* number of logical cells in y direction */
-	unsigned cid, tid;      /* this cells logical cell ID and task ID */
-	unsigned cidx, cidy;    /* logical cell id in x and y direction */
-	unsigned ack_flag, ack_request;
-	unsigned ok_x, ok_y, ok_xy; /* whether hardware x, y and xy sends are allowed */
-};
-
-
-/*
- * the system ringbuffer structure
- * this is also the old way that tasks accessed the MSC hardware
- */
-struct ringbuf_struct {
-	void *ringbuf; /* pointer to the ringbuf */
-	void *shared; /* pointer to the shared page */
-	int order; /* arg to __get_free_pages */
-	unsigned write_ptr; /* write pointer into the ringbuf */
-	unsigned vaddr; /* base virtual address of ringbuf for task */
-	unsigned frag_count; /* how many words in the frag queue */
-	unsigned frag_len; /* how many words expected in the frag queue */
-	unsigned sq_fragment[16]; /* if the task switches part way through
-				     an op then shove the partial op here */
-};
-
-
-#define APLIB_INIT    1
-#define APLIB_SYNC    2
-#define APLIB_GET     3
-#define APLIB_PUT     4
-#define APLIB_SEND    5
-#define APLIB_PROBE   6
-#define APLIB_POLL    7
-#define APLIB_XSEND   8
-#define APLIB_YSEND   9
-#define APLIB_XYSEND 10
-#define APLIB_XPUT   11
-#define APLIB_YPUT   12
-#define APLIB_XYPUT  13
-
-
-/* message kinds */
-#define RBUF_SYSTEM  0
-#define RBUF_SEND    1
-#define RBUF_X_BRD   2
-#define RBUF_Y_BRD   3
-#define RBUF_XY_BRD  4
-#define RBUF_RPC     5
-#define RBUF_GET     6
-#define RBUF_MPI     7
-#define RBUF_BIGSEND 8
-#define RBUF_SEEN   0xE
-#define RBUF_READ   0xF
-
-#define APLIB_PAGE_BASE 0xd0000000
-#define APLIB_PAGE_LEN  8192
-
-struct aplib_init {
-	unsigned numcells, cid;
-	unsigned numcells_x, numcells_y;
-	unsigned *phys_cells; /* physical cell list */
-	unsigned *ringbuffer;  /* pointer to user supplied ring buffer */
-	unsigned ringbuf_size; /* in words */
-};
-
-
-struct aplib_putget {
-	unsigned cid;
-	unsigned *src_addr, *dest_addr;
-	unsigned size; /* in words */
-	unsigned *dest_flag, *src_flag;
-	unsigned ack;
-};
-
-
-struct aplib_send {
-	/* the ordering here is actually quite important - the parts to be
-	   read by the bigrecv function must be in the first 24 bytes */
-	unsigned src_addr;
-	unsigned size;
-	unsigned info1, info2;
-	unsigned flag_addr;
-	volatile unsigned flag;
-	unsigned type;
-	unsigned tag;
-	unsigned cid;
-};
-
-#ifdef __KERNEL__
-#define MAX_PUT_SIZE (1024*1024 - 1) /* in words */
-#define SMALL_SEND_THRESHOLD 128
-
-
-#endif
-
-#endif /* _APLIB_H_ */
-
diff --git a/include/asm-sparc/ap1000/apreg.h b/include/asm-sparc/ap1000/apreg.h
deleted file mode 100644
index bf1ea66d3..000000000
--- a/include/asm-sparc/ap1000/apreg.h
+++ /dev/null
@@ -1,619 +0,0 @@
-  /*
-   * Copyright 1996 The Australian National University.
-   * Copyright 1996 Fujitsu Laboratories Limited
-   * 
-   * This software may be distributed under the terms of the Gnu
-   * Public License version 2 or later
-  */
-/* ap1000 register definitions needed for Linux/AP+ */
-
-#ifndef _AP1000_APREG_H
-#define _AP1000_APREG_H
-#include <asm/page.h>
-#include <asm/ap1000/apservice.h>
-#include <asm/ap1000/apbif.h>
-#include <linux/threads.h>
-
-/*
- * Macros for accessing I/O registers.
- */
-#define BIF_IN(reg)	(*(volatile unsigned *)(reg))
-#define BIF_OUT(reg,v)	(*(volatile unsigned *)(reg) = (v))
-#define DMA_IN(reg)	(*(volatile unsigned *)(reg))
-#define DMA_OUT(reg,v)	(*(volatile unsigned *)(reg) = (v))
-#define MC_IN(reg)	(*(volatile unsigned *)(reg))
-#define MC_OUT(reg,v)	(*(volatile unsigned *)(reg) = (v))
-#define MSC_IN(reg)	(*(volatile unsigned *)(reg))
-#define MSC_OUT(reg,v)	(*(volatile unsigned *)(reg) = (v))
-#define MSC_IO(reg)	(*(volatile unsigned *)(reg))
-#define RTC_IO(reg)	(*(volatile unsigned *)(reg))
-#define MC_IO(reg)	(*(volatile unsigned *)(reg))
-#define OPT_IO(reg)	(*(volatile unsigned *)(reg))
-
-/*
- * B-net interface register definitions.
- */
-#define BIF 	0xfff30000	
-#define BIF_CIDR1 	(BIF+0x004c)	/* cell-id register 1 (for cell mode)*/
-#define BIF_SDCSR 	(BIF+0x0070)	/* BIF data control set register  */
-#define BIF_DATA 	(BIF+0x0000)	/* BIF send and receive data registe	*/
-#define BIF_EDATA  	(BIF+0x0004)	/* BIF end data register 		*/
-#define BIF_INTR 	(BIF+0x006c)	/* BIF interrupt control register 	*/
-
-#define SSTT_SET	(BIF+0xe0)	/* set SSTT 			*/
-#define SSTT_CLR	(BIF+0xe4)	/* clear SSTT 			*/
-#define SSTT_SMSK	(BIF+0xe8)	/* set SSTT mask		*/
-#define SSTT_CMSK	(BIF+0xec)	/* clear SSTT mask		*/
-#define SSTT_SMD	(BIF+0xf0)	/* set SSYN & SSTT mode		*/
-#define SSTT_CMD	(BIF+0xf4)	/* clear SSYN & SSTT mode	*/
-
-/*
-** FSTT registers
-*/
-#define FSTT	BIF	/*	FSTT only system mode	*/
-#define FSTT_SET	(FSTT+0xa0)	/* set FSTT 			  */
-#define FSTT_CLR	(FSTT+0xa4)	/* clear FSTT 			  */
-#define FSTT_SMSK	(FSTT+0xa8)	/* set FSTT mask		  */
-#define FSTT_CMSK	(FSTT+0xac)	/* clear FSTT mask		  */
-#define FSTT_SMD	(FSTT+0xb0)	/* set FSYN & FSTT mode		  */
-#define FSTT_CMD	(FSTT+0xb4)	/* clear FSYN & FSTT mode	  */
-#define FSTT_TIM	(FSTT+0xb8)	/* status timer			  */
-
-
-#define BIF_SDCSR_RB	0x0000001c	/* data in receive FIFO		  */
-#define BIF_SDCSR_EB	0x00000100	/* send data that have end bit	  */
-#define BIF_SDCSR_BG	0x00001000	/* check if command bus got	  */
-#define BIF_SDCSR_BR	0x00000800	/* request command bus		  */
-#define BIF_SDCSR_TB	0x000000E0	/* data in send FIFO		  */
-#define BIF_SDCSR_PE	0x80000000	/* detect parity error in sync	       	*/
-#define BIF_SDCSR_BB    0x00002000      /* check if some BIF use command bus    */
-
-#define BIF_SDCSR_RB_SHIFT 2
-#define BIF_SDCSR_TB_SHIFT 5
-
-#define BIF_INTR_GET_SH       15         /* get bus interrupt */
-#define BIF_INTR_HEADER_SH    12         /* header interrupt */
-#define BIF_INTR_SEND_SH      9          /* send interrupt */
-#define BIF_INTR_RECV_SH      6          /* receive interrupt */
-#define BIF_INTR_ERR_SH       3          /* error interrupt */
-#define BIF_INTR_ATTN_SH      0          /* attention interrupt */
-
-
-#define BIF_HEADER_HS	0x00000200	/* header strip		*/
-#define BIF_HEADER_RS	0x00000100	/* bus release 		*/
-#define BIF_HEADER_IN	0x00001000	/* interrupt bit	*/
-#define BIF_HEADER_BR   0x00008000    /* broad bit    */
-#define BIF_INTR_HS		0x00004000	/* header interrupt select  */
-#define HOST_CID      0x1000
-#define MAKE_HEADER(cid) (BIF_HEADER_IN | \
-			  ((cid)==-1?BIF_HEADER_BR:((cid)<<16) | (1<<13)))
-
-#define BIF_RDCSR 	(BIF+0x0074)	/* BIF data control reset reregister */
-
-/*
- * Interrupt levels for AP+ devices
- */
-#define APBIFGET_IRQ	1		/* have acquired B-net */
-#define APOPT0_IRQ	2		/* option interrupt level 0 */
-#define APSYNC_IRQ	3		/* sync (S-net) interrupt */
-#define APDMA_IRQ	4		/* DMA complete interrupt */
-#define APRTC_IRQ	5		/* RTC data transfer interrupt */
-#define APIPORT_IRQ	6		/* Interrupt port interrupt */
-#define APOPT1_IRQ	7		/* option interrupt level 1 */
-#define APBIF_IRQ	8		/* B-net interface interrupt */
-#define APMAS_IRQ	9		/* Send/Recv mem acc. seq. intr */
-#define APTIM1_IRQ	10		/* Timer 1 interrupt */
-#define APMSC_IRQ	11		/* MSC+ ring buf/queue spill etc. */
-#define APLBUS_IRQ	12		/* LBUS error interrupt */
-#define APATTN_IRQ	13		/* Attention interrupt */
-#define APTIM0_IRQ	14		/* Timer 0 interrupt */
-#define APMEM_IRQ	15		/* Memory error interrupt */
-
-/*
- * LBUS DMA controller register definitions
- */
-#define DMA     0xfff00000 /* dma controller address */
-#define DMA3    (DMA+0xc0) /* DMA channel 3 */
-#define DMA_DMST    0x04
-#define DMA_MADDR   0x10
-#define DMA_HSKIP   0x08
-#define DMA_HCNT    0x0a
-#define DMA_VSKIP   0x0c
-#define DMA_VCNT    0x0e
-#define DMA_DCMD    0x00
-#define DMA_HDRP    0x28
-#define DMA_DSIZE   0x02
-#define DMA_CSIZE   0x06
-#define DMA_VCNT    0x0e
-
-#define DMA_BIF_BCMD	(DMA+0x120)	/* BIF receive command register	*/
-#define	DMA_BIF_BRST	(DMA+0x124)	/* BIF receive status register */
-#define	DMA_BCMD_SA		0x40000000	/* software abort   */
-#define	DMA_DMST_AC		0x80000000	/* channel active   */
-#define DMA_DMST_RST		0xffe40000  /* reset bits and reqs */
-#define	DMA_DCMD_ST		0x80000000	/* start operation    */
-#define	DMA_DCMD_TYP_AUTO	0x30000000	/* 11: auto  */
-
-#define	DMA_DCMD_TD_MD		0x04000000	/* transfer mem->dev */
-#define	DMA_DCMD_TD_DM		0x00000000	/* transfer direction dev->mem*/
-
-#define DMA_CH2    (DMA+0x80)	/* DMA channel 2	*/
-#define DMA_CH3    (DMA+0xc0)	/* DMA channel 3	*/
-#define DMA2_DMST  (DMA_CH2+0x04)		/* DMA2 status register	  */
-#define DMA3_DMST  (DMA_CH3+0x04)		/* DMA3 status register	  */
-#define DMA2_DCMD   (DMA_CH2+0x00)		/* DMA2 command register  */
-
-#define DMA_INTR_NORMAL_SH     19               /* normal DMA interrupt */
-#define DMA_INTR_ERROR_SH      16               /* error DMA interrupt */
-
-#define	DMA_DCMD_SA		0x40000000	/* software abort     */
-
-
-#define DMA_MAX_TRANS_SIZE		(0xffff<<2)
-#define DMA_TRANS_BLOCK_SIZE	(64<<2)
-
-#define WORD_SIZE 4
-#define B2W(x)    (((x) + WORD_SIZE - 1) / WORD_SIZE)
-#define W2B(x)    ((x) * WORD_SIZE)
-
-#define DMA_GEN		0xfff00180		/* DMA general control reg */
-
-/* AP1000+ Message Controller (MSC+) */
-
-#define MSC_BASE0 0xfa008000
-
-#define MSC_SQCTRL	(MSC_BASE0 + 0x0)	/* Send Queue control */
-
-/* bits in MSC_SQCTRL */
-#define MSC_SQC_STABLE	0x400			/* Send Queue stable */
-#define MSC_SQC_MODE	0x300			/* Send Queue mode: */
-#define MSC_SQC_MODE_BLOCK	0			/* blocking */
-#define MSC_SQC_MODE_THRU	0x100			/* through */
-#define MSC_SQC_MODE_NORMAL	0x200			/* or normal */
-#define MSC_SQC_SPLF_SH		3		/* bit# for spill flags */
-#define MSC_SQC_SPLF_M		0x1f		/* 5 bits wide */
-#define MSC_SQC_REPLYF	0x080			/* Reply queue full */
-#define MSC_SQC_REMRF	0x040			/* Remote reply queue full */
-#define MSC_SQC_USERF	0x020			/* User queue full */
-#define MSC_SQC_REMAF	0x010			/* Remote access queue full */
-#define MSC_SQC_SYSF	0x008			/* System queue full */
-#define MSC_SQC_PAUSE	0x004			/* Send Queue pause */
-#define MSC_SQC_RMODE	0x003			/* Requested mode: */
-#define MSC_SQC_RMODE_BLOCK	0			/* blocking */
-#define MSC_SQC_RMODE_THRU	1			/* through */
-#define MSC_SQC_RMODE_NORMAL	2			/* or normal */
-
-#define MSC_SQPTR0	(MSC_BASE0 + 0x8)	/* Send Queue 0 pointers */
-#define MSC_SQPTR1	(MSC_BASE0 + 0x10)	/* Send Queue 1 pointers */
-#define MSC_SQPTR2	(MSC_BASE0 + 0x18)	/* Send Queue 2 pointers */
-#define MSC_SQPTR3	(MSC_BASE0 + 0x20)	/* Send Queue 3 pointers */
-#define MSC_SQPTR4	(MSC_BASE0 + 0x28)	/* Send Queue 4 pointers */
-
-/* bits in MSC_SQPTR[0-4] */
-#define MSC_SQP_MODE	(1 << 20)		/* 64/32 word queue mode */
-#define MSC_SQP_BP_SH	17			/* bit no. for base ptr */
-#define MSC_SQP_BP_M	7			/* (it's 3 bits wide) */
-#define MSC_SQP_CNT_SH	12			/* bit no. for count */
-#define MSC_SQP_CNT_M	0x1f			/* (it's 5 bits wide) */
-#define MSC_SQP_RP_SH	6			/* bit no. for read ptr */
-#define MSC_SQP_RP_M	0x3f			/* (it's 6 bits wide() */
-#define MSC_SQP_WP_SH	0			/* bit no. for write ptr */
-#define MSC_SQP_WP_M	0x3f			/* (it's 6 bits wide() */
-
-#define MSC_OPTADR	(MSC_BASE0 + 0x30)	/* option memory address */
-
-#define MSC_MASCTRL	(MSC_BASE0 + 0x38)	/* Mem Access Sequencer ctrl */
-
-/* Bits in MSC_MASCTRL */
-#define MSC_MASC_SPAUSE	0x80			/* Send MAS pause */
-#define MSC_MASC_RPAUSE	0x40			/* Recv MAS pause */
-#define MSC_MASC_SFEXIT	0x20			/* Send MAS fault/exit */
-#define MSC_MASC_RFEXIT	0x10			/* Recv MAS fault/exit */
-#define MSC_MASC_SREADY	0x08			/* Send MAS ready */
-#define MSC_MASC_RREADY	0x04			/* Recv MAS ready */
-#define MSC_MASC_SSTOP	0x02			/* Send MAS is stopped */
-#define MSC_MASC_RSTOP	0x01			/* Recv MAS is stopped */
-
-#define MSC_SMASADR	(MSC_BASE0 + 0x40)	/* Send Mem Acc Seq address */
-#define MSC_RMASADR	(MSC_BASE0 + 0x48)	/* Recv Mem Acc Seq address */
-
-#define MSC_PID		(MSC_BASE0 + 0x50)	/* Context number (proc id) */
-
-#define MSC_QWORDCNT	(MSC_BASE0 + 0x60)	/* Queue word counts */
-
-/* Fields in MSC_QWORDCNT */
-#define MSC_QWDC_SYSCNT_SH	24		/* bit# for system count */
-#define MSC_QWDC_SYSCNT_M	0x3f		/* 6 bits wide */
-#define MSC_QWDC_SYSLEN_SH	16		/* bit# for len of sys cmd */
-#define MSC_QWDC_SYSLEN_M	0x3f		/* 6 bits wide */
-#define MSC_QWDC_USRCNT_SH	8		/* bit# for user count */
-#define MSC_QWDC_USRCNT_M	0x3f		/* 6 bits wide */
-#define MSC_QWDC_USRLEN_SH	0		/* bit# for len of user cmd */
-#define MSC_QWDC_USRLEN_M	0x3f		/* 6 bits wide */
-
-#define MSC_INTR	(MSC_BASE0 + 0x70)	/* Interrupt control/status */
-
-/* Bit offsets of interrupt fields in MSC_INTR */
-#define MSC_INTR_QBMFUL_SH	28		/* Queue buffer full intr */
-#define MSC_INTR_SQFILL_SH	24		/* Send queue fill intr */
-#define MSC_INTR_RBMISS_SH	20		/* Ring buffer miss intr */
-#define MSC_INTR_RBFULL_SH	16		/* Ring buffer full intr */
-#define MSC_INTR_RMASF_SH	12		/* Recv MAS fault intr */
-#define MSC_INTR_RMASE_SH	8		/* Recv MAS error intr */
-#define MSC_INTR_SMASF_SH	4		/* Send MAS fault intr */
-#define MSC_INTR_SMASE_SH	0		/* Send MAS error intr */
-
-#define MSC_PPIO	(MSC_BASE0 + 0x1000)	/* PArallel port I/O */
-#define MSC_PACSELECT	(MSC_BASE0 + 0x1008)	/* Performance analyser sel. */
-
-#define MSC_CIDRANGE	(MSC_BASE0 + 0x1010)	/* Rel. Cell-id range limits */
-
-/* Fields in MSC_CIDRANGE */
-#define MSC_CIDR_LRX_SH		24		/* Rel. X lower limit bit# */
-#define MSC_CIDR_LRX_M		0xFF		/* it's 8 bits wide */
-#define MSC_CIDR_HRX_SH		16		/* Rel. X upper limit bit# */
-#define MSC_CIDR_HRX_M		0xFF		/* it's 8 bits wide */
-#define MSC_CIDR_LRY_SH		8		/* Rel. Y lower limit bit# */
-#define MSC_CIDR_LRY_M		0xFF		/* it's 8 bits wide */
-#define MSC_CIDR_HRY_SH		0		/* Rel. Y upper limit bit# */
-#define MSC_CIDR_HRY_M		0xFF		/* it's 8 bits wide */
-
-#define MSC_QBMPTR	(MSC_BASE0 + 0x1018)	/* Queue buffer mgr. ptrs */
-
-/* Fields in MSC_QBMPTR */
-#define MSC_QBMP_LIM_SH		24		/* Pointer limit bit# */
-#define MSC_QBMP_LIM_M		0x3F		/* (6 bits wide) */
-#define MSC_QBMP_BP_SH		16		/* Base pointer bit# */
-#define MSC_QBMP_BP_M		0xFF		/* (8 bits wide) */
-#define MSC_QBMP_WP_SH		0		/* Write pointer bit# */
-#define MSC_QBMP_WP_M		0xFFFF		/* (16 bits wide) */
-
-#define MSC_SMASTWP	(MSC_BASE0 + 0x1030)	/* Send MAS virt page etc. */
-#define MSC_SMASREG	(MSC_BASE0 + 0x1038)	/* Send MAS context etc. */
-#define MSC_RMASTWP	(MSC_BASE0 + 0x1040)	/* Recv MAS virt page etc. */
-#define MSC_RMASREG	(MSC_BASE0 + 0x1048)	/* Recv MAS context etc. */
-
-/* Bits in MSC_[SR]MASREG */
-#define MSC_MASR_CONTEXT_SH	20		/* Context at bit 20 */
-#define MSC_MASR_CONTEXT_M	0xfff		/* 12 bits wide */
-#define MSC_MASR_AVIO		8		/* Address violation bit */
-#define MSC_MASR_CMD		7		/* MAS command bits */
-#define MSC_MASR_CMD_XFER	0		/* transfer data cmd */
-#define MSC_MASR_CMD_FOP	5		/* fetch & operate cmd */
-#define MSC_MASR_CMD_INC	6		/* increment cmd (i.e. flag) */
-#define MSC_MASR_CMD_CSI	7		/* compare & swap cmd */
-
-#define MSC_HDGERRPROC	(MSC_BASE0 + 0x1050)	/* Header gen. error process */
-#define MSC_RHDERRPROC	(MSC_BASE0 + 0x1058)	/* Recv. header decoder err. */
-
-#define MSC_SMASCNT	(MSC_BASE0 + 0x1060)	/* Send MAS counters */
-
-/* Bits in MSC_SMASCNT */
-#define MSC_SMCT_ACCSZ_SH	28		/* Access size at bit 28 */
-#define MSC_SMCT_ACCSZ_M	7		/* 3 bits wide */
-#define MSC_SMCT_MCNT_SH	8		/* M(?) count at bit 8 */
-#define MSC_SMCT_MCNT_M		0xfffff		/* 20 bits wide */
-#define MSC_SMCT_ICNT_SH	0		/* I(?) count at bit 0 */
-#define MSC_SMCT_ICNT_M		0xff		/* 8 bits wide */
-
-#define MSC_IRL		(MSC_BASE0 + 0x1070)	/* highest current int req */
-#define MSC_SIMMCHK	(MSC_BASE0 + 0x1078)	/* DRAM type installed */
-
-#define MSC_SIMMCHK_MASK 0x00000008
-
-#define MSC_SQRAM	(MSC_BASE0 + 0x2000)	/* Send Queue RAM (to +23f8) */
-
-#define MSC_VERSION	(MSC_BASE0 + 0x3000)	/* MSC+ version */
-
-#define MSC_NR_RBUFS 3
-
-#define MSC_RBMBWP0	(MSC_BASE0 + 0x4000)	/* Ring buf 0 base/write ptr */
-#define MSC_RBMMODE0	(MSC_BASE0 + 0x4008)	/* Ring buf 0 mode/context */
-#define MSC_RBMBWP1	(MSC_BASE0 + 0x4010)	/* Ring buf 1 base/write ptr */
-#define MSC_RBMMODE1	(MSC_BASE0 + 0x4018)	/* Ring buf 1 mode/context */
-#define MSC_RBMBWP2	(MSC_BASE0 + 0x4020)	/* Ring buf 2 base/write ptr */
-#define MSC_RBMMODE2	(MSC_BASE0 + 0x4028)	/* Ring buf 2 mode/context */
-
-#define MSC_RBMRP0	(MSC_BASE0 + 0x5000)	/* Ring buf 0 read pointer */
-#define MSC_RBMRP1	(MSC_BASE0 + 0x6000)	/* Ring buf 1 read pointer */
-#define MSC_RBMRP2	(MSC_BASE0 + 0x7000)	/* Ring buf 2 read pointer */
-
-/* locations of queues in virtual memory */
-#define MSC_QUEUE_BASE   0xfa800000
-#define MSC_PUT_QUEUE_S  (MSC_QUEUE_BASE + 0*PAGE_SIZE)
-#define MSC_GET_QUEUE_S  (MSC_QUEUE_BASE + 1*PAGE_SIZE)
-#define MSC_XYG_QUEUE_S  (MSC_QUEUE_BASE + 2*PAGE_SIZE)
-#define MSC_SEND_QUEUE_S  (MSC_QUEUE_BASE + 3*PAGE_SIZE)
-#define MSC_CPUT_QUEUE_S  (MSC_QUEUE_BASE + 4*PAGE_SIZE)
-#define MSC_BSEND_QUEUE_S  (MSC_QUEUE_BASE + 5*PAGE_SIZE)
-#define MSC_CXYG_QUEUE_S  (MSC_QUEUE_BASE + 6*PAGE_SIZE)
-#define MSC_CGET_QUEUE_S  (MSC_QUEUE_BASE + 7*PAGE_SIZE)
-
-/* the 4 interrupt ports - physical addresses (on bus 8) */
-#define MC_INTP_0        0x80004000
-#define MC_INTP_1        0x80005000
-#define MC_INTP_2        0x80006000
-#define MC_INTP_3        0x80007000
-
-/* the address used to send a remote signal - note that 32 pages 
- are used here - none of them are mapped to anything though */
-#define MSC_REM_SIGNAL          (MSC_QUEUE_BASE + 0x10 * PAGE_SIZE)
-
-#define MSC_PUT_QUEUE   (MSC_QUEUE_BASE + 0x100*PAGE_SIZE)
-#define MSC_GET_QUEUE   (MSC_QUEUE_BASE + 0x101*PAGE_SIZE)
-#define MSC_SEND_QUEUE  (MSC_QUEUE_BASE + 0x102*PAGE_SIZE)
-#define MSC_XY_QUEUE    (MSC_QUEUE_BASE + 0x103*PAGE_SIZE)
-#define MSC_X_QUEUE     (MSC_QUEUE_BASE + 0x104*PAGE_SIZE)
-#define MSC_Y_QUEUE     (MSC_QUEUE_BASE + 0x105*PAGE_SIZE)
-#define MSC_XYG_QUEUE   (MSC_QUEUE_BASE + 0x106*PAGE_SIZE)
-#define MSC_XG_QUEUE    (MSC_QUEUE_BASE + 0x107*PAGE_SIZE)
-#define MSC_YG_QUEUE    (MSC_QUEUE_BASE + 0x108*PAGE_SIZE)
-#define MSC_CSI_QUEUE   (MSC_QUEUE_BASE + 0x109*PAGE_SIZE)
-#define MSC_FOP_QUEUE   (MSC_QUEUE_BASE + 0x10a*PAGE_SIZE)
-
-#define SYSTEM_RINGBUF_BASE    (MSC_QUEUE_BASE + 0x200*PAGE_SIZE)
-#define SYSTEM_RINGBUF_ORDER 5
-#define SYSTEM_RINGBUF_SIZE ((1<<SYSTEM_RINGBUF_ORDER)*PAGE_SIZE)
-
-#define MSC_SYSTEM_DIRECT	(MSC_QUEUE_BASE + 0x700 * PAGE_SIZE)
-#define MSC_USER_DIRECT		(MSC_QUEUE_BASE + 0x701 * PAGE_SIZE)
-#define MSC_REMOTE_DIRECT	(MSC_QUEUE_BASE + 0x702 * PAGE_SIZE)
-#define MSC_REPLY_DIRECT	(MSC_QUEUE_BASE + 0x703 * PAGE_SIZE)
-#define MSC_REMREPLY_DIRECT	(MSC_QUEUE_BASE + 0x704 * PAGE_SIZE)
-
-#define MSC_SYSTEM_DIRECT_END	(MSC_QUEUE_BASE + 0x708 * PAGE_SIZE)
-#define MSC_USER_DIRECT_END	(MSC_QUEUE_BASE + 0x709 * PAGE_SIZE)
-#define MSC_REMOTE_DIRECT_END	(MSC_QUEUE_BASE + 0x70a * PAGE_SIZE)
-#define MSC_REPLY_DIRECT_END	(MSC_QUEUE_BASE + 0x70b * PAGE_SIZE)
-#define MSC_REMREPLY_DIRECT_END	(MSC_QUEUE_BASE + 0x70c * PAGE_SIZE)
-
-/* AP1000+ Memory Controller (MC+) */
-
-#define MC_BASE0	0xfa000000
-
-#define MC_DRAM_CTRL	(MC_BASE0 + 0x0)	/* DRAM control */
-#define MC_DRAM_CHKBIT	(MC_BASE0 + 0x8)	/* DRAM check bits */
-#define MC_DRAM_ERRADR	(MC_BASE0 + 0x10)	/* DRAM error address */
-#define MC_DRAM_ERRSYN	(MC_BASE0 + 0x18)	/* DRAM error syndrome */
-
-#define MC_FREERUN	(MC_BASE0 + 0x20)	/* Free run ctr (12.5MHz) */
-#define MC_ITIMER0	(MC_BASE0 + 0x28)	/* Interval timer 0 */
-#define MC_ITIMER1	(MC_BASE0 + 0x30)	/* Interval timer 1 */
-
-#define MC_INTR		(MC_BASE0 + 0x38)	/* Interrupt control/status */
-
-/* Interrupt control/status fields in MC_INTR */
-#define MC_INTR_ECCD_SH		12		/* ECC double (uncorr.) err */
-#define MC_INTR_ECCS_SH		8		/* ECC single (corr.) error */
-#define MC_INTR_ITIM1_SH	4		/* Interval timer 1 intr */
-#define MC_INTR_ITIM0_SH	0		/* Interval timer 0 intr */
-
-#define MC_CTP		(MC_BASE0 + 0x50)	/* Context table pointer */
-
-#define MC_VBUS_FAST	(MC_BASE0 + 0x60)	/* VBus fast data mode ctrl */
-
-#define MC_INTR_PORT	(MC_BASE0 + 0x68)	/* Interrupt port ctrl/stat */
-
-/* Interrupt control/status fields in MC_INTR_PORT */
-#define MC_INTP_3_SH		12		/* port 0 (880007000) */
-#define MC_INTP_2_SH		8		/* port 1 (880006000) */
-#define MC_INTP_1_SH		4		/* port 1 (880005000) */
-#define MC_INTP_0_SH		0		/* port 1 (880004000) */
-
-#define MC_PAC_COUNT	(MC_BASE0 + 0x1000)	/* Perf. an. counters */
-#define MC_PAC_SELECT	(MC_BASE0 + 0x1008)	/* Perf. an. ctr. select */
-
-#define MC_VERSION	(MC_BASE0 + 0x3000)	/* MC+ version/date */
-
-#define MC_MMU_TLB4K	(MC_BASE0 + 0x6000)	/* MC+ TLB for 4k pages */
-#define MC_MMU_TLB256K	(MC_BASE0 + 0x7000)	/* MC+ TLB for 256k pages */
-#define MC_MMU_TLB4K_SIZE 256
-#define MC_MMU_TLB256K_SIZE 64
-
-
-/*
- * Bit values for a standard AP1000 3-bit interrupt control/status field.
- */
-#define AP_INTR_REQ		1	/* interrupt request bit */
-#define AP_INTR_MASK		2	/* interrupt mask bit (1 disables) */
-#define AP_INTR_WENABLE		4	/* enable write to mask/req bits */
-#define AP_CLR_INTR_REQ		4	/* clear req. bit (dismiss intr) */
-#define AP_CLR_INTR_MASK	5	/* clear mask bit (enable ints) */
-#define AP_SET_INTR_REQ		6	/* set request bit */
-#define AP_SET_INTR_MASK	7	/* set mask bit (disable ints) */
-
-/*
- * Bit field extraction/insertion macros.
- */
-#define EXTFIELD(val, fld)	(((val) >> fld ## _SH) & fld ## _M)
-#define MKFIELD(val, fld)	(((val) & fld ## _M) << fld ## _SH)
-#define INSFIELD(dst, val, fld)	(((dst) & ~(fld ## _M << fld ## _SH)) \
-				 | MKFIELD(val, fld))
-
-/* 
- * RTC registers 
- */
-#define RTC 0xfff10000	/*	RTC system mode	*/
-#define RTC_CSR 	(RTC+0x0010)	/* RTC control	register   */
-#define RTC_STR   	(RTC+0x0020)	/* RTC status register	  */
-#define RTC_ITRR   	(RTC+0x0030)	/* RTC interrupt register  */
-#define RTC_RSTR   	(RTC+0x0070)	/* RTC reset register	   */	 
-#define RTC_RSTR_TR		0x00008000	/* RTC through mode */
-#define RTC_RSTR_TS		0x00004000	/* RTC test mode    */
-#define RTC_RSTR_ED		0x00002000	/* RTC reverse mode    */
-#define RTC_RSTR_AC		0x00001000	/* RTC long mode	*/
-#define RTC_RSTR_SN		0x00000800	/* SOUTH/NORTH direction */
-#define RTC_RSTR_EW		0x00000400	/* EAST/WEST direction	 */
-#define RTC_RSTR_NC		0x00000200	/* get NORTH channel   */
-#define RTC_RSTR_SC		0x00000100	/* get SOUTH channel	*/
-#define RTC_RSTR_WC		0x00000080	/* get WEST channel	*/
-#define RTC_RSTR_EC		0x00000040	/* get EAST channel	*/
-#define RTC_RSTR_BM		0x00000020	/* broad also my cell	*/
-#define RTC_RSTR_RT		0x00000020	/* reset  		*/
-
-
-#define RTC_ITRR_PA		0x00040000	/* parity error for LBUS */
-#define RTC_ITRR_LR		0x00020000	/* MSC read but FIFO is empty*/
-#define RTC_ITRR_LW		0x00010000	/* MSC write but FIFO is full*/
-#define RTC_ITRR_AL		0x00008000	/* specify end data in data transfer */
-#define RTC_ITRR_DN		0x00002000	/* parity error in NORTH channel  */
-#define RTC_ITRR_DS		0x00001000	/* parity error in SOUTH channel		*/
-#define RTC_ITRR_DW		0x00000800	/* parity error in WEST channel			*/
-#define RTC_ITRR_DE		0x00000400	/* parity error in EAST channel			*/
-#define RTC_ITRR_BD		0x00000200	/* receive 2 kind of broad data			*/
-#define RTC_ITRR_EW		0x00000100	/* control to write error bits			*/
-#define RTC_ITRR_EM		0x00000080	/* mask error interrupt request			*/
-#define RTC_ITRR_ER		0x00000040	/* error interrput request				*/
-#define RTC_ITRR_SW		0x00000020	/* control to write SR, SM  */
-#define RTC_ITRR_SM		0x00000010	/* mask send interrupt					*/
-#define RTC_ITRR_SR		0x00000008	/* send interrupt request				*/
-#define RTC_ITRR_RW		0x00000004	/* icontrol to read RR, RM				*/
-#define RTC_ITRR_RM		0x00000002	/* mask read interrupt					*/
-#define RTC_ITRR_RR		0x00000001	/* receive interrupt request			*/
-
-#define RTC_ITRR_RWM (RTC_ITRR_RW|RTC_ITRR_RM)
-#define RTC_ITRR_SWM (RTC_ITRR_SW|RTC_ITRR_SM)
-#define RTC_ITRR_EWM (RTC_ITRR_EW|RTC_ITRR_EM)
-#define RTC_ITRR_RWR (RTC_ITRR_RW|RTC_ITRR_RR)
-#define RTC_ITRR_SWR (RTC_ITRR_SW|RTC_ITRR_SR)
-#define RTC_ITRR_EWR (RTC_ITRR_EW|RTC_ITRR_ER)
-#define RTC_ITRR_RRM (RTC_ITRR_RM|RTC_ITRR_RR)
-#define RTC_ITRR_SRM (RTC_ITRR_SM|RTC_ITRR_SR)
-#define RTC_ITRR_ERM (RTC_ITRR_EM|RTC_ITRR_ER)
-#define RTC_ITRR_RWMR   (RTC_ITRR_RW|RTC_ITRR_RM|RTC_ITRR_RR)
-#define RTC_ITRR_SWMR   (RTC_ITRR_SW|RTC_ITRR_SM|RTC_ITRR_SR)
-#define RTC_ITRR_EWMR   (RTC_ITRR_EW|RTC_ITRR_EM|RTC_ITRR_ER)
-
-#define RTC_ITRR_ALLMSK (RTC_ITRR_RWM|RTC_ITRR_SWM|RTC_ITRR_EWM)
-#define RTC_ITRR_ALLCLR (RTC_ITRR_RW|RTC_ITRR_SW|RTC_ITRR_EW)
-#define RTC_ITRR_ALLWR  (RTC_ITRR_RWMR|RTC_ITRR_SWMR|RTC_ITRR_EWMR)
-#define RTC_ITRR_ALLRD  (RTC_ITRR_RRM|RTC_ITRR_SRM|RTC_ITRR_ERM)
-
-
-/*
- * macros to manipulate context/task/pid numbers for parallel programs
- */
-#define MPP_CONTEXT_BASE (AP_NUM_CONTEXTS - (NR_TASKS - MPP_TASK_BASE))
-#define MPP_TASK_TO_CTX(taskid) (((taskid) - MPP_TASK_BASE)+MPP_CONTEXT_BASE)
-#define MPP_CTX_TO_TASK(ctx) (((ctx)-MPP_CONTEXT_BASE)+MPP_TASK_BASE)
-#define MPP_IS_PAR_TASK(taskid) ((taskid) >= MPP_TASK_BASE)
-#define MPP_IS_PAR_CTX(ctx) ((ctx) >= MPP_CONTEXT_BASE)
-
-
-/*
- * ioctls available on the ring buffer
- */
-#define CAP_GETINIT 1
-#define CAP_SYNC    2
-#define CAP_SETTASK 3
-#define CAP_SETGANG 4
-#define CAP_MAP     5
-
-/*
- * the structure shared by the kernel and the parallel tasks in the
- * front of the cap_shared area
- */
-#ifndef _ASM_
-#ifdef _APLIB_
-struct _kernel_cap_shared {
-	unsigned rbuf_read_ptr;
-	unsigned dummy[32]; /* for future expansion */
-};
-#endif
-#endif
-
-/*
- * the mmap'd ringbuffer region is layed out like this:
-
- shared page - one page
- queue pages - 11 pages
- ring buffer - xx pages
- mirror of ring buffer - xx pages
- */
-#define RBUF_VBASE 0xd0000000
-#define RBUF_SHARED_PAGE_OFF 0
-#define RBUF_PUT_QUEUE             PAGE_SIZE
-#define RBUF_GET_QUEUE           2*PAGE_SIZE
-#define RBUF_SEND_QUEUE          3*PAGE_SIZE
-#define RBUF_XY_QUEUE            4*PAGE_SIZE
-#define RBUF_X_QUEUE             5*PAGE_SIZE
-#define RBUF_Y_QUEUE             6*PAGE_SIZE
-#define RBUF_XYG_QUEUE           7*PAGE_SIZE
-#define RBUF_XG_QUEUE            8*PAGE_SIZE
-#define RBUF_YG_QUEUE            9*PAGE_SIZE
-#define RBUF_CSI_QUEUE          10*PAGE_SIZE
-#define RBUF_FOP_QUEUE          11*PAGE_SIZE
-#define RBUF_RING_BUFFER_OFFSET 15*PAGE_SIZE
-
-
-/*
- * number of MMU contexts to use
- */
-#define AP_NUM_CONTEXTS 1024
-#define SYSTEM_CONTEXT 1
-
-/*
- * the default gang scheduling factor
-*/
-#define DEF_GANG_FACTOR 15
-
-/*
- * useful for bypassing the cache
-*/
-#ifdef _APLIB_
-#ifndef _ASM_
-static inline unsigned long phys_8_in(unsigned long paddr)
-{
-	unsigned long word;
-	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
-			     "=r" (word) :
-			     "r" (paddr), "i" (0x28) :
-			     "memory");
-	return word;
-}
-
-/*
- * useful for bypassing the cache
-*/
-static inline unsigned long phys_9_in(unsigned long paddr)
-{
-	unsigned long word;
-	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
-			     "=r" (word) :
-			     "r" (paddr), "i" (0x29) :
-			     "memory");
-	return word;
-}
-#endif
-#endif
-
-/*
- * DDV definitions 
-*/
-#define OBASE        (0xfff40010)
-#define OPTION_BASE 0xfc000000
-#define _OPIBUS_BASE (OPTION_BASE + 0x800000)
-#ifdef CAP2_OPTION
-#define OPIBUS_BASE 0
-#else
-#define OPIBUS_BASE _OPIBUS_BASE
-#endif
-#define PBUF0        (OPIBUS_BASE+0x7e0080)
-#define PBUF1        (OPIBUS_BASE+0x7e0084)
-#define PBUF2        (OPIBUS_BASE+0x7e0088)
-#define PBUF3        (OPIBUS_BASE+0x7e008c)
-#define PIRQ         (OPIBUS_BASE+0x7e0090)
-#define PRST         (OPIBUS_BASE+0x7e0094)
-
-#define IRC0         (OPIBUS_BASE+0x7d00a0)
-#define IRC1         (OPIBUS_BASE+0x7d00a4)
-
-#define PRST_IRST    (0x00000001)
-
-#define OPIU_RESET			(0x00000000)
-#define OPIU_OP				(PBUF0)
-
-#define LSTR(s) (_OPIBUS_BASE + (s))
-
-#endif /* _AP1000_APREG_H */
-
diff --git a/include/asm-sparc/ap1000/apservice.h b/include/asm-sparc/ap1000/apservice.h
deleted file mode 100644
index 902e774d6..000000000
--- a/include/asm-sparc/ap1000/apservice.h
+++ /dev/null
@@ -1,111 +0,0 @@
-  /*
-   * Copyright 1996 The Australian National University.
-   * Copyright 1996 Fujitsu Laboratories Limited
-   * 
-   * This software may be distributed under the terms of the Gnu
-   * Public License version 2 or later
-  */
-/* this defines service requests that can be made by the cells of the 
-   front end "bootap" server 
-
-   tridge, March 1996
-   */
-#ifndef _APSERVICE_H
-#define _APSERVICE_H
-#ifdef __KERNEL__
-#include <linux/sched.h>
-#endif
-
-#ifndef _ASM_
-
-/* all requests start with this structure */
-struct cap_request {
-  unsigned header; /* for the hardware */
-  int size; /* the total request size in bytes, including this header */
-  int cid; /* the cell it came from */
-  int type; /* the type of request */
-  int data[4]; /* misc data */
-};
-
-/* Initialisation data to be sent to boot cell program */
-struct cap_init {
-  int bootcid;  /* base cid to boot */
-  int numcells; /* number of cells */
-  int physcells; /* physical number of cells */
-  unsigned long baseIP; /* IP address of cell 0 */
-  unsigned long netmask; /* netmask of cells net */
-  int gdbcell; /* what cell is the debugger running on */
-  unsigned init_time; /* time at startup */
-};
-#endif
-
-/* what fake host number to use for the aliased IP device */
-#define AP_ALIAS_IP 2
-
-/* request types */
-#define REQ_WRITE 0
-#define REQ_SHUTDOWN 1
-#define REQ_LOAD_AOUT 2
-#define REQ_PUTCHAR 3
-#define REQ_GETBOOTARGS 4       
-#define REQ_PUTDEBUGCHAR 5      
-#define REQ_GETDEBUGCHAR 6     
-#define REQ_OPENNET 7
-#define REQ_IP 8
-#define REQ_BREAK 9
-#define REQ_INIT 10
-#define REQ_PUTDEBUGSTRING 11
-#define REQ_BREAD 12
-#define REQ_BWRITE 13
-#define REQ_BOPEN 14
-#define REQ_BCLOSE 15
-#define REQ_DDVOPEN 16
-#define REQ_BIF_TOKEN 17
-#define REQ_KILL 18
-#define REQ_SCHEDULE 19
-
-/* the bit used to indicate that the host wants the BIF */
-#define HOST_STATUS_BIT 2
-
-#ifdef __KERNEL__
-/* some prototypes */
-extern int ap_dma_wait(int ch);
-extern int ap_dma_go(unsigned long ch,unsigned int p,int size,unsigned long cmd);
-extern int mpp_cid(void);
-extern void ap_start_debugger(void);
-extern int bif_queue(struct cap_request *req,char *buf,int bufsize);
-extern void write_bif_polled(char *buf1,int len1,char *buf2,int len2);
-extern void read_bif(char *buf,int size);
-extern void ap_wait_request(struct cap_request *req,int type);
-extern void bif_set_poll(int set);
-extern void ap_led(unsigned char d);
-extern void ap_xor_led(unsigned char d);
-extern void ap_set_led(unsigned char d);
-extern void ap_unset_led(unsigned char d);
-extern void bif_toss(int size);
-void ap_msc_init(void);
-void mac_dma_complete(void);
-void ap_dbg_flush(void);
-void bif_queue_flush(void);
-/* void ap_printk(char *msg,int a1,int a2,int a3,int a4,int a5); */
-void show_mapping_ctx(unsigned *ctp,int context,unsigned Vm);
-void async_fault(unsigned long address, int write, int taskid,
-		 void (*callback)(int,unsigned long,int,int));
-void ap_bif_init(void);
-void ap_tnet_init(void);
-int wait_on_int(volatile int *p,int x,int interval);
-void ap_put(int dest_cell,u_long local_addr,int size,
-	    u_long remote_addr,u_long dest_flag,u_long local_flag);
-void ap_bput(u_long local_addr,int size,
-	     u_long remote_addr,u_long dest_flag,u_long local_flag);
-void msc_switch_check(struct task_struct *tsk);
-int bif_queue_nocopy(struct cap_request *req,char *buf,int bufsize);
-void mpp_set_gang_factor(int factor);
-void bif_register_request(int type,void (*fn)(struct cap_request *));
-void bif_add_debug_key(char key,void (*fn)(void),char *description);
-void ap_complete(struct cap_request *creq);
-void ap_reboot(char *bootstr);
-#endif
-
-
-#endif /* _APSERVICE_H */
diff --git a/include/asm-sparc/ap1000/pgtapmmu.h b/include/asm-sparc/ap1000/pgtapmmu.h
deleted file mode 100644
index 9e238db45..000000000
--- a/include/asm-sparc/ap1000/pgtapmmu.h
+++ /dev/null
@@ -1,141 +0,0 @@
-  /*
-   * Copyright 1996 The Australian National University.
-   * Copyright 1996 Fujitsu Laboratories Limited
-   * 
-   * This software may be distributed under the terms of the Gnu
-   * Public License version 2 or later
-  */
-/* 
- * based on pgtsrmmu.h
- *
- */
-
-#ifndef _SPARC_PGTAPMMU_H
-#define _SPARC_PGTAPMMU_H
-
-#include <asm/page.h>
-#include <asm/ap1000/apreg.h>
-
-
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define APMMU_PMD_SHIFT         18
-#define APMMU_PMD_SIZE          (1UL << APMMU_PMD_SHIFT)
-#define APMMU_PMD_MASK          (~(APMMU_PMD_SIZE-1))
-#define APMMU_PMD_ALIGN(addr)   (((addr)+APMMU_PMD_SIZE-1)&APMMU_PMD_MASK)
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define APMMU_PGDIR_SHIFT       24
-#define APMMU_PGDIR_SIZE        (1UL << APMMU_PGDIR_SHIFT)
-#define APMMU_PGDIR_MASK        (~(APMMU_PGDIR_SIZE-1))
-#define APMMU_PGDIR_ALIGN(addr) (((addr)+APMMU_PGDIR_SIZE-1)&APMMU_PGDIR_MASK)
-
-#define APMMU_PTRS_PER_PTE      64
-#define APMMU_PTRS_PER_PMD      64
-#define APMMU_PTRS_PER_PGD      256
-
-#define APMMU_PTE_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
-#define APMMU_PMD_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
-#define APMMU_PGD_TABLE_SIZE    0x400 /* 256 entries, 4 bytes a piece */
-
-#define APMMU_VMALLOC_START   (0xfe300000)
-#define APMMU_VMALLOC_END     ~0x0UL
-
-/* Definition of the values in the ET field of PTD's and PTE's */
-#define APMMU_ET_MASK         0x3
-#define APMMU_ET_INVALID      0x0
-#define APMMU_ET_PTD          0x1
-#define APMMU_ET_PTE          0x2
-#define APMMU_ET_REPTE        0x3 /* AIEEE, SuperSparc II reverse endian page! */
-
-/* Physical page extraction from PTP's and PTE's. */
-#define APMMU_CTX_PMASK    0xfffffff0
-#define APMMU_PTD_PMASK    0xfffffff0
-#define APMMU_PTE_PMASK    0xffffff00
-
-/* The pte non-page bits.  Some notes:
- * 1) cache, dirty, valid, and ref are frobbable
- *    for both supervisor and user pages.
- * 2) exec and write will only give the desired effect
- *    on user pages
- * 3) use priv and priv_readonly for changing the
- *    characteristics of supervisor ptes
- */
-#define APMMU_CACHE        0x80
-#define APMMU_DIRTY        0x40
-#define APMMU_REF          0x20
-#define APMMU_EXEC         0x08
-#define APMMU_WRITE        0x04
-#define APMMU_VALID        0x02 /* APMMU_ET_PTE */
-#define APMMU_PRIV         0x1c
-#define APMMU_PRIV_RDONLY  0x18
-
-#define APMMU_CHG_MASK    (0xffffff00 | APMMU_REF | APMMU_DIRTY)
-
-/*
- * "normal" sun systems have their memory on bus 0. This means the top
- * 4 bits of 36 bit physical addresses are 0. We use this define to
- * determine if a piece of memory might be normal memory, or if its
- * definately some sort of device memory.  
- *
- * On the AP+ normal memory is on bus 8. Why? Ask Fujitsu :-)
-*/
-#define MEM_BUS_SPACE 8
-
-/* Some day I will implement true fine grained access bits for
- * user pages because the APMMU gives us the capabilities to
- * enforce all the protection levels that vma's can have.
- * XXX But for now...
- */
-#define APMMU_PAGE_NONE    __pgprot((MEM_BUS_SPACE<<28) | \
-				    APMMU_VALID | APMMU_CACHE | \
-				    APMMU_PRIV | APMMU_REF)
-#define APMMU_PAGE_SHARED  __pgprot((MEM_BUS_SPACE<<28) | \
-				    APMMU_VALID | APMMU_CACHE | \
-				    APMMU_EXEC | APMMU_WRITE | APMMU_REF)
-#define APMMU_PAGE_COPY    __pgprot((MEM_BUS_SPACE<<28) | \
-				    APMMU_VALID | APMMU_CACHE | \
-				    APMMU_EXEC | APMMU_REF)
-#define APMMU_PAGE_RDONLY  __pgprot((MEM_BUS_SPACE<<28) | \
-				    APMMU_VALID | APMMU_CACHE | \
-				    APMMU_EXEC | APMMU_REF)
-#define APMMU_PAGE_KERNEL  __pgprot((MEM_BUS_SPACE<<28) | \
-				    APMMU_VALID | APMMU_CACHE | APMMU_PRIV | \
-				    APMMU_DIRTY | APMMU_REF)
-
-#define APMMU_CTXTBL_PTR         0x00000100
-#define APMMU_CTX_REG            0x00000200
-
-extern __inline__ unsigned long apmmu_get_ctable_ptr(void)
-{
-	unsigned int retval;
-
-	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
-			     "=r" (retval) :
-			     "r" (APMMU_CTXTBL_PTR),
-			     "i" (ASI_M_MMUREGS));
-	return (retval & APMMU_CTX_PMASK) << 4;
-}
-
-extern __inline__ void apmmu_set_context(int context)
-{
-	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
-			     "r" (context), "r" (APMMU_CTX_REG),
-			     "i" (ASI_M_MMUREGS) : "memory");
-	/* The AP1000+ message controller also needs to know
-	   the current task's context. */
-	MSC_OUT(MSC_PID, context);
-}
-
-extern __inline__ int apmmu_get_context(void)
-{
-	register int retval;
-	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
-			     "=r" (retval) :
-			     "r" (APMMU_CTX_REG),
-			     "i" (ASI_M_MMUREGS));
-	return retval;
-}
-
-#endif /* !(_SPARC_PGTAPMMU_H) */
-
-
diff --git a/include/asm-sparc/checksum.h b/include/asm-sparc/checksum.h
index 625ff3bda..00324fc79 100644
--- a/include/asm-sparc/checksum.h
+++ b/include/asm-sparc/checksum.h
@@ -1,4 +1,4 @@
-/* $Id: checksum.h,v 1.30 2000/01/05 21:27:39 davem Exp $ */
+/* $Id: checksum.h,v 1.31 2000/01/31 01:26:52 davem Exp $ */
 #ifndef __SPARC_CHECKSUM_H
 #define __SPARC_CHECKSUM_H
 
@@ -210,7 +210,7 @@ static inline unsigned short int csum_tcpudp_magic(unsigned long saddr,
 
 static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
 						     struct in6_addr *daddr,
-						     __u16 len,
+						     __u32 len,
 						     unsigned short proto,
 						     unsigned int sum) 
 {
@@ -237,7 +237,7 @@ static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
 		"
 		: "=&r" (sum)
 		: "r" (saddr), "r" (daddr), 
-		  "r"(htonl((__u32) (len))), "r"(htonl(proto)), "r"(sum)
+		  "r"(htonl(len)), "r"(htonl(proto)), "r"(sum)
 		: "g2", "g3", "g4", "cc");
 
 	return csum_fold(sum);
diff --git a/include/asm-sparc/ethtool.h b/include/asm-sparc/ethtool.h
index bea36b6c6..572db24fb 100644
--- a/include/asm-sparc/ethtool.h
+++ b/include/asm-sparc/ethtool.h
@@ -1,7 +1,7 @@
-/* $Id: ethtool.h,v 1.1 1998/12/19 15:09:38 davem Exp $
+/* $Id: ethtool.h,v 1.2 2000/01/31 04:59:17 davem Exp $
  * ethtool.h: Defines for SparcLinux ethtool.
  *
- * Copyright (C) 1998 David S. Miller (davem@dm.cobaltmicro.com)
+ * Copyright (C) 1998 David S. Miller (davem@redhat.com)
  */
 
 #ifndef _SPARC_ETHTOOL_H
diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h
index 352590e2e..344640811 100644
--- a/include/asm-sparc/page.h
+++ b/include/asm-sparc/page.h
@@ -1,4 +1,4 @@
-/* $Id: page.h,v 1.46 2000/01/08 16:38:22 anton Exp $
+/* $Id: page.h,v 1.47 2000/01/29 00:41:49 anton Exp $
  * page.h:  Various defines and such for MMU operations on the Sparc for
  *          the Linux kernel.
  *
@@ -93,132 +93,6 @@ typedef struct { unsigned long iopgprot; } iopgprot_t;
 #define __pgprot(x)	((pgprot_t) { (x) } )
 #define __iopgprot(x)	((iopgprot_t) { (x) } )
 
-#elif CONFIG_AP1000_DEBUG
-
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long iopte; } iopte_t;
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long ctxd; } ctxd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct { unsigned long iopgprot; } iopgprot_t;
-
-static inline unsigned long __get_val(unsigned long x)
-{
-	if ((x & 0xF0000000) == (8<<28))
-		return x & 0x0FFFFFFF;
-	return x;
-}
-
-static inline unsigned long __set_val(unsigned long x)
-{
-	if ((x & 0xF0000000) == (0<<28))
-		return x | 0x80000000;
-	return x;
-}
-
-#define __pte_val(x)	((x).pte)
-#define __iopte_val(x)	((x).iopte)
-#define __pmd_val(x)      ((x).pmd)
-#define __pgd_val(x)	((x).pgd)
-#define __ctxd_val(x)	((x).ctxd)
-#define __pgprot_val(x)	((x).pgprot)
-#define __iopgprot_val(x)	((x).iopgprot)
-
-#define ___pte(x)	((pte_t) { (x) } )
-#define ___iopte(x)	((iopte_t) { (x) } )
-#define ___pmd(x)        ((pmd_t) { (x) } )
-#define ___pgd(x)	((pgd_t) { (x) } )
-#define ___ctxd(x)	((ctxd_t) { (x) } )
-#define ___pgprot(x)	((pgprot_t) { (x) } )
-#define ___iopgprot(x)	((iopgprot_t) { (x) } )
-
-
-#define pte_val(x) __get_val(__pte_val(x))
-#define iopte_val(x) __get_val(__iopte_val(x))
-#define pmd_val(x) __get_val(__pmd_val(x))
-#define pgd_val(x) __get_val(__pgd_val(x))
-#define ctxd_val(x) __get_val(__ctxd_val(x))
-#define pgprot_val(x) __get_val(__pgprot_val(x))
-#define iopgprot_val(x) __get_val(__iopgprot_val(x))
-
-#define __pte(x) ___pte(__set_val(x))
-#define __iopte(x) ___iopte(__set_val(x))
-#define __pmd(x) ___pmd(__set_val(x))
-#define __pgd(x) ___pgd(__set_val(x))
-#define __ctxd(x) ___ctxd(__set_val(x))
-#define __pgprot(x) ___pgprot(x)
-#define __iopgprot(x) ___iopgprot(__set_val(x))
-
-#elif CONFIG_AP1000
-
-typedef unsigned long pte_t;
-typedef unsigned long iopte_t;
-typedef unsigned long pmd_t;
-typedef unsigned long pgd_t;
-typedef unsigned long ctxd_t;
-typedef unsigned long pgprot_t;
-typedef unsigned long iopgprot_t;
-
-static inline unsigned long __get_val(unsigned long x)
-{
-#if 0
-	extern void ap_panic(char *fmt,...);
-	if (x && (x & 0xF0000000) == 0) {
-		ap_panic("get_val got 0x%x\n",x);
-	}
-#endif
-	if ((x & 0xF0000000) == (8<<28))
-		return x & 0x0FFFFFFF;
-	return x;
-}
-
-static inline unsigned long __set_val(unsigned long x)
-{
-#if 0
-	extern void ap_panic(char *fmt,...);
-	if ((x & 0xF0000000) == (8<<28)) {
-		ap_panic("set_val got 0x%x\n",x);
-	}
-#endif
-	if ((x & 0xF0000000) == (0<<28))
-		return x | 0x80000000;
-	return x;
-}
-
-#define __pte_val(x)	(x)
-#define __iopte_val(x)	(x)
-#define __pmd_val(x)      (x)
-#define __pgd_val(x)	(x)
-#define __ctxd_val(x)	(x)
-#define __pgprot_val(x)	(x)
-#define __iopgprot_val(x)	(x)
-
-#define ___pte(x)	((pte_t) { (x) } )
-#define ___iopte(x)	((iopte_t) { (x) } )
-#define ___pmd(x)        ((pmd_t) { (x) } )
-#define ___pgd(x)	((pgd_t) { (x) } )
-#define ___ctxd(x)	((ctxd_t) { (x) } )
-#define ___pgprot(x)	((pgprot_t) { (x) } )
-#define ___iopgprot(x)	((iopgprot_t) { (x) } )
-
-
-#define pte_val(x) __get_val(__pte_val(x))
-#define iopte_val(x) __get_val(__iopte_val(x))
-#define pmd_val(x) __get_val(__pmd_val(x))
-#define pgd_val(x) __get_val(__pgd_val(x))
-#define ctxd_val(x) __get_val(__ctxd_val(x))
-#define pgprot_val(x) __get_val(__pgprot_val(x))
-#define iopgprot_val(x) __get_val(__iopgprot_val(x))
-
-#define __pte(x) ___pte(__set_val(x))
-#define __iopte(x) ___iopte(__set_val(x))
-#define __pmd(x) ___pmd(__set_val(x))
-#define __pgd(x) ___pgd(__set_val(x))
-#define __ctxd(x) ___ctxd(__set_val(x))
-#define __pgprot(x) ___pgprot(x)
-#define __iopgprot(x) ___iopgprot(__set_val(x))
-
 #else
 /*
  * .. while these make it easier on the compiler
diff --git a/include/asm-sparc/sbus.h b/include/asm-sparc/sbus.h
index c96b5660e..b7f2b8f9e 100644
--- a/include/asm-sparc/sbus.h
+++ b/include/asm-sparc/sbus.h
@@ -1,4 +1,4 @@
-/* $Id: sbus.h,v 1.20 1999/12/27 06:37:17 anton Exp $
+/* $Id: sbus.h,v 1.21 2000/01/28 13:43:11 jj Exp $
  * sbus.h:  Defines for the Sun SBus.
  *
  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
diff --git a/include/asm-sparc/scatterlist.h b/include/asm-sparc/scatterlist.h
index e5776df9b..02e420275 100644
--- a/include/asm-sparc/scatterlist.h
+++ b/include/asm-sparc/scatterlist.h
@@ -1,4 +1,4 @@
-/* $Id: scatterlist.h,v 1.4 1999/12/27 06:37:20 anton Exp $ */
+/* $Id: scatterlist.h,v 1.5 2000/01/29 16:27:07 jj Exp $ */
 #ifndef _SPARC_SCATTERLIST_H
 #define _SPARC_SCATTERLIST_H
 
@@ -14,6 +14,9 @@ struct scatterlist {
     __u32 dvma_length;
 };
 
+#define sg_dma_address(sg) ((sg)->dvma_address)
+#define sg_dma_len(sg)     ((sg)->dvma_length)
+
 #define ISA_DMA_THRESHOLD (~0UL)
 
 #endif /* !(_SPARC_SCATTERLIST_H) */
diff --git a/include/asm-sparc/siginfo.h b/include/asm-sparc/siginfo.h
index 480126b38..9d82eee87 100644
--- a/include/asm-sparc/siginfo.h
+++ b/include/asm-sparc/siginfo.h
@@ -1,4 +1,4 @@
-/* $Id: siginfo.h,v 1.6 2000/01/21 11:39:17 jj Exp $
+/* $Id: siginfo.h,v 1.7 2000/01/29 07:41:51 davem Exp $
  * siginfo.c:
  */
 
diff --git a/include/asm-sparc/types.h b/include/asm-sparc/types.h
index b70210ba8..8a43339c1 100644
--- a/include/asm-sparc/types.h
+++ b/include/asm-sparc/types.h
@@ -1,4 +1,4 @@
-/* $Id: types.h,v 1.11 1997/12/22 13:28:22 mj Exp $ */
+/* $Id: types.h,v 1.12 2000/01/29 02:23:25 anton Exp $ */
 #ifndef _SPARC_TYPES_H
 #define _SPARC_TYPES_H
 
@@ -45,6 +45,8 @@ typedef unsigned long long u64;
 
 #define BITS_PER_LONG 32
 
+typedef u32 dma_addr_t;
+
 #endif /* __KERNEL__ */
 
 #endif /* defined(_SPARC_TYPES_H) */
diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h
index c25741549..989c6742c 100644
--- a/include/asm-sparc/unistd.h
+++ b/include/asm-sparc/unistd.h
@@ -1,4 +1,4 @@
-/* $Id: unistd.h,v 1.64 2000/01/16 06:20:32 davem Exp $ */
+/* $Id: unistd.h,v 1.66 2000/01/29 17:57:25 jj Exp $ */
 #ifndef _SPARC_UNISTD_H
 #define _SPARC_UNISTD_H
 
@@ -161,7 +161,7 @@
 /* #define __NR_ni_syscall      143    ENOSYS under SunOS                          */
 #define __NR_getrlimit          144 /* Common                                      */
 #define __NR_setrlimit          145 /* Common                                      */
-/* #define __NR_killpg          146    SunOS Specific                              */
+#define __NR_pivot_root		146 /* Linux Specific, killpg under SunOS          */
 #define __NR_prctl		147 /* ENOSYS under SunOS                          */
 #define __NR_pciconfig_read	148 /* ENOSYS under SunOS                          */
 #define __NR_pciconfig_write	149 /* ENOSYS under SunOS                          */