diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1998-03-17 22:05:47 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 1998-03-17 22:05:47 +0000 |
| commit | 27cfca1ec98e91261b1a5355d10a8996464b63af (patch) | |
| tree | 8e895a53e372fa682b4c0a585b9377d67ed70d0e /include/linux/sc26198.h | |
| parent | 6a76fb7214c477ccf6582bd79c5b4ccc4f9c41b1 (diff) | |
Look Ma' what I found on my harddisk ...
o New faster syscalls for 2.1.x, too
o Upgrade to 2.1.89.
Don't try to run this. It's flaky as hell. But feel free to debug ...
Diffstat (limited to 'include/linux/sc26198.h')
| -rw-r--r-- | include/linux/sc26198.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/linux/sc26198.h b/include/linux/sc26198.h index 255241c61..38685e077 100644 --- a/include/linux/sc26198.h +++ b/include/linux/sc26198.h @@ -3,7 +3,7 @@ /* * sc26198.h -- SC26198 UART hardware info. * - * Copyright (C) 1995-1997 Stallion Technologies (support@stallion.oz.au). + * Copyright (C) 1995-1998 Stallion Technologies (support@stallion.oz.au). * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,15 +28,15 @@ /* * Define the number of async ports per sc26198 uart device. */ -#define SC26198_PORTS 8 +#define SC26198_PORTS 8 /* * Baud rate timing clocks. All derived from a master 14.7456 MHz clock. */ -#define SC26198_MASTERCLOCK 14745600L -#define SC26198_DCLK (SC26198_MASTERCLOCK) -#define SC26198_CCLK (SC26198_MASTERCLOCK / 2) -#define SC26198_BCLK (SC26198_MASTERCLOCK / 4) +#define SC26198_MASTERCLOCK 14745600L +#define SC26198_DCLK (SC26198_MASTERCLOCK) +#define SC26198_CCLK (SC26198_MASTERCLOCK / 2) +#define SC26198_BCLK (SC26198_MASTERCLOCK / 4) /* * Define internal FIFO sizes for the 26198 ports. |