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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>1999-06-22 22:12:59 +0000
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>1999-06-22 22:12:59 +0000
commit52273a23c9a84336b93a35e4847fc88fac7eb0e4 (patch)
tree77ff0727779f408a0824168988235cf2b0f806fd /include
parent43ff5e29a8d29c9c8da2d67f83fe6441a390a1dd (diff)
added little endian version of new semaphore code. Probably still buggy:-(
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/semaphore-helper.h30
-rw-r--r--include/asm-mips/semaphore.h27
2 files changed, 54 insertions, 3 deletions
diff --git a/include/asm-mips/semaphore-helper.h b/include/asm-mips/semaphore-helper.h
index 59337b898..95210135f 100644
--- a/include/asm-mips/semaphore-helper.h
+++ b/include/asm-mips/semaphore-helper.h
@@ -92,7 +92,35 @@ waking_non_zero_interruptible(struct semaphore *sem, struct task_struct *tsk)
#endif
#ifdef __MIPSEL__
-#error "FIXME: waking_non_zero_interruptible doesn't support little endian machines yet."
+ __asm__ __volatile__("
+ .set mips3
+ .set push
+ .set noat
+0: lld %1,%2
+ li %0,0
+
+ bltz %1, 1f
+ dli $1, 0xffffffff00000000
+ daddu %1, $1
+ li %0, 1
+ b 2f
+1:
+
+ beqz %3, 1f
+ addiu $1, %1, 1
+ dsrl32 %1, %1, 0
+ dsll32 %1, %1, 0
+ or %1, $1
+ li %0, %4
+ b 2f
+1:
+ scd %1, %2
+2:
+ beqz %1,0b
+ .set pop
+ .set mips0"
+ : "=&r"(ret), "=&r"(tmp), "=m"(*sem)
+ : "r"(signal_pending(tsk)), "i"(-EINTR));
#endif
return ret;
diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h
index 302f4ff7d..1f713fe49 100644
--- a/include/asm-mips/semaphore.h
+++ b/include/asm-mips/semaphore.h
@@ -1,4 +1,4 @@
-/* $Id: semaphore.h,v 1.7 1999/06/11 14:30:15 ralf Exp $
+/* $Id: semaphore.h,v 1.6 1999/06/17 13:30:38 ralf Exp $
*
* SMP- and interrupt-safe semaphores..
*
@@ -133,7 +133,30 @@ extern inline int down_trylock(struct semaphore * sem)
#endif
#ifdef __MIPSEL__
-#error "FIXME: down_trylock doesn't support little endian machines yet."
+ __asm__ __volatile__("
+ .set mips3
+ 0: lld %1, %4
+ dli %3, 0x0000000100000000
+ sltu %0, %1, $0
+
+ bltz %1, 1f
+ move %3, $0
+ 1:
+
+ sltu %2, %1, $0
+ and %0, %0, %2
+ bnez %0, 2f
+
+ subu %0, %3
+ scd %1, %4
+
+ beqz %1, 0b
+ 2:
+
+ .set mips0"
+ : "=&r"(ret), "=&r"(tmp), "=&r"(tmp2), "=&r"(sub)
+ : "m"(*sem)
+ : "memory");
#endif
return ret;