Add code to support the SB1 core, including mmu routines, processor

detection.  This also tweaks cpu_probe() to use bits 15:8 of PRId as
a company ID, as per the mips32/mips64 specs, and use bits 7:0 as the
processor ID within the company.  Patch from Justin with mods and some
additional bits by me.

7 files changed, 91 insertions, 47 deletions

diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 45bd9ef3f..0d1bf3246 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -20,6 +20,8 @@
 #define KSEG2                   0xc0000000
 #define KSEG3                   0xe0000000
 
+#define K0BASE  KSEG0
+
 /*
  * Returns the kernel segment base of a given address
  */
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 6bb29f1b7..12760cc3c 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -92,10 +92,10 @@ extern __inline__ void atomic_add(int i, atomic_t * v)
 	unsigned long temp;
 
 	__asm__ __volatile__(
-		"1:\tll\t%0, %1\t\t\t# atomic_add\n\t"
-		"addu\t%0, %2\n\t"
-		"sc\t%0, %1\n\t"
-		"beqz\t%0, 1b"
+		"1:   ll      %0, %1      # atomic_add\n"
+		"     addu    %0, %2                  \n"
+		"     sc      %0, %1                  \n"
+		"     beqz    %0, 1b                  \n"
 		: "=&r" (temp), "=m" (v->counter)
 		: "Ir" (i), "m" (v->counter));
 }
@@ -105,10 +105,10 @@ extern __inline__ void atomic_sub(int i, atomic_t * v)
 	unsigned long temp;
 
 	__asm__ __volatile__(
-		"1:\tll\t%0, %1\t\t\t# atomic_sub\n\t"
-		"subu\t%0, %2\n\t"
-		"sc\t%0, %1\n\t"
-		"beqz\t%0, 1b"
+		"1:   ll      %0, %1      # atomic_sub\n"
+		"     subu    %0, %2                  \n"
+		"     sc      %0, %1                  \n"
+		"     beqz    %0, 1b                  \n"
 		: "=&r" (temp), "=m" (v->counter)
 		: "Ir" (i), "m" (v->counter));
 }
@@ -121,13 +121,14 @@ extern __inline__ int atomic_add_return(int i, atomic_t * v)
 	unsigned long temp, result;
 
 	__asm__ __volatile__(
-		".set\tnoreorder\t\t\t# atomic_add_return\n"
-		"1:\tll\t%1,%2\n\t"
-		"addu\t%0,%1,%3\n\t"
-		"sc\t%0,%2\n\t"
-		"beqz\t%0,1b\n\t"
-		"addu\t%0,%1,%3\n\t"
-		".set\treorder"
+		".set push               # atomic_add_return\n"
+		".set noreorder                             \n"
+		"1:   ll      %1, %2                        \n"
+		"     addu    %0, %1, %3                    \n"
+		"     sc      %0, %2                        \n"
+		"     beqz    %0, 1b                        \n"
+		"     addu    %0, %1, %3                    \n"
+		".set pop                                   \n"
 		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
 		: "Ir" (i), "m" (v->counter)
 		: "memory");
@@ -140,13 +141,14 @@ extern __inline__ int atomic_sub_return(int i, atomic_t * v)
 	unsigned long temp, result;
 
 	__asm__ __volatile__(
-		".set\tnoreorder\t\t\t# atomic_sub_return\n"
-		"1:\tll\t%1,%2\n\t"
-		"subu\t%0,%1,%3\n\t"
-		"sc\t%0,%2\n\t"
-		"beqz\t%0,1b\n\t"
-		"subu\t%0,%1,%3\n\t"
-		".set\treorder"
+		".set push                                   \n"
+		".set noreorder           # atomic_sub_return\n"
+		"1:   ll    %1, %2                           \n"
+		"     subu  %0, %1, %3                       \n"
+		"     sc    %0, %2                           \n"
+		"     beqz  %0, 1b                           \n"
+		"     subu  %0, %1, %3                       \n"
+		".set pop                                    \r"
 		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
 		: "Ir" (i), "m" (v->counter)
 		: "memory");
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 23710cbef..5d7b01020 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -28,10 +28,11 @@
 #define MACH_GROUP_ITE         13 /* ITE Semi Eval Boards                     */
 #define MACH_GROUP_PHILLIPS    14
 #define MACH_GROUP_GLOBESPAN   15 /* Globespan PVR Referrence Board           */
+#define MACH_GROUP_SIBYTE      16 /* Sibyte Eval Boards                       */
 
 #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", "SNI", "ACN",      \
 	"SGI", "Cobalt", "NEC DDB", "Baget", "Cosine", "Galileo", "Momentum", \
-	"ITE", "Phillips", "Globepspan" }
+	"ITE", "Phillips", "Globepspan", "SiByte" }
 
 /*
  * Valid machtype values for group unknown (low order halfword of mips_machtype)
@@ -168,6 +169,13 @@
 #define GROUP_PHILIPS_NAMES { "Nino" , "Velo" }
 
 /*
+ * Valid machtype for group SIBYTE
+ */
+#define MACH_SWARM              0
+
+#define GROUP_SIBYTE_NAMES {"SWARM" }
+
+/*
  * Valid cputype values
  */
 #define CPU_UNKNOWN		0
@@ -204,14 +212,15 @@
 #define CPU_5KC                 31
 #define CPU_R4310               32
 #define CPU_R3912               33
-#define CPU_LAST		33
+#define CPU_SB1                 34
+#define CPU_LAST		34
 
 #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \
         "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC",         \
         "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000",          \
         "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000",     \
         "R5000A", "R4640", "Nevada", "RM7000", "R5432", "MIPS 4Kc",          \
-        "MIPS 5Kc", "R4310", "R3912" }
+        "MIPS 5Kc", "R4310", "R3912", "SiByte SB1" }
 
 #define COMMAND_LINE_SIZE	256
 
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 0d6db87bc..e5031ee38 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -8,11 +8,32 @@
 #define _ASM_CPU_H
 
 #include <asm/cache.h>
+/* Assigned Company values for bits 23:16 of the PRId Register  
+   (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from 
+   MTI, the PRId register is defined in this (backwards compatible)
+   way:
+
+  +----------------+----------------+----------------+----------------+
+  | Company Options| Company ID     | Processor ID   | Revision       |
+  +----------------+----------------+----------------+----------------+
+   31            24 23            16 15             8 7
+
+   I don't have docs for all the previous processors, but my impression is
+   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
+   spec.  
+*/
+
+#define PRID_COMP_LEGACY       0x000000
+#define PRID_COMP_MIPS         0x010000
+/* 
+ * Don't know who should be here...QED and Sandcraft, maybe?
+ */
+#define PRID_COMP_SIBYTE       0x040000
 
 /*
  * Assigned values for the product ID register.  In order to detect a
  * certain CPU type exactly eventually additional registers may need to
- * be examined.
+ * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
  */
 #define PRID_IMP_R2000		0x0100
 #define PRID_IMP_R3000		0x0200		/* Same as R2000A  */
@@ -40,6 +61,17 @@
 
 #define PRID_IMP_UNKNOWN	0xff00
 
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
+ */
+
+#define PRID_IMP_SB1            0x0100
+
+/*
+ * Definitions for 7:0 on legacy processors
+ */
+
+
 #define PRID_REV_R4400		0x0040
 #define PRID_REV_R3000A		0x0030
 #define PRID_REV_R3000		0x0020
diff --git a/include/asm-mips/current.h b/include/asm-mips/current.h
index 3015ce4bd..2c776757e 100644
--- a/include/asm-mips/current.h
+++ b/include/asm-mips/current.h
@@ -1,5 +1,4 @@
-/* $Id: current.h,v 1.5 1999/07/26 19:42:43 harald Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -16,21 +15,5 @@
 register struct task_struct *current asm("$28");
 
 #endif /* _LANGUAGE_C */
-#ifdef _LANGUAGE_ASSEMBLY
-
-/*
- * Special variant for use by exception handlers when the stack pointer
- * is not loaded.
- */
-#define _GET_CURRENT(reg)			\
-	lui	reg, %hi(kernelsp);		\
-	.set	push;				\
-	.set	reorder;			\
-	lw	reg, %lo(kernelsp)(reg);	\
-	.set	pop;				\
-	ori	reg, 8191;			\
-	xori	reg, 8191
-
-#endif
 
 #endif /* _ASM_CURRENT_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 25666e99f..4018ba883 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -130,13 +130,25 @@ extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 #define _CACHE_CACHABLE_NONCOHERENT 0
 
 #else
- 
 #define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
 #define _PAGE_GLOBAL                (1<<6)
 #define _PAGE_VALID                 (1<<7)
 #define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
 #define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
 #define _PAGE_SILENT_WRITE          (1<<8)
+#define _CACHE_MASK                 (7<<9)
+
+#if defined(CONFIG_CPU_SB1)
+
+/* No penalty for being coherent on the SB1, so just
+   use it for "noncoherent" spaces, too.  Shouldn't hurt. */
+
+#define _CACHE_UNCACHED             (2<<9)  
+#define _CACHE_CACHABLE_COW         (5<<9)  
+#define _CACHE_CACHABLE_NONCOHERENT (5<<9)  
+
+#else
+
 #define _CACHE_CACHABLE_NO_WA       (0<<9)  /* R4600 only              */
 #define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
 #define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
@@ -145,9 +157,9 @@ extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 #define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00 only           */
 #define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00 only           */
 #define _CACHE_CACHABLE_ACCELERATED (7<<9)  /* R10000 only             */
-#define _CACHE_MASK                 (7<<9)
 
 #endif
+#endif
 
 #define __READABLE	(_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
 #define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -157,8 +169,12 @@ extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 #ifdef CONFIG_MIPS_UNCACHED
 #define PAGE_CACHABLE_DEFAULT	_CACHE_UNCACHED
 #else
+#ifdef CONFIG_CPU_SB1
+#define PAGE_CACHABLE_DEFAULT	_CACHE_CACHABLE_COW
+#else
 #define PAGE_CACHABLE_DEFAULT	_CACHE_CACHABLE_NONCOHERENT
 #endif
+#endif
 
 #define PAGE_NONE	__pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
diff --git a/include/linux/tty_ldisc.h b/include/linux/tty_ldisc.h
index 501ea0765..028ce04a2 100644
--- a/include/linux/tty_ldisc.h
+++ b/include/linux/tty_ldisc.h
@@ -35,7 +35,7 @@
  *		   unsigned char * buf, size_t nr);
  *
  * 	This function is called when the user requests to read from
- * 	the tty.  The line discpline will return whatever characters
+ * 	the tty.  The line discipline will return whatever characters
  * 	it has buffered up for the user.  If this function is not
  * 	defined, the user will receive an EIO error.
  *