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authorKanoj Sarcar <kanoj@engr.sgi.com>2000-04-12 21:19:50 +0000
committerKanoj Sarcar <kanoj@engr.sgi.com>2000-04-12 21:19:50 +0000
commitacc376bc74201609a348fe00534d06e6780b4a91 (patch)
tree697cc5c1a895348fef513b5705b05e344b3f2c17 /include
parenta0a1b243d81d50fe7811b745803584908fd15785 (diff)
The state of the two interrupt mask registers for the 128 intr levels
for each cpu in the hub is now stored in the per processor data area.
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips64/processor.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-mips64/processor.h b/include/asm-mips64/processor.h
index 2f987555a..1148a35ab 100644
--- a/include/asm-mips64/processor.h
+++ b/include/asm-mips64/processor.h
@@ -27,6 +27,7 @@
#if (defined(CONFIG_SGI_IP27))
#include <asm/sn/types.h>
+#include <asm/sn/intr_public.h>
#endif
struct cpuinfo_mips {
@@ -41,6 +42,7 @@ struct cpuinfo_mips {
cnodeid_t p_nodeid; /* my node ID in compact-id-space */
nasid_t p_nasid; /* my node ID in numa-as-id-space */
unsigned char p_slice; /* Physical position on node board */
+ hub_intmasks_t p_intmasks; /* SN0 per-CPU interrupt masks */
#endif
} __attribute__((aligned(128)));