- IOC3 driver now will panic when encountering a RX/TX PCI DMA error.

 - IOC3 driver does no longer use GFP_DMA which given the _very_ small
   number of available GFP_DMA pages might have deadlocked the system.
 - First cut of Origin support.  Last minute change:  Do no longer use
   ARC memory / MD hub memory configuration information but klconfig.h
   stuff.  Simpler, faster, shorter.
 - Zillions of MIPS64 fixes.

22 files changed, 589 insertions, 135 deletions

diff --git a/include/asm-mips64/addrspace.h b/include/asm-mips64/addrspace.h
index d8d5a90a5..fee19b6d3 100644
--- a/include/asm-mips64/addrspace.h
+++ b/include/asm-mips64/addrspace.h
@@ -1,15 +1,17 @@
-/* $Id: addrspace.h,v 1.2 1999/10/19 20:51:53 ralf Exp $
+/* $Id: addrspace.h,v 1.2 1999/12/04 03:59:12 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 1996, 1999 by Ralf Baechle
- * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
  */
 #ifndef _ASM_ADDRSPACE_H
 #define _ASM_ADDRSPACE_H
 
+#include <linux/config.h>
+
 /*
  * Memory segments (32bit kernel mode addresses)
  */
@@ -27,7 +29,8 @@
 /*
  * Returns the physical address of a KSEG0/KSEG1 address
  */
-#define PHYSADDR(a)		(((unsigned long)(a)) & 0x1fffffff)
+#define CPHYSADDR(a)		(((unsigned long)(a)) & 0x1fffffffUL)
+#define PHYSADDR(a)		(((unsigned long)(a)) & 0x1fffffffUL)
 
 /*
  * Map an address to a certain kernel segment
@@ -49,4 +52,56 @@
 #define CKSSEG                  0xffffffffc0000000
 #define CKSEG3                  0xffffffffe0000000
 
+#if defined (CONFIG_CPU_R4300)						\
+    || defined (CONFIG_CPU_R4X00)					\
+    || defined (CONFIG_CPU_R5000)					\
+    || defined (CONFIG_CPU_NEVADA)
+#define	KUSIZE		0x0000010000000000		/* 2^^40 */
+#define	KUSIZE_64	0x0000010000000000		/* 2^^40 */
+#define	K0SIZE		0x0000001000000000		/* 2^^36 */
+#define	K1SIZE		0x0000001000000000		/* 2^^36 */
+#define	K2SIZE		0x000000ff80000000
+#define	KSEGSIZE	0x000000ff80000000		/* max syssegsz */
+#define TO_PHYS_MASK	0x0000000fffffffff		/* 2^^36 - 1 */
+#endif
+
+#if defined (CONFIG_CPU_R8000)
+/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
+#define	KUSIZE		0x0000010000000000		/* 2^^40 */
+#define	KUSIZE_64	0x0000010000000000		/* 2^^40 */
+#define	K0SIZE		0x0000010000000000		/* 2^^40 */
+#define	K1SIZE		0x0000010000000000		/* 2^^40 */
+#define	K2SIZE		0x0001000000000000
+#define	KSEGSIZE	0x0000010000000000		/* max syssegsz */
+#define TO_PHYS_MASK	0x000000ffffffffff		/* 2^^40 - 1 */
+#endif
+
+#if defined (CONFIG_CPU_R10000)
+#define	KUSIZE		0x0000010000000000		/* 2^^40 */
+#define	KUSIZE_64	0x0000010000000000		/* 2^^40 */
+#define	K0SIZE		0x0000010000000000		/* 2^^40 */
+#define	K1SIZE		0x0000010000000000		/* 2^^40 */
+#define	K2SIZE		0x00000fff80000000
+#define	KSEGSIZE	0x00000fff80000000		/* max syssegsz */
+#define TO_PHYS_MASK	0x000000ffffffffff		/* 2^^40 - 1 */
+#endif
+
+/*
+ * Further names for SGI source compatibility.  These are stolen from
+ * IRIX's <sys/mips_addrspace.h>.
+ */
+#define KUBASE		0
+#define KUSIZE_32	0x0000000080000000	/* KUSIZE for a 32 bit proc */
+#define K0BASE		0xa800000000000000
+#define K0BASE_EXL_WR	K0BASE			/* exclusive on write */
+#define K0BASE_NONCOH	0x9800000000000000	/* noncoherent */
+#define K0BASE_EXL	0xa000000000000000	/* exclusive */
+
+#ifdef CONFIG_SGI_IP27
+#define K1BASE		0x9600000000000000	/* Uncached attr 3, uncac */
+#else
+#define K1BASE		0x9000000000000000
+#endif
+#define K2BASE		0xc000000000000000
+
 #endif /* _ASM_ADDRSPACE_H */
diff --git a/include/asm-mips64/arc/hinv.h b/include/asm-mips64/arc/hinv.h
new file mode 100644
index 000000000..698891f87
--- /dev/null
+++ b/include/asm-mips64/arc/hinv.h
@@ -0,0 +1,175 @@
+/* $Id$
+ *
+ * ARCS hardware/memory inventory/configuration and system ID definitions.
+ */
+#ifndef _ASM_ARC_HINV_H
+#define _ASM_ARC_HINV_H
+
+#include <asm/arc/types.h>
+
+/* configuration query defines */
+typedef enum configclass {
+	SystemClass,
+	ProcessorClass,
+	CacheClass,
+#ifndef	_NT_PROM
+	MemoryClass,
+	AdapterClass,
+	ControllerClass,
+	PeripheralClass
+#else	/* _NT_PROM */
+	AdapterClass,
+	ControllerClass,
+	PeripheralClass,
+	MemoryClass
+#endif	/* _NT_PROM */
+} CONFIGCLASS;
+
+typedef enum configtype {
+	ARC,
+	CPU,
+	FPU,
+	PrimaryICache,
+	PrimaryDCache,
+	SecondaryICache,
+	SecondaryDCache,
+	SecondaryCache,
+#ifndef	_NT_PROM
+	Memory,
+#endif
+	EISAAdapter,
+	TCAdapter,
+	SCSIAdapter,
+	DTIAdapter,
+	MultiFunctionAdapter,
+	DiskController,
+	TapeController,
+	CDROMController,
+	WORMController,
+	SerialController,
+	NetworkController,
+	DisplayController,
+	ParallelController,
+	PointerController,
+	KeyboardController,
+	AudioController,
+	OtherController,
+	DiskPeripheral,
+	FloppyDiskPeripheral,
+	TapePeripheral,
+	ModemPeripheral,
+	MonitorPeripheral,
+	PrinterPeripheral,
+	PointerPeripheral,
+	KeyboardPeripheral,
+	TerminalPeripheral,
+	LinePeripheral,
+	NetworkPeripheral,
+#ifdef	_NT_PROM
+	Memory,
+#endif
+	OtherPeripheral,
+
+	/* new stuff for IP30 */
+	/* added without moving anything */
+	/* except ANONYMOUS. */
+
+	XTalkAdapter,
+	PCIAdapter,
+	GIOAdapter,
+	TPUAdapter,
+
+	Anonymous
+} CONFIGTYPE;
+
+typedef enum {
+	Failed = 1,
+	ReadOnly = 2,
+	Removable = 4,
+	ConsoleIn = 8,
+	ConsoleOut = 16,
+	Input = 32,
+	Output = 64
+} IDENTIFIERFLAG;
+
+#ifndef NULL			/* for GetChild(NULL); */
+#define	NULL	0
+#endif
+
+union key_u {
+	struct {
+#ifdef	_MIPSEB
+		unsigned char  c_bsize;		/* block size in lines */
+		unsigned char  c_lsize;		/* line size in bytes/tag */
+		unsigned short c_size;		/* cache size in 4K pages */
+#else	/* _MIPSEL */
+		unsigned short c_size;		/* cache size in 4K pages */
+		unsigned char  c_lsize;		/* line size in bytes/tag */
+		unsigned char  c_bsize;		/* block size in lines */
+#endif	/* _MIPSEL */
+	} cache;
+	ULONG FullKey;
+};
+
+#if _MIPS_SIM == _ABI64
+#define SGI_ARCS_VERS	64			/* sgi 64-bit version */
+#define SGI_ARCS_REV	0			/* rev .00 */
+#else
+#define SGI_ARCS_VERS	1			/* first version */
+#define SGI_ARCS_REV	10			/* rev .10, 3/04/92 */
+#endif
+
+typedef struct component {
+	CONFIGCLASS	Class;
+	CONFIGTYPE	Type;
+	IDENTIFIERFLAG	Flags;
+	USHORT		Version;
+	USHORT		Revision;
+	ULONG 		Key;
+	ULONG		AffinityMask;
+	ULONG		ConfigurationDataSize;
+	ULONG		IdentifierLength;
+	char		*Identifier;
+} COMPONENT;
+
+/* internal structure that holds pathname parsing data */
+struct cfgdata {
+	char *name;			/* full name */
+	int minlen;			/* minimum length to match */
+	CONFIGTYPE type;		/* type of token */
+};
+
+/* System ID */
+typedef struct systemid {
+	CHAR VendorId[8];
+	CHAR ProductId[8];
+} SYSTEMID;
+
+/* memory query functions */
+typedef enum memorytype {
+	ExceptionBlock,
+	SPBPage,			/* ARCS == SystemParameterBlock */
+#ifndef	_NT_PROM
+	FreeContiguous,
+	FreeMemory,
+	BadMemory,
+	LoadedProgram,
+	FirmwareTemporary,
+	FirmwarePermanent
+#else	/* _NT_PROM */
+	FreeMemory,
+	BadMemory,
+	LoadedProgram,
+	FirmwareTemporary,
+	FirmwarePermanent,
+	FreeContiguous
+#endif	/* _NT_PROM */
+} MEMORYTYPE;
+
+typedef struct memorydescriptor {
+	MEMORYTYPE	Type;
+	LONG		BasePage;
+	LONG		PageCount;
+} MEMORYDESCRIPTOR;
+
+#endif /* _ASM_ARC_HINV_H */
diff --git a/include/asm-mips64/arc/types.h b/include/asm-mips64/arc/types.h
index 685580411..79ca5d9da 100644
--- a/include/asm-mips64/arc/types.h
+++ b/include/asm-mips64/arc/types.h
@@ -40,11 +40,11 @@ typedef LONG		_PVOID;
 
 typedef char		CHAR;
 typedef short		SHORT;
-typedef long		LARGE_INTEGER __attribute__ (__mode__ (__DI__));
-typedef	long		LONG __attribute__ (__mode__ (__DI__));
+typedef long		LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef	long		LONG __attribute__ ((__mode__ (__DI__)));
 typedef unsigned char	UCHAR;
 typedef unsigned short	USHORT;
-typedef unsigned long	ULONG __attribute__ (__mode__ (__DI__));
+typedef unsigned long	ULONG __attribute__ ((__mode__ (__DI__)));
 typedef void		VOID;
 
 /* The pointer types.  We're 64-bit and the firmware is also 64-bit, so
diff --git a/include/asm-mips64/asm.h b/include/asm-mips64/asm.h
index fe616eb08..48f6bfbec 100644
--- a/include/asm-mips64/asm.h
+++ b/include/asm-mips64/asm.h
@@ -1,4 +1,4 @@
-/* $Id: asm.h,v 1.1 1999/08/18 23:37:50 ralf Exp $
+/* $Id: asm.h,v 1.2 1999/12/04 03:59:12 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -65,11 +65,19 @@ symbol:		.frame	sp, framesize, rpc
 /*
  * EXPORT - export definition of symbol
  */
-#define	EXPORT(symbol)                                  \
+#define	EXPORT(symbol)					\
 		.globl	symbol;                         \
 symbol:
 
 /*
+ * FEXPORT - export definition of a function symbol
+ */
+#define	FEXPORT(symbol)					\
+		.globl	symbol;                         \
+		.type	symbol,@function;		\
+symbol:
+
+/*
  * ABS - export absolute symbol
  */
 #define	ABS(symbol,value)                               \
diff --git a/include/asm-mips64/bcache.h b/include/asm-mips64/bcache.h
index e3507bb04..0df4edb7d 100644
--- a/include/asm-mips64/bcache.h
+++ b/include/asm-mips64/bcache.h
@@ -5,10 +5,17 @@
  * for more details.
  *
  * Copyright (c) 1997, 1999 by Ralf Baechle
+ * Copyright (c) 1999 Silicon Graphics, Inc.
  */
 #ifndef _ASM_BCACHE_H
 #define _ASM_BCACHE_H
 
+#include <linux/config.h>
+
+#ifdef CONFIG_BOARD_SCACHE
+
+/* Some R4000 / R4400 / R4600 / R5000 machines may have chipset implemented
+   caches.  On machines with other CPUs the CPU does the cache thing itself. */
 struct bcache_ops {
 	void (*bc_enable)(void);
 	void (*bc_disable)(void);
@@ -21,4 +28,35 @@ extern void sni_pcimt_sc_init(void);
 
 extern struct bcache_ops *bcops;
 
+void inline bc_enable(void)
+{
+	bcops->bc_enable();
+}
+
+void inline bc_disable(void)
+{
+	bcops->bc_disble();
+}
+
+void bc_wback_inv(unsigned long page, unsigned long size)
+{
+	bcops->bc_wback_inv(page, size);
+}
+
+void bc_inv(unsigned long page, unsigned long size)
+{
+	bcops->bc_inv(page, size);
+}
+
+#else /* !defined(CONFIG_BOARD_SCACHE) */
+
+/* Not R4000 / R4400 / R4600 / R5000.  */
+
+#define bc_enable() do { } while (0)
+#define bc_disable() do { } while (0)
+#define bc_wback_inv(page, size) do { } while (0)
+#define bc_inv(page, size) do { } while (0)
+
+#endif /* !defined(CONFIG_BOARD_SCACHE) */
+
 #endif /* _ASM_BCACHE_H */
diff --git a/include/asm-mips64/bootinfo.h b/include/asm-mips64/bootinfo.h
index 10c209c51..f62ec0e2f 100644
--- a/include/asm-mips64/bootinfo.h
+++ b/include/asm-mips64/bootinfo.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: bootinfo.h,v 1.1 1999/08/18 23:37:50 ralf Exp $
  *
  * bootinfo.h -- Definition of the Linux/MIPS boot information structure
  *
@@ -89,8 +89,9 @@
  * Valid machtype for group SGI
  */
 #define MACH_SGI_INDY		0	/* R4?K and R5K Indy workstaions */
+#define MACH_SGI_IP27		1	/* Origin 200, Origin 2000, Onyx 2 */
 
-#define GROUP_SGI_NAMES { "Indy" }
+#define GROUP_SGI_NAMES { "Indy", "IP27" }
 
 /*
  * Valid machtype for group COBALT
diff --git a/include/asm-mips64/cacheops.h b/include/asm-mips64/cacheops.h
index 438aa1b94..e69de29bb 100644
--- a/include/asm-mips64/cacheops.h
+++ b/include/asm-mips64/cacheops.h
@@ -1,48 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Cache operations for the cache instruction.
- *
- * (C) Copyright 1996, 1997, 1999 by Ralf Baechle
- */
-#ifndef	_ASM_CACHEOPS_H
-#define	_ASM_CACHEOPS_H
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I	0x04
-#define Index_Load_Tag_D	0x05
-#define Index_Load_Tag_SI	0x06
-#define Index_Load_Tag_SD	0x07
-#define Index_Store_Tag_I	0x08
-#define Index_Store_Tag_D	0x09
-#define Index_Store_Tag_SI	0x0A
-#define Index_Store_Tag_SD	0x0B
-#define Create_Dirty_Excl_D	0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I	0x10
-#define Hit_Invalidate_D	0x11
-#define Hit_Invalidate_SI	0x12
-#define Hit_Invalidate_SD	0x13
-#define Fill			0x14
-#define Hit_Writeback_Inv_D	0x15
-					/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I		0x18
-#define Hit_Writeback_D		0x19
-					/* 0x1a is unused */
-#define Hit_Writeback_SD	0x1b
-					/* 0x1c is unused */
-					/* 0x1e is unused */
-#define Hit_Set_Virtual_SI	0x1e
-#define Hit_Set_Virtual_SD	0x1f
-
-#endif	/* _ASM_CACHEOPS_H */
diff --git a/include/asm-mips64/current.h b/include/asm-mips64/current.h
index 0afc8cad4..abaab72af 100644
--- a/include/asm-mips64/current.h
+++ b/include/asm-mips64/current.h
@@ -1,4 +1,4 @@
-/* $Id: current.h,v 1.2 1999/09/28 22:27:19 ralf Exp $
+/* $Id: current.h,v 1.3 1999/12/04 03:59:12 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -25,7 +25,7 @@ register struct task_struct *current asm("$28");
 	lui	reg, %hi(kernelsp);		\
 	.set	push;				\
 	.set	noreorder;			\
-	lw	reg, %lo(kernelsp)(reg);	\
+	ld	reg, %lo(kernelsp)(reg);	\
 	.set	pop;				\
 	ori	reg, 0x3fff;			\
 	xori	reg, 0x3fff
diff --git a/include/asm-mips64/elf.h b/include/asm-mips64/elf.h
index f6f8785d4..f7724d9c8 100644
--- a/include/asm-mips64/elf.h
+++ b/include/asm-mips64/elf.h
@@ -82,8 +82,16 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #endif
 
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex,ibcs2) \
-	current->personality = (ibcs2 ? PER_SVR4 : PER_LINUX)
+#define SET_PERSONALITY(ex, ibcs2)			\
+do {	if ((ex).e_ident[EI_CLASS] == ELFCLASS32)	\
+		current->thread.mflags |= MF_32BIT;	\
+	else						\
+		current->thread.mflags &= ~MF_32BIT;	\
+	if (ibcs2)					\
+		current->personality = PER_SVR4;	\
+	else if (current->personality != PER_LINUX32)	\
+		current->personality = PER_LINUX;	\
+} while (0)
 #endif
 
 #endif /* _ASM_ELF_H */
diff --git a/include/asm-mips64/io.h b/include/asm-mips64/io.h
index edcd71b0e..e9df13a60 100644
--- a/include/asm-mips64/io.h
+++ b/include/asm-mips64/io.h
@@ -1,4 +1,4 @@
-/* $Id: io.h,v 1.1 1999/08/18 23:37:51 ralf Exp $
+/* $Id: io.h,v 1.2 1999/10/09 00:01:43 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -11,13 +11,13 @@
 #ifndef _ASM_IO_H
 #define _ASM_IO_H
 
+#include <linux/config.h>
+
 /*
  * Slowdown I/O port space accesses for antique hardware.
  */
 #undef CONF_SLOWDOWN_IO
 
-#include <linux/config.h>
-
 #include <asm/addrspace.h>
 
 /*
@@ -394,8 +394,27 @@ __OUTS(w,l,4)
  *    be discarded.  This operation is necessary before dma operations
  *    to the memory.
  */
+#ifdef CONFIG_COHERENT_IO
+
+/* This is for example for IP27.  */
+extern inline void dma_cache_wback_inv(unsigned long start, unsigned long size)
+{
+}
+
+extern inline void dma_cache_wback(unsigned long start, unsigned long size)
+{
+}
+
+extern inline void dma_cache_inv(unsigned long start, unsigned long size)
+{
+}
+
+#else
+
 extern void (*dma_cache_wback_inv)(unsigned long start, unsigned long size);
 extern void (*dma_cache_wback)(unsigned long start, unsigned long size);
 extern void (*dma_cache_inv)(unsigned long start, unsigned long size);
 
+#endif
+
 #endif /* _ASM_IO_H */
diff --git a/include/asm-mips64/mipsregs.h b/include/asm-mips64/mipsregs.h
index 2a4063ec9..3dba0bba0 100644
--- a/include/asm-mips64/mipsregs.h
+++ b/include/asm-mips64/mipsregs.h
@@ -1,4 +1,4 @@
-/* $Id$
+/* $Id: mipsregs.h,v 1.1 1999/08/18 23:37:51 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -153,8 +153,7 @@ set_cp0_##name(unsigned int change, unsigned int new)           \
 	res = read_32bit_cp0_register(register);                \
 	res &= ~change;                                         \
 	res |= (new & change);                                  \
-	if(change)                                              \
-		write_32bit_cp0_register(register, res);        \
+	write_32bit_cp0_register(register, res);                \
                                                                 \
 	return res;                                             \
 }
diff --git a/include/asm-mips64/page.h b/include/asm-mips64/page.h
index 4471bb273..607da8bb4 100644
--- a/include/asm-mips64/page.h
+++ b/include/asm-mips64/page.h
@@ -1,4 +1,4 @@
-/* $Id: page.h,v 1.1 1999/08/18 23:37:51 ralf Exp $
+/* $Id: page.h,v 1.2 1999/12/04 03:59:12 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -10,6 +10,8 @@
 #ifndef _ASM_PAGE_H
 #define _ASM_PAGE_H
 
+#include <linux/config.h>
+
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT	12
 #define PAGE_SIZE	(1UL << PAGE_SHIFT)
@@ -74,9 +76,16 @@ typedef unsigned long pgprot_t;
 
 /*
  * This handles the memory map.
- * We handle pages at KSEG0 for kernels with 32 bit address space.
+ * We handle pages at KSEG0 for kernels with upto 512mb of memory,
+ * at XKPHYS for kernels with more than that.
  */
+#ifdef CONFIG_SGI_IP22
 #define PAGE_OFFSET	0xffffffff80000000UL
+#endif
+#ifdef CONFIG_SGI_IP27
+#define PAGE_OFFSET	0xa800000000000000UL
+#endif
+
 #define __pa(x)		((unsigned long) (x) - PAGE_OFFSET)
 #define __va(x)		((void *)((unsigned long) (x) + PAGE_OFFSET))
 #define MAP_NR(addr)	(__pa(addr) >> PAGE_SHIFT)
diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h
index 02ca0e208..0f1fe41b3 100644
--- a/include/asm-mips64/pgtable.h
+++ b/include/asm-mips64/pgtable.h
@@ -198,8 +198,6 @@ extern unsigned long zero_page_mask;
 #define PAGE_PTR(address) \
 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
 
-extern void (*load_pgd)(unsigned long pg_dir);
-
 extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
 extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
 
@@ -777,7 +775,7 @@ extern inline void set_entryhi(unsigned long val)
 }
 
 /* CP0_INDEX register */
-extern inline unsigned long get_index(void)
+extern inline unsigned int get_index(void)
 {
 	unsigned long val;
 
@@ -789,7 +787,7 @@ extern inline unsigned long get_index(void)
 	return val;
 }
 
-extern inline void set_index(unsigned long val)
+extern inline void set_index(unsigned int val)
 {
 	__asm__ __volatile__(
 		".set noreorder\n\t"
diff --git a/include/asm-mips64/processor.h b/include/asm-mips64/processor.h
index e17b9b2c3..1bb9240e8 100644
--- a/include/asm-mips64/processor.h
+++ b/include/asm-mips64/processor.h
@@ -1,4 +1,4 @@
-/* $Id: processor.h,v 1.4 1999/12/04 03:59:12 ralf Exp $
+/* $Id: processor.h,v 1.5 2000/01/16 01:40:43 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -76,16 +76,17 @@ extern struct task_struct *last_task_used_math;
 /*
  * User space process size: 1TB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.  TASK_SIZE
- * is limited to 1TB by the R4000 architecture; R10000 and better do
+ * is limited to 1TB by the R4000 architecture; R10000 and better can
  * support 16TB.
-#define TASK_SIZE	   0x80000000UL
  */
+#define TASK_SIZE32	   0x80000000UL
 #define TASK_SIZE	0x10000000000UL
 
 /* This decides where the kernel will search for a free chunk of vm
  * space during mmap's.
  */
-#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)
+#define TASK_UNMAPPED_BASE	((current->thread.mflags & MF_32BIT) ? \
+	(TASK_SIZE32 / 3) : (TASK_SIZE / 3))
 
 /*
  * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
diff --git a/include/asm-mips64/r10kcache.h b/include/asm-mips64/r10kcache.h
index cd6ec974d..77d14e9a7 100644
--- a/include/asm-mips64/r10kcache.h
+++ b/include/asm-mips64/r10kcache.h
@@ -1,4 +1,4 @@
-/* $Id: r10kcache.h,v 1.1 2000/01/12 23:18:32 ralf Exp $
+/* $Id: r10kcache.h,v 1.1 2000/01/16 01:27:14 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -21,6 +21,8 @@
 /* These are fixed for the current R10000.  */
 #define icache_size	0x8000
 #define dcache_size	0x8000
+#define icache_way_size	0x4000
+#define dcache_way_size	0x4000
 #define ic_lsize	64
 #define dc_lsize	32
 
@@ -148,6 +150,22 @@ extern inline void protected_writeback_dcache_line(unsigned long addr)
 		: "r" (addr), "i" (Hit_Writeback_Inv_D));
 }
 
+#define cache32_unroll16(base,op)				\
+	__asm__ __volatile__("					\
+		.set noreorder;					\
+		cache %1, 0x000(%0); cache %1, 0x020(%0);	\
+		cache %1, 0x040(%0); cache %1, 0x060(%0);	\
+		cache %1, 0x080(%0); cache %1, 0x0a0(%0);	\
+		cache %1, 0x0c0(%0); cache %1, 0x0e0(%0);	\
+		cache %1, 0x100(%0); cache %1, 0x120(%0);	\
+		cache %1, 0x140(%0); cache %1, 0x160(%0);	\
+		cache %1, 0x180(%0); cache %1, 0x1a0(%0);	\
+		cache %1, 0x1c0(%0); cache %1, 0x1e0(%0);	\
+		.set reorder"					\
+		:						\
+		: "r" (base),					\
+		  "i" (op));
+
 #define cache32_unroll32(base,op)				\
 	__asm__ __volatile__("					\
 		.set noreorder;					\
@@ -174,12 +192,15 @@ extern inline void protected_writeback_dcache_line(unsigned long addr)
 
 extern inline void blast_dcache32(void)
 {
-	unsigned long start = KSEG0;
-	unsigned long end = (start + dcache_size);
-
-	while (start < end) {
-		cache32_unroll32(start,Index_Writeback_Inv_D);
-		start += 0x400;
+	unsigned long way0 = KSEG0;
+	unsigned long way1 = way0 ^ 1;
+	unsigned long end = (way0 + dcache_way_size);
+
+	while (way0 < end) {
+		cache32_unroll16(way0, Index_Writeback_Inv_D);
+		cache32_unroll16(way1, Index_Writeback_Inv_D);
+		way0 += 0x200;
+		way1 += 0x200;
 	}
 }
 
@@ -189,22 +210,41 @@ extern inline void blast_dcache32_page(unsigned long page)
 	unsigned long end = page + PAGE_SIZE;
 
 	while (start < end) {
-		cache32_unroll32(start,Hit_Writeback_Inv_D);
-		start += 0x800;
+		cache32_unroll32(start, Hit_Writeback_Inv_D);
+		start += 0x400;
 	}
 }
 
 extern inline void blast_dcache32_page_indexed(unsigned long page)
 {
-	unsigned long start = page;
-	unsigned long end = (start + PAGE_SIZE);
+	unsigned long way0 = page;
+	unsigned long way1 = page ^ 1;
+	unsigned long end = page + PAGE_SIZE;
 
-	while (start < end) {
-		cache32_unroll32(start,Index_Writeback_Inv_D);
-		start += 0x400;
+	while (way0 < end) {
+		cache32_unroll16(way0, Index_Writeback_Inv_D);
+		cache32_unroll16(way1, Index_Writeback_Inv_D);
+		way0 += 0x200;
+		way1 += 0x200;
 	}
 }
 
+#define cache64_unroll16(base,op)				\
+	__asm__ __volatile__("					\
+		.set noreorder;					\
+		cache %1, 0x000(%0); cache %1, 0x040(%0);	\
+		cache %1, 0x080(%0); cache %1, 0x0c0(%0);	\
+		cache %1, 0x100(%0); cache %1, 0x140(%0);	\
+		cache %1, 0x180(%0); cache %1, 0x1c0(%0);	\
+		cache %1, 0x200(%0); cache %1, 0x240(%0);	\
+		cache %1, 0x280(%0); cache %1, 0x2c0(%0);	\
+		cache %1, 0x300(%0); cache %1, 0x340(%0);	\
+		cache %1, 0x380(%0); cache %1, 0x3c0(%0);	\
+		.set reorder"					\
+		:						\
+		: "r" (base),					\
+		  "i" (op));
+
 #define cache64_unroll32(base,op)				\
 	__asm__ __volatile__("					\
 		.set noreorder;					\
@@ -231,12 +271,15 @@ extern inline void blast_dcache32_page_indexed(unsigned long page)
 
 extern inline void blast_icache64(void)
 {
-	unsigned long start = KSEG0;
-	unsigned long end = KSEG0 + dcache_size;
-
-	while (start < end) {
-		cache64_unroll32(start,Index_Invalidate_I);
-		start += 0x800;
+	unsigned long way0 = KSEG0;
+	unsigned long way1 = way0 ^ 1;
+	unsigned long end = way0 + icache_way_size;
+
+	while (way0 < end) {
+		cache64_unroll16(way0,Index_Invalidate_I);
+		cache64_unroll16(way1,Index_Invalidate_I);
+		way0 += 0x400;
+		way1 += 0x400;
 	}
 }
 
@@ -253,23 +296,29 @@ extern inline void blast_icache64_page(unsigned long page)
 
 extern inline void blast_icache64_page_indexed(unsigned long page)
 {
-	unsigned long start = page;
+	unsigned long way0 = page;
+	unsigned long way1 = page ^ 1;
 	unsigned long end = page + PAGE_SIZE;
 
-	while (start < end) {
-		cache64_unroll32(start,Index_Invalidate_I);
-		start += 0x800;
+	while (way0 < end) {
+		cache64_unroll16(way0,Index_Invalidate_I);
+		cache64_unroll16(way1,Index_Invalidate_I);
+		way0 += 0x400;
+		way1 += 0x400;
 	}
 }
 
 extern inline void blast_scache64(void)
 {
-	unsigned long start = KSEG0;
+	unsigned long way0 = KSEG0;
+	unsigned long way1 = way0 ^ 1;
 	unsigned long end = KSEG0 + scache_size();
 
-	while (start < end) {
-		cache64_unroll32(start,Index_Writeback_Inv_S);
-		start += 0x800;
+	while (way0 < end) {
+		cache64_unroll16(way0,Index_Writeback_Inv_S);
+		cache64_unroll16(way1,Index_Writeback_Inv_S);
+		way0 += 0x400;
+		way1 += 0x400;
 	}
 }
 
@@ -286,15 +335,34 @@ extern inline void blast_scache64_page(unsigned long page)
 
 extern inline void blast_scache64_page_indexed(unsigned long page)
 {
-	unsigned long start = page;
+	unsigned long way0 = page;
+	unsigned long way1 = page ^ 1;
 	unsigned long end = page + PAGE_SIZE;
 
-	while (start < end) {
-		cache64_unroll32(start,Index_Writeback_Inv_S);
-		start += 0x800;
+	while (way0 < end) {
+		cache64_unroll16(way0,Index_Writeback_Inv_S);
+		cache64_unroll16(way1,Index_Writeback_Inv_S);
+		way0 += 0x400;
+		way1 += 0x400;
 	}
 }
 
+#define cache128_unroll16(base,op)				\
+	__asm__ __volatile__("					\
+		.set noreorder;					\
+		cache %1, 0x000(%0); cache %1, 0x080(%0);	\
+		cache %1, 0x100(%0); cache %1, 0x180(%0);	\
+		cache %1, 0x200(%0); cache %1, 0x280(%0);	\
+		cache %1, 0x300(%0); cache %1, 0x380(%0);	\
+		cache %1, 0x400(%0); cache %1, 0x480(%0);	\
+		cache %1, 0x500(%0); cache %1, 0x580(%0);	\
+		cache %1, 0x600(%0); cache %1, 0x680(%0);	\
+		cache %1, 0x700(%0); cache %1, 0x780(%0);	\
+		.set reorder"					\
+		:						\
+		: "r" (base),					\
+		  "i" (op));
+
 #define cache128_unroll32(base,op)				\
 	__asm__ __volatile__("					\
 		.set noreorder;					\
@@ -321,23 +389,27 @@ extern inline void blast_scache64_page_indexed(unsigned long page)
 
 extern inline void blast_scache128(void)
 {
-	unsigned long start = KSEG0;
-	unsigned long end = KSEG0 + scache_size();
-
-	while (start < end) {
-		cache128_unroll32(start,Index_Writeback_Inv_S);
-		start += 0x1000;
+	unsigned long way0 = KSEG0;
+	unsigned long way1 = way0 ^ 1;
+	unsigned long end = way0 + scache_size();
+
+	while (way0 < end) {
+		cache128_unroll16(way0, Index_Writeback_Inv_S);
+		cache128_unroll16(way1, Index_Writeback_Inv_S);
+		way0 += 0x800;
+		way1 += 0x800;
 	}
 }
 
 extern inline void blast_scache128_page(unsigned long page)
 {
-	cache128_unroll32(page,Hit_Writeback_Inv_S);
+	cache128_unroll32(page, Hit_Writeback_Inv_S);
 }
 
 extern inline void blast_scache128_page_indexed(unsigned long page)
 {
-	cache128_unroll32(page,Index_Writeback_Inv_S);
+	cache128_unroll32(page    , Index_Writeback_Inv_S);
+	cache128_unroll32(page ^ 1, Index_Writeback_Inv_S);
 }
 
 #endif /* _ASM_R10KCACHE_H */
diff --git a/include/asm-mips64/r4kcache.h b/include/asm-mips64/r4kcache.h
index 6801259dd..cee70ceb9 100644
--- a/include/asm-mips64/r4kcache.h
+++ b/include/asm-mips64/r4kcache.h
@@ -14,7 +14,7 @@
 #define _ASM_R4KCACHE_H
 
 #include <asm/asm.h>
-#include <asm/cacheops.h>
+#include <asm/r4kcacheops.h>
 
 extern inline void flush_icache_line_indexed(unsigned long addr)
 {
diff --git a/include/asm-mips64/r4kcacheops.h b/include/asm-mips64/r4kcacheops.h
new file mode 100644
index 000000000..bc4b924ed
--- /dev/null
+++ b/include/asm-mips64/r4kcacheops.h
@@ -0,0 +1,48 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Cache operations for the cache instruction.
+ *
+ * (C) Copyright 1996, 1997, 1999 by Ralf Baechle
+ */
+#ifndef	_ASM_R4kCACHEOPS_H
+#define	_ASM_R4kCACHEOPS_H
+
+/*
+ * Cache Operations
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_I	0x04
+#define Index_Load_Tag_D	0x05
+#define Index_Load_Tag_SI	0x06
+#define Index_Load_Tag_SD	0x07
+#define Index_Store_Tag_I	0x08
+#define Index_Store_Tag_D	0x09
+#define Index_Store_Tag_SI	0x0A
+#define Index_Store_Tag_SD	0x0B
+#define Create_Dirty_Excl_D	0x0d
+#define Create_Dirty_Excl_SD	0x0f
+#define Hit_Invalidate_I	0x10
+#define Hit_Invalidate_D	0x11
+#define Hit_Invalidate_SI	0x12
+#define Hit_Invalidate_SD	0x13
+#define Fill			0x14
+#define Hit_Writeback_Inv_D	0x15
+					/* 0x16 is unused */
+#define Hit_Writeback_Inv_SD	0x17
+#define Hit_Writeback_I		0x18
+#define Hit_Writeback_D		0x19
+					/* 0x1a is unused */
+#define Hit_Writeback_SD	0x1b
+					/* 0x1c is unused */
+					/* 0x1e is unused */
+#define Hit_Set_Virtual_SI	0x1e
+#define Hit_Set_Virtual_SD	0x1f
+
+#endif	/* _ASM_R4kCACHEOPS_H */
diff --git a/include/asm-mips64/serial.h b/include/asm-mips64/serial.h
index 2b148a7d8..c6b3245d7 100644
--- a/include/asm-mips64/serial.h
+++ b/include/asm-mips64/serial.h
@@ -1,4 +1,4 @@
-/* $Id: serial.h,v 1.1 2000/01/04 10:37:18 ralf Exp $
+/* $Id: serial.h,v 1.1 2000/01/04 10:51:55 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -37,8 +37,8 @@
 
 #ifdef CONFIG_SGI_IP27
 #define ORIGIN_SERIAL_PORT_DFNS						\
-	{ 0, IOC3_BAUD, 0x9200000008620178, IOC3_SERIAL_INT, IOC3_COM_FLAGS },\
-	{ 0, IOC3_BAUD, 0x9200000008620170, IOC3_SERIAL_INT, IOC3_COM_FLAGS },
+	{ 0, IOC3_BAUD, 0x9200000008620178, 0, IOC3_COM_FLAGS },\
+	{ 0, IOC3_BAUD, 0x9200000008620170, 0, IOC3_COM_FLAGS },
 #else
 #define ORIGIN_SERIAL_PORT_DFNS
 #endif
diff --git a/include/asm-mips64/sgialib.h b/include/asm-mips64/sgialib.h
index cafa0aa1c..ab02c8fd9 100644
--- a/include/asm-mips64/sgialib.h
+++ b/include/asm-mips64/sgialib.h
@@ -1,4 +1,4 @@
-/* $Id: sgialib.h,v 1.2 1999/08/20 21:59:08 ralf Exp $
+/* $Id: sgialib.h,v 1.3 1999/12/04 03:59:12 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -42,7 +42,7 @@ extern void prom_printf(char *fmt, ...);
 /* Memory descriptor management. */
 #define PROM_MAX_PMEMBLOCKS    32
 struct prom_pmemblock {
-	LONG	base;		/* Within KSEG0. */
+	LONG	base;		/* Within KSEG0 or XKPHYS. */
 	ULONG size;		/* In bytes. */
         ULONG type;		/* free or prom memory */
 };
@@ -120,13 +120,13 @@ extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **ar
 extern long prom_exec(char *name, long argc, char **argv, char **envp);
 
 /* Misc. routines. */
-extern void prom_halt(void) __attribute__((noreturn));
-extern void prom_powerdown(void) __attribute__((noreturn));
-extern void prom_restart(void) __attribute__((noreturn));
+extern void prom_halt(VOID) __attribute__((noreturn));
+extern void prom_powerdown(VOID) __attribute__((noreturn));
+extern void prom_restart(VOID) __attribute__((noreturn));
 extern VOID ArcReboot(VOID) __attribute__((noreturn));
-extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn));
-extern long prom_cfgsave(void);
-extern struct linux_sysid *prom_getsysid(void);
-extern void prom_cacheflush(void);
+extern VOID ArcEnterInteractiveMode(void) __attribute__((noreturn));
+extern long prom_cfgsave(VOID);
+extern struct linux_sysid *prom_getsysid(VOID);
+extern VOID ArcFlushAllCaches(VOID);
 
 #endif /* _ASM_SGIALIB_H */
diff --git a/include/asm-mips64/sgiarcs.h b/include/asm-mips64/sgiarcs.h
index 632920b3b..457c03af1 100644
--- a/include/asm-mips64/sgiarcs.h
+++ b/include/asm-mips64/sgiarcs.h
@@ -1,4 +1,4 @@
-/* $Id: sgiarcs.h,v 1.3 1999/08/21 22:19:17 ralf Exp $
+/* $Id: sgiarcs.h,v 1.4 1999/12/04 03:59:12 ralf Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -13,6 +13,7 @@
 #ifndef _ASM_SGIARCS_H
 #define _ASM_SGIARCS_H
 
+#include <linux/config.h>
 #include <asm/arc/types.h>
 
 /* Various ARCS error codes. */
@@ -364,6 +365,7 @@ struct linux_smonblock {
  * Macros for calling a 32-bit ARC implementation from 64-bit code
  */
 
+#ifdef CONFIG_ARC32
 #define __arc_clobbers							\
 	"$2","$3","$4","$5","$6","$7","$8","$9","$10","$11",		\
 	"$12","$13","$14","$15","$16","$24","25","$31"
@@ -470,5 +472,73 @@ struct linux_smonblock {
 	: __arc_clobbers);						\
 	__res;								\
 })
+#endif /* CONFIG_ARC32 */
+
+#ifdef CONFIG_ARC64
+
+#define ARC_CALL0(dest)							\
+({	long __res;							\
+	long (*__vec)(void) = (void *) romvec->dest;			\
+									\
+	__res = __vec();						\
+	__res;								\
+})
+
+#define ARC_CALL1(dest,a1)						\
+({	long __res;							\
+	long __a1 = (long) (a1);					\
+	long (*__vec)(long) = (void *) romvec->dest;			\
+									\
+	__res = __vec(__a1);						\
+	__res;								\
+})
+
+#define ARC_CALL2(dest,a1,a2)						\
+({	long __res;							\
+	long __a1 = (long) (a1);					\
+	long __a2 = (long) (a2);					\
+	long (*__vec)(long, long) = (void *) romvec->dest;		\
+									\
+	__res = __vec(__a1, __a2);					\
+	__res;								\
+})
+
+#define ARC_CALL3(dest,a1,a2,a3)					\
+({	long __res;							\
+	long __a1 = (long) (a1);					\
+	long __a2 = (long) (a2);					\
+	long __a3 = (long) (a3);					\
+	long (*__vec)(long, long, long)	= (void *) romvec->dest;	\
+									\
+	__res = __vec(__a1, __a2, __a3);				\
+	__res;								\
+})
+
+#define ARC_CALL4(dest,a1,a2,a3,a4)					\
+({	long __res;							\
+	long __a1 = (long) (a1);					\
+	long __a2 = (long) (a2);					\
+	long __a3 = (long) (a3);					\
+	long __a4 = (long) (a4);					\
+	long (*__vec)(long, long, long, long) = (void *) romvec->dest;	\
+									\
+	__res = __vec(__a1, __a2, __a3, __a4);				\
+	__res;								\
+})
+
+#define ARC_CALL5(dest,a1,a2,a3,a4,a5)					\
+({	long __res;							\
+	long __a1 = (long) (a1);					\
+	long __a2 = (long) (a2);					\
+	long __a3 = (long) (a3);					\
+	long __a4 = (long) (a4);					\
+	long __a5 = (long) (a5);					\
+	long (*__vec)(long, long, long, long, long);			\
+	__vec = (void *) romvec->dest;					\
+									\
+	__res = __vec(__a1, __a2, __a3, __a4, __a5);			\
+	__res;								\
+})
+#endif /* CONFIG_ARC64 */
 
 #endif /* _ASM_SGIARCS_H */
diff --git a/include/linux/serial.h b/include/linux/serial.h
index e1ad16ae6..3cc56b08f 100644
--- a/include/linux/serial.h
+++ b/include/linux/serial.h
@@ -95,6 +95,7 @@ struct serial_uart_config {
 #define ASYNC_FLAGS	0x3FFF	/* Possible legal async flags */
 #define ASYNC_USR_MASK	0x3430	/* Legal flags that non-privileged
 				 * users can set or reset */
+#define ASYNC_IOC3	0x4000	/* SGI IOC3 serial */
 
 /* Internal flags used only by kernel/chr_drv/serial.c */
 #define ASYNC_INITIALIZED	0x80000000 /* Serial port was initialized */
diff --git a/include/linux/serialP.h b/include/linux/serialP.h
index 02fcb9363..3726d9b5d 100644
--- a/include/linux/serialP.h
+++ b/include/linux/serialP.h
@@ -39,7 +39,7 @@ struct async_icount {
 struct serial_state {
 	int	magic;
 	int	baud_base;
-	int	port;
+	unsigned long	port;
 	int	irq;
 	int	flags;
 	int	hub6;
@@ -54,14 +54,14 @@ struct serial_state {
 	unsigned short	close_delay;
 	unsigned short	closing_wait; /* time to wait before closing */
 	struct async_icount	icount;	
-	struct termios		normal_termios;
+	struct termios	normal_termios;
 	struct termios		callout_termios;
 	struct async_struct *info;
 };
 
 struct async_struct {
 	int			magic;
-	int			port;
+	unsigned long		port;
 	int			hub6;
 	int			flags;
 	int			xmit_fifo_size;