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-rw-r--r--arch/mips/ddb5074/setup.c4
-rw-r--r--arch/mips/ddb5476/irq.c4
-rw-r--r--arch/mips/dec/irq.c4
-rw-r--r--arch/mips/galileo-boards/ev64120/irq.c13
-rw-r--r--arch/mips/galileo-boards/ev64120/reset.c4
-rw-r--r--arch/mips/galileo-boards/ev64120/setup.c2
-rw-r--r--arch/mips/galileo-boards/ev96100/time.c2
-rw-r--r--arch/mips/gt64120/momenco_ocelot/irq.c6
-rw-r--r--arch/mips/gt64120/momenco_ocelot/reset.c2
-rw-r--r--arch/mips/ite-boards/generic/irq.c2
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c2
-rw-r--r--arch/mips/ite-boards/generic/reset.c4
-rw-r--r--arch/mips/jazz/setup.c2
-rw-r--r--arch/mips/kernel/process.c6
-rw-r--r--arch/mips/kernel/signal.c2
-rw-r--r--arch/mips/kernel/traps.c6
-rw-r--r--arch/mips/mips-boards/generic/time.c2
-rw-r--r--arch/mips/mm/r4xx0.c4
-rw-r--r--arch/mips/mm/r5432.c2
-rw-r--r--arch/mips/philips/nino/setup.c4
-rw-r--r--arch/mips/sgi/kernel/setup.c2
-rw-r--r--include/asm-mips/mipsregs.h28
22 files changed, 65 insertions, 42 deletions
diff --git a/arch/mips/ddb5074/setup.c b/arch/mips/ddb5074/setup.c
index d8cc518de..8091163fe 100644
--- a/arch/mips/ddb5074/setup.c
+++ b/arch/mips/ddb5074/setup.c
@@ -87,8 +87,8 @@ static void __init ddb_time_init(struct irqaction *irq)
/* enable interrupt */
nile4_enable_irq(NILE4_INT_GPT);
i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
- set_cp0_status(ST0_IM,
- IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
+ change_cp0_status(ST0_IM,
+ IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
}
void __init ddb_setup(void)
diff --git a/arch/mips/ddb5476/irq.c b/arch/mips/ddb5476/irq.c
index 4a39d613e..ea888894b 100644
--- a/arch/mips/ddb5476/irq.c
+++ b/arch/mips/ddb5476/irq.c
@@ -244,8 +244,8 @@ void __init ddb_irq_setup(void)
m1543_irq_setup();
/* we pin #0 - #4 (no internal timer) */
- set_cp0_status(ST0_IM,
- IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
+ change_cp0_status(ST0_IM,
+ IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
set_except_vector(0, ddbIRQ);
}
diff --git a/arch/mips/dec/irq.c b/arch/mips/dec/irq.c
index 95bdc9ca2..2f1951887 100644
--- a/arch/mips/dec/irq.c
+++ b/arch/mips/dec/irq.c
@@ -36,7 +36,7 @@ static inline void mask_irq(unsigned int irq_nr)
dummy = *imr;
dummy = *imr;
} else /* This is a cpu interrupt */
- set_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) & ~dec_interrupt[irq_nr].cpu_mask);
+ change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) & ~dec_interrupt[irq_nr].cpu_mask);
}
static inline void unmask_irq(unsigned int irq_nr)
@@ -48,7 +48,7 @@ static inline void unmask_irq(unsigned int irq_nr)
dummy = *imr;
dummy = *imr;
}
- set_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) | dec_interrupt[irq_nr].cpu_mask);
+ change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) | dec_interrupt[irq_nr].cpu_mask);
}
void disable_irq(unsigned int irq_nr)
diff --git a/arch/mips/galileo-boards/ev64120/irq.c b/arch/mips/galileo-boards/ev64120/irq.c
index ff2d0c25f..49591fdb0 100644
--- a/arch/mips/galileo-boards/ev64120/irq.c
+++ b/arch/mips/galileo-boards/ev64120/irq.c
@@ -420,18 +420,18 @@ void galileo_irq_setup(void)
/*
* Clear all of the interrupts while we change the able around a bit.
*/
- set_cp0_status(ST0_IM, 0);
- set_cp0_status(ST0_BEV, 1); /* int-handler is not on bootstrap */
+ clear_cp0_status(ST0_IM | ST0_BEV);
/* Sets the exception_handler array. */
set_except_vector(0, galileo_handle_int);
cli();
-/*
- Enable timer. Other interrupts will be enabled as they are registered.
-*/
- set_cp0_status(ST0_IM, IE_IRQ2);
+ /*
+ * Enable timer. Other interrupts will be enabled as they are
+ * registered.
+ */
+ set_cp0_status(IE_IRQ2);
#ifdef CONFIG_REMOTE_DEBUG
@@ -443,7 +443,6 @@ void galileo_irq_setup(void)
breakpoint(); /* you may move this line to whereever you want :-) */
}
#endif
-
}
diff --git a/arch/mips/galileo-boards/ev64120/reset.c b/arch/mips/galileo-boards/ev64120/reset.c
index 8f801c8f3..e060b33b7 100644
--- a/arch/mips/galileo-boards/ev64120/reset.c
+++ b/arch/mips/galileo-boards/ev64120/reset.c
@@ -22,8 +22,8 @@ void galileo_machine_restart(char *command)
* kernel in the flush locks up somewhen during of after the PCI
* detection stuff.
*/
- set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
- set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ set_cp0_status(ST0_BEV | ST0_ERL);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
diff --git a/arch/mips/galileo-boards/ev64120/setup.c b/arch/mips/galileo-boards/ev64120/setup.c
index f983a1c27..a04088aef 100644
--- a/arch/mips/galileo-boards/ev64120/setup.c
+++ b/arch/mips/galileo-boards/ev64120/setup.c
@@ -133,7 +133,7 @@ void ev64120_setup(void)
board_time_init = galileo_time_init;
mips_io_port_base = KSEG1;
- set_cp0_status(ST0_FR, 0);
+ clear_cp0_status(ST0_FR);
#ifdef CONFIG_L2_L3_CACHE
#error "external cache not implemented yet"
diff --git a/arch/mips/galileo-boards/ev96100/time.c b/arch/mips/galileo-boards/ev96100/time.c
index d5e66fe7b..80283c929 100644
--- a/arch/mips/galileo-boards/ev96100/time.c
+++ b/arch/mips/galileo-boards/ev96100/time.c
@@ -149,7 +149,7 @@ void __init time_init(void)
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
/* FIX ME */
- set_cp0_status(ST0_IM, IE_IRQ5);
+ change_cp0_status(ST0_IM, IE_IRQ5);
}
/* This is for machines which generate the exact clock. */
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c
index 407031e6a..d93b86a7b 100644
--- a/arch/mips/gt64120/momenco_ocelot/irq.c
+++ b/arch/mips/gt64120/momenco_ocelot/irq.c
@@ -129,9 +129,9 @@ void momenco_ocelot_irq_setup(void)
/*
* Clear all of the interrupts while we change the able around a bit.
+ * int-handler is not on bootstrap
*/
- set_cp0_status(ST0_IM, 0);
- set_cp0_status(ST0_BEV, 1); /* int-handler is not on bootstrap */
+ clear_cp0_status(ST0_IM | ST0_BEV);
/* Sets the first-level interrupt dispatcher. */
set_except_vector(0, ocelot_handle_int);
@@ -142,7 +142,7 @@ void momenco_ocelot_irq_setup(void)
* Enable timer. Other interrupts will be enabled as they are
* registered.
*/
- // set_cp0_status(ST0_IM, IE_IRQ4);
+ // change_cp0_status(ST0_IM, IE_IRQ4);
#ifdef CONFIG_REMOTE_DEBUG
diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c
index 0f4c7fee6..a54b9d6ff 100644
--- a/arch/mips/gt64120/momenco_ocelot/reset.c
+++ b/arch/mips/gt64120/momenco_ocelot/reset.c
@@ -26,7 +26,7 @@ void momenco_ocelot_restart(char *command)
* kernel in the flush locks up somewhen during of after the PCI
* detection stuff.
*/
- set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
+ clear_cp0_status(ST0_BEV | ST0_ERL);
set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c
index 4a10e0b47..7c8870d12 100644
--- a/arch/mips/ite-boards/generic/irq.c
+++ b/arch/mips/ite-boards/generic/irq.c
@@ -440,7 +440,7 @@ void __init init_IRQ(void)
* All ITE interrupts are masked for now.
*/
enable_irq(1<<EXT_IRQ0_TO_IP);
- //set_cp0_status(ST0_IM, IE_IRQ2);
+ //change_cp0_status(ST0_IM, IE_IRQ2);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
index e111c71cc..8e7f67edd 100644
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ b/arch/mips/ite-boards/generic/it8172_setup.c
@@ -127,7 +127,7 @@ void __init it8172_setup(void)
}
#endif
- set_cp0_status(ST0_FR,0);
+ clear_cp0_status(ST0_FR);
rtc_ops = &it8172_rtc_ops;
_machine_restart = it8172_restart;
diff --git a/arch/mips/ite-boards/generic/reset.c b/arch/mips/ite-boards/generic/reset.c
index 22bcf79ff..1e013c93d 100644
--- a/arch/mips/ite-boards/generic/reset.c
+++ b/arch/mips/ite-boards/generic/reset.c
@@ -39,8 +39,8 @@
void it8172_restart(char *command)
{
- set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
- set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ set_cp0_status(ST0_BEV | ST0_ERL);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 91d2f176b..9b125c255 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -71,7 +71,7 @@ static void __init jazz_irq_setup(void)
JAZZ_IE_FLOPPY);
r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
r4030_read_reg32(JAZZ_R4030_INVAL_ADDR); /* clear error bits */
- set_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1);
+ change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1);
/* set the clock to 100 Hz */
r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
request_region(0x20, 0x20, "pic1");
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index dd2810109..6cda842fd 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -56,7 +56,7 @@ void exit_thread(void)
{
/* Forget lazy fpu state */
if (last_task_used_math == current) {
- set_cp0_status(ST0_CU1, ST0_CU1);
+ set_cp0_status(ST0_CU1);
__asm__ __volatile__("cfc1\t$0,$31");
last_task_used_math = NULL;
}
@@ -66,7 +66,7 @@ void flush_thread(void)
{
/* Forget lazy fpu state */
if (last_task_used_math == current) {
- set_cp0_status(ST0_CU1, ST0_CU1);
+ set_cp0_status(ST0_CU1);
__asm__ __volatile__("cfc1\t$0,$31");
last_task_used_math = NULL;
}
@@ -87,7 +87,7 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
if (mips_cpu.options & MIPS_CPU_FPU)
#endif
{
- set_cp0_status(ST0_CU1, ST0_CU1);
+ set_cp0_status(ST0_CU1);
save_fp(p);
}
/* set up new TSS. */
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index ff7c8d5a8..b91e8a0b9 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -354,7 +354,7 @@ setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
err |= __put_user(owned_fp, &sc->sc_ownedfp);
if (current->used_math) { /* fp is active. */
- set_cp0_status(ST0_CU1, ST0_CU1);
+ set_cp0_status(ST0_CU1);
err |= save_fp_context(sc);
last_task_used_math = NULL;
regs->cp0_status &= ~ST0_CU1;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 402975288..363dfd778 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -702,7 +702,7 @@ static inline void setup_dedicated_int(void)
if(mips_cpu.options & MIPS_CPU_DIVEC) {
memcpy((void *)(KSEG0 + 0x200), except_vec4, 8);
- set_cp0_cause(CAUSEF_IV, CAUSEF_IV);
+ set_cp0_cause(CAUSEF_IV);
dedicated_iv_available = 1;
}
}
@@ -785,7 +785,7 @@ void __init trap_init(void)
EISA_bus = 1;
/* Some firmware leaves the BEV flag set, clear it. */
- set_cp0_status(ST0_BEV, 0);
+ clear_cp0_status(ST0_BEV);
/* Copy the generic exception handler code to it's final destination. */
memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
@@ -878,7 +878,7 @@ void __init trap_init(void)
* should get some special optimizations.
*/
write_32bit_cp0_register(CP0_FRAMEMASK, 0);
- set_cp0_status(ST0_XX, ST0_XX);
+ set_cp0_status(ST0_XX);
/*
* The R10k might even work for Linux/MIPS - but we're paranoid
* and refuse to run until this is tested on real silicon
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index ee08dd5ac..8819f464a 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -264,7 +264,7 @@ void __init time_init(void)
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
- set_cp0_status(ST0_IM, ALLINTS);
+ change_cp0_status(ST0_IM, ALLINTS);
/* Read time from the RTC chipset. */
write_lock_irqsave (&xtime_lock, flags);
diff --git a/arch/mips/mm/r4xx0.c b/arch/mips/mm/r4xx0.c
index f4c05d8a3..06a19ee44 100644
--- a/arch/mips/mm/r4xx0.c
+++ b/arch/mips/mm/r4xx0.c
@@ -2675,9 +2675,9 @@ void __init ld_mmu_r4xx0(void)
printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
#ifdef CONFIG_MIPS_UNCACHED
- set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
#else
- set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
#endif
probe_icache(config);
diff --git a/arch/mips/mm/r5432.c b/arch/mips/mm/r5432.c
index 80fa8deef..d6a420728 100644
--- a/arch/mips/mm/r5432.c
+++ b/arch/mips/mm/r5432.c
@@ -832,7 +832,7 @@ void __init ld_mmu_r5432(void)
printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
- set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
probe_icache(config);
probe_dcache(config);
diff --git a/arch/mips/philips/nino/setup.c b/arch/mips/philips/nino/setup.c
index 7ac6cdf06..2554d3bfb 100644
--- a/arch/mips/philips/nino/setup.c
+++ b/arch/mips/philips/nino/setup.c
@@ -58,9 +58,9 @@ static void __init nino_irq_setup(void)
* Enable only the interrupts for the UART and negative
* edge (1-to-0) triggered multi-function I/O pins.
*/
- set_cp0_status(ST0_BEV, 0);
+ clear_cp0_status(ST0_BEV);
tmp = read_32bit_cp0_register(CP0_STATUS);
- set_cp0_status(ST0_IM, tmp | IE_IRQ2 | IE_IRQ4);
+ change_cp0_status(ST0_IM, tmp | IE_IRQ2 | IE_IRQ4);
/* Register the global interrupt handler */
set_except_vector(0, nino_handle_int);
diff --git a/arch/mips/sgi/kernel/setup.c b/arch/mips/sgi/kernel/setup.c
index c6ae803d2..09a291844 100644
--- a/arch/mips/sgi/kernel/setup.c
+++ b/arch/mips/sgi/kernel/setup.c
@@ -219,7 +219,7 @@ void sgi_time_init (struct irqaction *irq) {
/* Set ourselves up for future interrupts */
r4k_next = (read_32bit_cp0_register(CP0_COUNT) + r4k_interval);
write_32bit_cp0_register(CP0_COMPARE, r4k_next);
- set_cp0_status(ST0_IM, ALLINTS);
+ change_cp0_status(ST0_IM, ALLINTS);
sti ();
}
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index c5d8ac759..9692eb57a 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1994, 1995, 1996, 1997, 2000 by Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
* Copyright (C) 2000 Silicon Graphics, Inc.
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
@@ -238,7 +238,31 @@
*/
#define __BUILD_SET_CP0(name,register) \
extern __inline__ unsigned int \
-set_cp0_##name(unsigned int change, unsigned int new) \
+set_cp0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res |= ~set; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+extern __inline__ unsigned int \
+clear_cp0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~clear; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+extern __inline__ unsigned int \
+change_cp0_##name(unsigned int change, unsigned int new) \
{ \
unsigned int res; \
\
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:34:01 +0000