diff options
| -rw-r--r-- | arch/mips64/mm/andes.c | 22 | ||||
| -rw-r--r-- | arch/mips64/mm/loadmmu.c | 6 | ||||
| -rw-r--r-- | arch/mips64/mm/r4xx0.c | 6 | ||||
| -rw-r--r-- | arch/mips64/sgi-ip27/ip27-init.c | 2 | ||||
| -rw-r--r-- | arch/mips64/sgi-ip27/ip27-memory.c | 21 | ||||
| -rw-r--r-- | include/asm-mips64/pgtable.h | 12 |
6 files changed, 46 insertions, 23 deletions
diff --git a/arch/mips64/mm/andes.c b/arch/mips64/mm/andes.c index 885443032..fa140bf94 100644 --- a/arch/mips64/mm/andes.c +++ b/arch/mips64/mm/andes.c @@ -6,6 +6,7 @@ * * Copyright (C) 1997, 1998, 1999 Ralf Baechle (ralf@gnu.org) * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com) */ #include <linux/init.h> #include <linux/kernel.h> @@ -88,6 +89,26 @@ andes_flush_cache_all(void) blast_dcache32(); blast_icache64(); } +/* + * This is only used during initialization time. vmalloc() also calls + * this, but that will be changed pretty soon. + */ +static void +andes_flush_cache_l2(void) +{ + switch (sc_lsize()) { + case 64: + blast_scache64(); + break; + case 128: + blast_scache128(); + break; + default: + printk("Unknown L2 line size\n"); + while(1); + } +} + static void andes_flush_cache_mm(struct mm_struct *mm) { @@ -441,6 +462,7 @@ void __init ld_mmu_andes(void) _copy_page = andes_copy_page; _flush_cache_all = andes_flush_cache_all; + _flush_cache_l2 = andes_flush_cache_l2; _flush_cache_mm = andes_flush_cache_mm; _flush_cache_range = andes_flush_cache_range; _flush_cache_page = andes_flush_cache_page; diff --git a/arch/mips64/mm/loadmmu.c b/arch/mips64/mm/loadmmu.c index 69f661c0b..b8d04273d 100644 --- a/arch/mips64/mm/loadmmu.c +++ b/arch/mips64/mm/loadmmu.c @@ -30,9 +30,13 @@ void (*_flush_cache_mm)(struct mm_struct *mm); void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start, unsigned long end); void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); -void (*_flush_cache_sigtramp)(unsigned long addr); void (*_flush_page_to_ram)(struct page * page); +/* MIPS specific cache operations */ +void (*_flush_cache_sigtramp)(unsigned long addr); +void (*_flush_cache_l2)(void); + + /* DMA cache operations. */ void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); void (*_dma_cache_wback)(unsigned long start, unsigned long size); diff --git a/arch/mips64/mm/r4xx0.c b/arch/mips64/mm/r4xx0.c index 2b3ca03a4..84078b824 100644 --- a/arch/mips64/mm/r4xx0.c +++ b/arch/mips64/mm/r4xx0.c @@ -2146,6 +2146,11 @@ static void r4k_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) } } +static void +r4k_flush_cache_l2(void) +{ +} + #ifdef DEBUG_TLBUPDATE static unsigned long ehi_debug[NTLB_ENTRIES]; static unsigned long el0_debug[NTLB_ENTRIES]; @@ -2538,6 +2543,7 @@ void __init ld_mmu_r4xx0(void) _flush_tlb_mm = r4k_flush_tlb_mm; _flush_tlb_range = r4k_flush_tlb_range; _flush_tlb_page = r4k_flush_tlb_page; + _flush_cache_l2 = r4k_flush_cache_l2; update_mmu_cache = r4k_update_mmu_cache; diff --git a/arch/mips64/sgi-ip27/ip27-init.c b/arch/mips64/sgi-ip27/ip27-init.c index 91bd7c9f5..f18b124a1 100644 --- a/arch/mips64/sgi-ip27/ip27-init.c +++ b/arch/mips64/sgi-ip27/ip27-init.c @@ -302,6 +302,7 @@ void per_hub_init(cnodeid_t cnode) memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x100); flush_cache_all(); + flush_cache_l2(); } #endif } @@ -419,6 +420,7 @@ void cboot(void) #endif _flush_tlb_all(); flush_cache_all(); + flush_cache_l2(); start_secondary(); } diff --git a/arch/mips64/sgi-ip27/ip27-memory.c b/arch/mips64/sgi-ip27/ip27-memory.c index 4900ff777..c31e00667 100644 --- a/arch/mips64/sgi-ip27/ip27-memory.c +++ b/arch/mips64/sgi-ip27/ip27-memory.c @@ -170,24 +170,6 @@ pfn_t szmem(pfn_t fpage, pfn_t maxpmem) } /* - * HACK ALERT - Things do not work if this is not here. Maybe this is - * acting as a pseudocacheflush operation. The write pattern seems to - * be important, writing a 0 does not help. - */ -void setup_test(cnodeid_t node, pfn_t start, pfn_t end) -{ - unsigned long *ptr = __va(start << PAGE_SHIFT); - unsigned long size = 4 * 1024 * 1024; /* 4M L2 caches */ - - while (size) { - size -= sizeof(unsigned long); - *ptr = (0xdeadbeefbabeb000UL|node); - /* *ptr = 0; */ - ptr++; - } -} - -/* * Currently, the intranode memory hole support assumes that each slot * contains at least 32 MBytes of memory. We assume all bootmem data * fits on the first slot. @@ -210,8 +192,7 @@ void __init prom_meminit(void) /* Foll line hack for non discontigmem; remove once discontigmem * becomes the default. */ max_low_pfn = (slot_lastpfn - slot_firstpfn); - if (node != 0) - setup_test(node, slot_freepfn, slot_lastpfn); + /* * Allocate the node data structure on the node first. */ diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h index b0c97ced1..867e78041 100644 --- a/include/asm-mips64/pgtable.h +++ b/include/asm-mips64/pgtable.h @@ -32,14 +32,12 @@ extern void (*_flush_cache_mm)(struct mm_struct *mm); extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start, unsigned long end); extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); -extern void (*_flush_cache_sigtramp)(unsigned long addr); extern void (*_flush_page_to_ram)(struct page * page); #define flush_cache_all() _flush_cache_all() #define flush_cache_mm(mm) _flush_cache_mm(mm) #define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end) #define flush_cache_page(vma,page) _flush_cache_page(vma, page) -#define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) #define flush_page_to_ram(page) _flush_page_to_ram(page) #define flush_icache_range(start, end) flush_cache_all() @@ -52,6 +50,16 @@ do { \ } while (0) /* + * The foll cache flushing routines are MIPS specific. + * flush_cache_l2 is needed only during initialization. + */ +extern void (*_flush_cache_sigtramp)(unsigned long addr); +extern void (*_flush_cache_l2)(void); + +#define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) +#define flush_cache_l2() _flush_cache_l2() + +/* * Each address space has 2 4K pages as its page directory, giving 1024 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to |