diff options
| -rw-r--r-- | include/asm-mips64/sn/sn1/addrs.h | 388 | ||||
| -rw-r--r-- | include/asm-mips64/sn/sn1/arch.h | 81 | ||||
| -rw-r--r-- | include/asm-mips64/sn/sn1/bdrkhspecregs.h | 553 | ||||
| -rw-r--r-- | include/asm-mips64/sn/sn1/bdrkhspecregs_next.h | 35 |
4 files changed, 1057 insertions, 0 deletions
diff --git a/include/asm-mips64/sn/sn1/addrs.h b/include/asm-mips64/sn/sn1/addrs.h new file mode 100644 index 000000000..d5da1b9f5 --- /dev/null +++ b/include/asm-mips64/sn/sn1/addrs.h @@ -0,0 +1,388 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_ADDRS_H +#define _ASM_SN_SN1_ADDRS_H + +/* + * IP35 (on a TRex) Address map + * + * This file contains a set of definitions and macros which are used + * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, + * and UNCAC) used by the IP35 architecture. It also contains addresses + * for "major" statically locatable PROM/Kernel data structures, such as + * the partition table, the configuration data structure, etc. + * We make an implicit assumption that the processor using this file + * follows the R12K's provisions for specifying uncached attributes; + * should this change, the base registers may very well become processor- + * dependent. + * + * For more information on the address spaces, see the "Local Resources" + * chapter of the Hub specification. + * + * NOTE: This header file is included both by C and by assembler source + * files. Please bracket any language-dependent definitions + * appropriately. + */ + +#include <linux/config.h> + +/* + * Some of the macros here need to be casted to appropriate types when used + * from C. They definitely must not be casted from assembly language so we + * use some new ANSI preprocessor stuff to paste these on where needed. + */ + +#if defined(_RUN_UNCACHED) +#define CAC_BASE 0x9600000000000000 +#else +#define CAC_BASE 0xa800000000000000 +#endif + +#define HSPEC_BASE 0x9000000000000000 +#define IO_BASE 0x9200000000000000 +#define MSPEC_BASE 0x9400000000000000 +#define UNCAC_BASE 0x9600000000000000 + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) + + +/* + * The following couple of definitions will eventually need to be variables, + * since the amount of address space assigned to each node depends on + * whether the system is running in N-mode (more nodes with less memory) + * or M-mode (fewer nodes with more memory). We expect that it will + * be a while before we need to make this decision dynamically, though, + * so for now we just use defines bracketed by an ifdef. + */ + +#if defined(N_MODE) + +#define NODE_SIZE_BITS 32 +#define BWIN_SIZE_BITS 28 + +#define NASID_BITS 8 +#define NASID_BITMASK (0xffLL) +#define NASID_SHFT 32 +#define NASID_META_BITS 1 +#define NASID_LOCAL_BITS 7 + +#define BDDIR_UPPER_MASK (UINT64_CAST 0x1ffffff << 4) +#define BDECC_UPPER_MASK (UINT64_CAST 0x1fffffff ) + +#else /* !defined(N_MODE), assume that M-mode is desired */ + +#define NODE_SIZE_BITS 33 +#define BWIN_SIZE_BITS 29 + +#define NASID_BITMASK (0x7fLL) +#define NASID_BITS 7 +#define NASID_SHFT 33 +#define NASID_META_BITS 0 +#define NASID_LOCAL_BITS 7 + +#define BDDIR_UPPER_MASK (UINT64_CAST 0x3ffffff << 4) +#define BDECC_UPPER_MASK (UINT64_CAST 0x3fffffff) + +#endif /* defined(N_MODE) */ + +#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) + +#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) +#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ + NASID_SHFT) & NASID_BITMASK) + +#if _LANGUAGE_C && !defined(_STANDALONE) +#define NODE_SWIN_BASE(nasid, widget) \ + ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ + : RAW_NODE_SWIN_BASE(nasid, widget)) +#else +#define NODE_SWIN_BASE(nasid, widget) \ + (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) +#endif /* _LANGUAGE_C */ + +/* + * The following definitions pertain to the IO special address + * space. They define the location of the big and little windows + * of any given node. + */ + +#define BWIN_INDEX_BITS 3 +#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) +#define BWIN_SIZEMASK (BWIN_SIZE - 1) +#define BWIN_WIDGET_MASK 0x7 +#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) +#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ + (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) + +#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) +#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) +/* + * Verify if addr belongs to large window address of node with "nasid" + * + * + * NOTE: "addr" is expected to be XKPHYS address, and NOT physical + * address + * + * + */ + +#define NODE_BWIN_ADDR(nasid, addr) \ + (((addr) >= NODE_BWIN_BASE0(nasid)) && \ + ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ + BWIN_SIZE))) + +/* + * The following define the major position-independent aliases used + * in IP27. + * CALIAS -- Varies in size, points to the first n bytes of memory + * on the reader's node. + */ + +#define CALIAS_BASE CAC_BASE + + + +#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ + ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) + +#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) + +#if _LANGUAGE_C +#define KERN_NMI_ADDR(nasid, slice) \ + TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ + (IP27_NMI_KREGS_CPU_SIZE * (slice))) +#endif /* _LANGUAGE_C */ + +#ifdef PROM + +#define MISC_PROM_BASE PHYS_TO_K0(0x01300000) +#define MISC_PROM_SIZE 0x200000 + +#define DIAG_BASE PHYS_TO_K0(0x01500000) +#define DIAG_SIZE 0x300000 + +#define ROUTE_BASE PHYS_TO_K0(0x01800000) +#define ROUTE_SIZE 0x200000 + +#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000) +#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000) +#define IP27PROM_CORP_MAX 32 +#define IP27PROM_CORP PHYS_TO_K0(0x01800000) +#define IP27PROM_CORP_SIZE 0x10000 +#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000) +#define IP27PROM_CORP_STKSIZE 0x2000 +#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000) +#define IP27PROM_DECOMP_SIZE 0xfff00 + +#define IP27PROM_BASE PHYS_TO_K0(0x01a00000) +#define IP27PROM_BASE_MAPPED (K2BASE | 0x1fc00000) +#define IP27PROM_SIZE_MAX 0x200000 + +/* Note: the PROM stacks are accessed via the TLB, so must lie + * within 2M of IP27PROM_BASE (or IP35prom/tlb.s must be fixed) + */ +#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000) +#define IP27PROM_STACK_C PHYS_TO_K0(0x01bf0000) +#define IP27PROM_STACK_SHFT 15 +#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT) + +#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000) +#define SLAVESTACK_SIZE 0x40000 + +#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000) +#define ENETBUFS_SIZE 0x20000 + +/* The route cache is only used by the CPU PROM and can be + safely overwritten as the IO PROM is loaded. */ +#define IP27PROM_DRT_CACHE_BASE IO6PROM_BASE +#define IP27PROM_DRT_CACHE_SIZE 0x2000 + +#define IO6PROM_BASE PHYS_TO_K0(0x03000000) +#define IO6PROM_SIZE 0x400000 +#define IO6PROM_BASE_MAPPED (K2BASE | 0x13000000) +#define IO6DPROM_BASE PHYS_TO_K0(0x03000000) +#define IO6DPROM_SIZE 0x200000 + +#define IP27PROM_PCFG PHYS_TO_K0(0x02000000) +#define IP27PROM_PCFG_SIZE 0xd0000 +#define IP27PROM_ERRDMP PHYS_TO_K1(0x020d0000) +#define IP27PROM_ERRDMP_SIZE 0xf000 + +#define IP27PROM_INIT_START PHYS_TO_K1(0x020d0000) +#define IP27PROM_CONSOLE PHYS_TO_K1(0x020df000) +#define IP27PROM_CONSOLE_SIZE 0x200 +#define IP27PROM_NETUART PHYS_TO_K1(0x020df200) +#define IP27PROM_NETUART_SIZE 0x100 +#define IP27PROM_UNUSED1 PHYS_TO_K1(0x020df300) +#define IP27PROM_UNUSED1_SIZE 0xd00 +#define IP27PROM_INIT_END PHYS_TO_K0(0x020e2000) + +#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00040000) +#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00310000) + +#define IP27PROM_INT_LAUNCH 10 /* and 11 */ +#define IP27PROM_INT_NETUART 12 /* through 17 */ +#endif /* PROM */ + +/* + * needed by symmon so it needs to be outside #if PROM + * (see also POD_ELSCSIZE) + */ +#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x020e0000) +#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x020e0800) +#define IP27PROM_ELSC_BASE_C PHYS_TO_K0(0x020e1000) +#define IP27PROM_ELSC_BASE_D PHYS_TO_K0(0x020e1800) +#define IP27PROM_ELSC_SHFT 11 +#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) + +#define FREEMEM_BASE PHYS_TO_K0(0x4000000) + +#define IO6PROM_STACK_SHFT 14 /* stack per cpu */ +#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) + +/* + * IP27 PROM vectors + */ + +#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000) +#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008) +#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010) +#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018) +#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020) +#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028) +#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030) +#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038) +#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040) +#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048) + +#define KL_UART_BASE LOCAL_HSPEC(HSPEC_UART_0) /* base of UART regs */ +#define KL_UART_CMD LOCAL_HSPEC(HSPEC_UART_0) /* UART command reg */ +#define KL_UART_DATA LOCAL_HSPEC(HSPEC_UART_1) /* UART data reg */ + +#if !_LANGUAGE_ASSEMBLY +/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc + * CACHE_ERR_SP_PTR could either contain an address to the stack, or + * the stack could start at CACHE_ERR_SP_PTR + */ +#if defined (HUB_ERR_STS_WAR) +#define CACHE_ERR_EFRAME 0x480 +#else /* HUB_ERR_STS_WAR */ +#define CACHE_ERR_EFRAME 0x400 +#endif /* HUB_ERR_STS_WAR */ + +#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) +#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ +#define CACHE_ERR_IBASE_PTR (0x1000 - 40) +#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) +#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) + +#endif /* !_LANGUAGE_ASSEMBLY */ + +/* Each CPU accesses UALIAS at a different physaddr, on 32k boundaries + * This determines the locations of the exception vectors + */ +#define UALIAS_FLIP_BASE UALIAS_BASE +#define UALIAS_FLIP_SHIFT 15 +#define UALIAS_FLIP_ADDR(_x) ((_x) ^ (cputoslice(getcpuid())<<UALIAS_FLIP_SHIFT)) + +#define EX_HANDLER_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT) +#define EX_HANDLER_ADDR(nasid, slice) \ + PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice)) +#define EX_HANDLER_SIZE 0x0400 + +#define EX_FRAME_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT | 0x400) +#define EX_FRAME_ADDR(nasid, slice) \ + PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice)) +#define EX_FRAME_SIZE 0x0c00 + +#define _ARCSPROM + +#ifdef _STANDALONE + +/* + * The PROM needs to pass the device base address and the + * device pci cfg space address to the device drivers during + * install. The COMPONENT->Key field is used for this purpose. + * Macros needed by IP27 device drivers to convert the + * COMPONENT->Key field to the respective base address. + * Key field looks as follows: + * + * +----------------------------------------------------+ + * |devnasid | widget |pciid |hubwidid|hstnasid | adap | + * | 2 | 1 | 1 | 1 | 2 | 1 | + * +----------------------------------------------------+ + * | | | | | | | + * 64 48 40 32 24 8 0 + * + * These are used by standalone drivers till the io infrastructure + * is in place. + */ + +#if _LANGUAGE_C + +#define uchar unsigned char + +#define KEY_DEVNASID_SHFT 48 +#define KEY_WIDID_SHFT 40 +#define KEY_PCIID_SHFT 32 +#define KEY_HUBWID_SHFT 24 +#define KEY_HSTNASID_SHFT 8 + +#define MK_SN0_KEY(nasid, widid, pciid) \ + ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\ + ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\ + ((__psunsigned_t)pciid) << KEY_PCIID_SHFT) + +#define ADD_HUBWID_KEY(key,hubwid)\ + (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT)) + +#define ADD_HSTNASID_KEY(key,hstnasid)\ + (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT)) + +#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT)) +#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT)) +#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT)) +#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT)) +#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT)) + +#define PCI_64_TARGID_SHFT 60 + +#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ + GET_WIDID_FROM_KEY(key))\ + | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key))) + +#define GET_PCICFGBASE_FROM_KEY(key) \ + (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ + GET_WIDID_FROM_KEY(key))\ + | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key))) + +#define GET_WIDBASE_FROM_KEY(key) \ + (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ + GET_WIDID_FROM_KEY(key))) + +#define PUT_INSTALL_STATUS(c,s) c->Revision = s +#define GET_INSTALL_STATUS(c) c->Revision + +#endif /* LANGUAGE_C */ + +#endif /* _STANDALONE */ + +#if defined (HUB_ERR_STS_WAR) + +#define ERR_STS_WAR_NASID 63 +#define ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100) + +#endif /* HUB_ERR_STS_WAR */ +#endif /* _ASM_SN_SN1_ADDRS_H */ diff --git a/include/asm-mips64/sn/sn1/arch.h b/include/asm-mips64/sn/sn1/arch.h new file mode 100644 index 000000000..4f7c3eb15 --- /dev/null +++ b/include/asm-mips64/sn/sn1/arch.h @@ -0,0 +1,81 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_ARCH_H +#define _ASM_SN_SN1_ARCH_H + +#if defined(N_MODE) +#error "ERROR constants defined only for M-mode" +#endif + +#include <linux/config.h> + +/* + * This is the maximum number of NASIDS that can be present in a system. + * (Highest NASID plus one.) + */ +#define MAX_NASIDS 128 + +/* + * MAXCPUS refers to the maximum number of CPUs in a single kernel. + * This is not necessarily the same as MAXNODES * CPUS_PER_NODE + */ +#define MAXCPUS 512 + +/* + * This is the maximum number of nodes that can be part of a kernel. + * Effectively, it's the maximum number of compact node ids (cnodeid_t). + * This is not necessarily the same as MAX_NASIDS. + */ +#define MAX_COMPACT_NODES 128 + +/* + * MAX_REGIONS refers to the maximum number of hardware partitioned regions. + */ +#define MAX_REGIONS 64 +#define MAX_NONPREMIUM_REGIONS 16 +#define MAX_PREMIUM_REGIONS MAX_REGIONS + + +/* + * MAX_PARITIONS refers to the maximum number of logically defined + * partitions the system can support. + */ +#define MAX_PARTITIONS MAX_REGIONS + + +#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) + +/* + * Slot constants for IP35 + */ + +#define MAX_MEM_SLOTS 8 /* max slots per node */ + +#if defined(N_MODE) +#error "N-mode not supported" +#endif + +#define SLOT_SHIFT (30) +#define SLOT_MIN_MEM_SIZE (64*1024*1024) + +/* + * two PIs per bedrock, two CPUs per PI + */ +#define NUM_SUBNODES 2 +#define SUBNODE_SHFT 1 +#define SUBNODE_MASK (0x1 << SUBNODE_SHFT) +#define LOCALCPU_SHFT 0 +#define LOCALCPU_MASK (0x1 << LOCALCPU_SHFT) +#define SUBNODE(slice) (((slice) & SUBNODE_MASK) >> SUBNODE_SHFT) +#define LOCALCPU(slice) (((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT) +#define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ + ((local) << LOCALCPU_SHFT)) + +#endif /* _ASM_SN_SN1_ARCH_H */ diff --git a/include/asm-mips64/sn/sn1/bdrkhspecregs.h b/include/asm-mips64/sn/sn1/bdrkhspecregs.h new file mode 100644 index 000000000..ae86d4f17 --- /dev/null +++ b/include/asm-mips64/sn/sn1/bdrkhspecregs.h @@ -0,0 +1,553 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_BDRKHSPECREGS_H +#define _ASM_SN_SN1_BDRKHSPECREGS_H + + +/************************************************************************ + * * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * + * * + * This file is created by an automated script. Any (minimal) changes * + * made manually to this file should be made with care. * + * * + * MAKE ALL ADDITIONS TO THE END OF THIS FILE * + * * + ************************************************************************/ + + +#define HSPEC_MEM_DIMM_INIT_0 0x00000000 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_MEM_DIMM_INIT_1 0x00000008 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_MEM_DIMM_INIT_2 0x00000010 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_MEM_DIMM_INIT_3 0x00000018 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_MEM_DIMM_INIT_4 0x00000020 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_MEM_DIMM_INIT_5 0x00000028 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_MEM_DIMM_INIT_6 0x00000030 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_MEM_DIMM_INIT_7 0x00000038 /* + * Memory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_0 0x00000040 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_1 0x00000048 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_2 0x00000050 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_3 0x00000058 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_4 0x00000060 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_5 0x00000068 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_6 0x00000070 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_DIR_DIMM_INIT_7 0x00000078 /* + * Directory DIMM mode + * initialization + */ + + + +#define HSPEC_UART_0 0x00000080 /* UART Registers */ + + + +#define HSPEC_UART_1 0x00000088 /* UART Registers */ + + + +#define HSPEC_UART_2 0x00000090 /* UART Registers */ + + + +#define HSPEC_UART_3 0x00000098 /* UART Registers */ + + + +#define HSPEC_UART_4 0x000000A0 /* UART Registers */ + + + +#define HSPEC_UART_5 0x000000A8 /* UART Registers */ + + + +#define HSPEC_UART_6 0x000000B0 /* UART Registers */ + + + +#define HSPEC_UART_7 0x000000B8 /* UART Registers */ + + + +#define HSPEC_LED0 0x000000C0 /* Write 8-bit LED */ + + + +#define HSPEC_LED1 0x000000C8 /* Write 8-bit LED */ + + + +#define HSPEC_LED2 0x000000D0 /* Write 8-bit LED */ + + + +#define HSPEC_LED3 0x000000D8 /* Write 8-bit LED */ + + + +#define HSPEC_SYNERGY0_0 0x04000000 /* Synergy0 Registers */ + + + +#define HSPEC_SYNERGY0_2097151 0x04FFFFF8 /* Synergy0 Registers */ + + + +#define HSPEC_SYNERGY1_0 0x05000000 /* Synergy1 Registers */ + + + +#define HSPEC_SYNERGY1_2097151 0x05FFFFF8 /* Synergy1 Registers */ + + + + + +#ifdef _LANGUAGE_C + +/************************************************************************ + * * + * Writes to these 8 consecutive registers will perform mode * + * register writes to the memory SDRAMs on the DIMMs. There is one * + * initialization register for each of the 8 physical banks of * + * memory. The value in the DIMM_MODE field is written to the * + * designated DIMM after the hardware does a precharge operation and * + * enforces the minimum SDRAM timing.. * + * * + ************************************************************************/ + + + + +typedef union hspec_mem_dimm_init_0_u { + bdrkreg_t hspec_mem_dimm_init_0_regval; + struct { + bdrkreg_t mdi0_reserved : 52; + bdrkreg_t mdi0_dimm_mode : 12; + } hspec_mem_dimm_init_0_fld_s; +} hspec_mem_dimm_init_0_u_t; + + + + +/************************************************************************ + * * + * Writes to these 8 consecutive registers will perform mode * + * register writes to the memory SDRAMs on the DIMMs. There is one * + * initialization register for each of the 8 physical banks of * + * memory. The value in the DIMM_MODE field is written to the * + * designated DIMM after the hardware does a precharge operation and * + * enforces the minimum SDRAM timing.. * + * * + ************************************************************************/ + + + + +typedef union hspec_mem_dimm_init_7_u { + bdrkreg_t hspec_mem_dimm_init_7_regval; + struct { + bdrkreg_t mdi7_reserved : 52; + bdrkreg_t mdi7_dimm_mode : 12; + } hspec_mem_dimm_init_7_fld_s; +} hspec_mem_dimm_init_7_u_t; + + + + +/************************************************************************ + * * + * Writes to these 8 consecutive registers will perform mode * + * register writes to the directory SDRAMs on the DIMMs. There is one * + * initialization register for each of the 8 physical banks of * + * memory. The value in the DIMM_MODE field is written to the * + * designated DIMM after the hardware does a precharge operation and * + * enforces the minimum SDRAM timing. * + * * + ************************************************************************/ + + + + +typedef union hspec_dir_dimm_init_0_u { + bdrkreg_t hspec_dir_dimm_init_0_regval; + struct { + bdrkreg_t ddi0_reserved : 52; + bdrkreg_t ddi0_dimm_mode : 12; + } hspec_dir_dimm_init_0_fld_s; +} hspec_dir_dimm_init_0_u_t; + + + + +/************************************************************************ + * * + * Writes to these 8 consecutive registers will perform mode * + * register writes to the directory SDRAMs on the DIMMs. There is one * + * initialization register for each of the 8 physical banks of * + * memory. The value in the DIMM_MODE field is written to the * + * designated DIMM after the hardware does a precharge operation and * + * enforces the minimum SDRAM timing. * + * * + ************************************************************************/ + + + + +typedef union hspec_dir_dimm_init_7_u { + bdrkreg_t hspec_dir_dimm_init_7_regval; + struct { + bdrkreg_t ddi7_reserved : 52; + bdrkreg_t ddi7_dimm_mode : 12; + } hspec_dir_dimm_init_7_fld_s; +} hspec_dir_dimm_init_7_u_t; + + + + +/************************************************************************ + * * + * These addresses provide read/write access to up to eight UART * + * registers. The datapath to the UART is eight bits wide. * + * * + ************************************************************************/ + + + + +typedef union hspec_uart_0_u { + bdrkreg_t hspec_uart_0_regval; + struct { + bdrkreg_t u0_reserved : 55; + bdrkreg_t u0_unused : 1; + bdrkreg_t u0_data : 8; + } hspec_uart_0_fld_s; +} hspec_uart_0_u_t; + + + + +/************************************************************************ + * * + * These addresses provide read/write access to up to eight UART * + * registers. The datapath to the UART is eight bits wide. * + * * + ************************************************************************/ + + + + +typedef union hspec_uart_7_u { + bdrkreg_t hspec_uart_7_regval; + struct { + bdrkreg_t u7_reserved : 55; + bdrkreg_t u7_unused : 1; + bdrkreg_t u7_data : 8; + } hspec_uart_7_fld_s; +} hspec_uart_7_u_t; + + + + +/************************************************************************ + * * + * This register sets the value on the first 8-bit bank of LEDs. * + * * + ************************************************************************/ + + + + +typedef union hspec_led0_u { + bdrkreg_t hspec_led0_regval; + struct { + bdrkreg_t l_reserved : 55; + bdrkreg_t l_unused : 1; + bdrkreg_t l_data : 8; + } hspec_led0_fld_s; +} hspec_led0_u_t; + + + + +/************************************************************************ + * * + * This register sets the value on the second 8-bit bank of LEDs. * + * * + ************************************************************************/ + + + + +typedef union hspec_led1_u { + bdrkreg_t hspec_led1_regval; + struct { + bdrkreg_t l_reserved : 55; + bdrkreg_t l_unused : 1; + bdrkreg_t l_data : 8; + } hspec_led1_fld_s; +} hspec_led1_u_t; + + + + +/************************************************************************ + * * + * This register sets the value on the third 8-bit bank of LEDs. * + * * + ************************************************************************/ + + + + +typedef union hspec_led2_u { + bdrkreg_t hspec_led2_regval; + struct { + bdrkreg_t l_reserved : 55; + bdrkreg_t l_unused : 1; + bdrkreg_t l_data : 8; + } hspec_led2_fld_s; +} hspec_led2_u_t; + + + + +/************************************************************************ + * * + * This register sets the value on the fourth 8-bit bank of LEDs. * + * * + ************************************************************************/ + + + + +typedef union hspec_led3_u { + bdrkreg_t hspec_led3_regval; + struct { + bdrkreg_t l_reserved : 55; + bdrkreg_t l_unused : 1; + bdrkreg_t l_data : 8; + } hspec_led3_fld_s; +} hspec_led3_u_t; + + + + +/************************************************************************ + * * + * This range allows access to the first Synergy chip. * + * * + ************************************************************************/ + + + + +typedef union hspec_synergy0_0_u { + bdrkreg_t hspec_synergy0_0_regval; + struct { + bdrkreg_t s0_data : 64; + } hspec_synergy0_0_fld_s; +} hspec_synergy0_0_u_t; + + + + +/************************************************************************ + * * + * This range allows access to the first Synergy chip. * + * * + ************************************************************************/ + + + + +typedef union hspec_synergy0_2097151_u { + bdrkreg_t hspec_synergy0_2097151_regval; + struct { + bdrkreg_t s2_data : 64; + } hspec_synergy0_2097151_fld_s; +} hspec_synergy0_2097151_u_t; + + + + +/************************************************************************ + * * + * This range allows access to the second Synergy chip. * + * * + ************************************************************************/ + + + + +typedef union hspec_synergy1_0_u { + bdrkreg_t hspec_synergy1_0_regval; + struct { + bdrkreg_t s0_data : 64; + } hspec_synergy1_0_fld_s; +} hspec_synergy1_0_u_t; + + + + +/************************************************************************ + * * + * This range allows access to the second Synergy chip. * + * * + ************************************************************************/ + + + + +typedef union hspec_synergy1_2097151_u { + bdrkreg_t hspec_synergy1_2097151_regval; + struct { + bdrkreg_t s2_data : 64; + } hspec_synergy1_2097151_fld_s; +} hspec_synergy1_2097151_u_t; + + + + + + +#endif /* _LANGUAGE_C */ + +/************************************************************************ + * * + * The following defines which were not formed into structures are * + * probably indentical to another register, and the name of the * + * register is provided against each of these registers. This * + * information needs to be checked carefully * + * * + * HSPEC_MEM_DIMM_INIT_1 HSPEC_MEM_DIMM_INIT_0 * + * HSPEC_MEM_DIMM_INIT_2 HSPEC_MEM_DIMM_INIT_0 * + * HSPEC_MEM_DIMM_INIT_3 HSPEC_MEM_DIMM_INIT_0 * + * HSPEC_MEM_DIMM_INIT_4 HSPEC_MEM_DIMM_INIT_0 * + * HSPEC_MEM_DIMM_INIT_5 HSPEC_MEM_DIMM_INIT_0 * + * HSPEC_MEM_DIMM_INIT_6 HSPEC_MEM_DIMM_INIT_0 * + * HSPEC_DIR_DIMM_INIT_1 HSPEC_DIR_DIMM_INIT_0 * + * HSPEC_DIR_DIMM_INIT_2 HSPEC_DIR_DIMM_INIT_0 * + * HSPEC_DIR_DIMM_INIT_3 HSPEC_DIR_DIMM_INIT_0 * + * HSPEC_DIR_DIMM_INIT_4 HSPEC_DIR_DIMM_INIT_0 * + * HSPEC_DIR_DIMM_INIT_5 HSPEC_DIR_DIMM_INIT_0 * + * HSPEC_DIR_DIMM_INIT_6 HSPEC_DIR_DIMM_INIT_0 * + * HSPEC_UART_1 HSPEC_UART_0 * + * HSPEC_UART_2 HSPEC_UART_0 * + * HSPEC_UART_3 HSPEC_UART_0 * + * HSPEC_UART_4 HSPEC_UART_0 * + * HSPEC_UART_5 HSPEC_UART_0 * + * HSPEC_UART_6 HSPEC_UART_0 * + * * + ************************************************************************/ + + +/************************************************************************ + * * + * MAKE ALL ADDITIONS AFTER THIS LINE * + * * + ************************************************************************/ + + + + + +#endif /* _ASM_SN_SN1_BDRKHSPECREGS_H */ diff --git a/include/asm-mips64/sn/sn1/bdrkhspecregs_next.h b/include/asm-mips64/sn/sn1/bdrkhspecregs_next.h new file mode 100644 index 000000000..35d6bc025 --- /dev/null +++ b/include/asm-mips64/sn/sn1/bdrkhspecregs_next.h @@ -0,0 +1,35 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_BDRKHSPECREGS_NEXT_H +#define _ASM_SN_SN1_BDRKHSPECREGS_NEXT_H + +/* HSPEC_SYNERGY0_0 (PIMM PSC) shifts and masks */ + +#define HS_PIMM_PSC_SHFT(subnode) (4 * (subnode)) +#define HS_PIMM_PSC_MASK(subnode) (0xf << HS_PIMM_PSC_SHFT(subnode)) + + +/* + * LED register macros + */ + +#ifdef _LANGUAGE_C + +#define CPU_LED_ADDR(_nasid, _slice) \ + REMOTE_HSPEC_ADDR((_nasid), HSPEC_LED0 + ((_slice) << 3)) + +#define SET_CPU_LEDS(_nasid, _slice, _val) \ + (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val))) + +#define SET_MY_LEDS(_v) \ + SET_CPU_LEDS(get_nasid(), get_slice(), (_v)) + +#endif /* _LANGUAGE_C */ +#endif /* _ASM_SN_SN1_BDRKHSPECREGS_NEXT_H */ |