diff options
| -rw-r--r-- | arch/mips/Makefile | 3 | ||||
| -rw-r--r-- | arch/mips/config.in | 5 | ||||
| -rw-r--r-- | arch/mips/defconfig | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-atlas | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-cp7000 | 2 | ||||
| -rw-r--r-- | arch/mips/defconfig-ddb5476 | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-decstation | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-ev64120 | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-ev96100 | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-ip22 | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-malta | 1 | ||||
| -rw-r--r-- | arch/mips/defconfig-rm200 | 1 | ||||
| -rw-r--r-- | arch/mips/kernel/head.S | 54 | ||||
| -rw-r--r-- | arch/mips/kernel/r4k_misc.S | 14 | ||||
| -rw-r--r-- | arch/mips/kernel/r4k_switch.S | 12 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/time.c | 12 | ||||
| -rw-r--r-- | arch/mips/mm/Makefile | 4 | ||||
| -rw-r--r-- | arch/mips/mm/loadmmu.c | 38 | ||||
| -rw-r--r-- | arch/mips/mm/mips32.c | 1088 | ||||
| -rw-r--r-- | include/asm-mips/mips32_cache.h | 288 | ||||
| -rw-r--r-- | include/asm-mips/mipsregs.h | 26 | ||||
| -rw-r--r-- | include/asm-mips/semaphore-helper.h | 11 | ||||
| -rw-r--r-- | include/asm-mips/semaphore.h | 3 |
23 files changed, 1523 insertions, 46 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 314fdff11..6a8cfe187 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -60,6 +60,9 @@ endif ifdef CONFIG_CPU_R4X00 GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap endif +ifdef CONFIG_CPU_MIPS32 +GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap +endif ifdef CONFIG_CPU_R5000 GCCFLAGS += -mcpu=r8000 -mips2 -Wa,--trap endif diff --git a/arch/mips/config.in b/arch/mips/config.in index 49268dd3b..c2367d8c4 100644 --- a/arch/mips/config.in +++ b/arch/mips/config.in @@ -161,7 +161,8 @@ choice 'CPU type' \ RM7000 CONFIG_CPU_RM7000 \ R56x0 CONFIG_CPU_NEVADA \ R8000 CONFIG_CPU_R8000 \ - R10000 CONFIG_CPU_R10000" R4x00 + R10000 CONFIG_CPU_R10000 \ + MIPS32 CONFIG_CPU_MIPS32" R4x00 bool 'Override CPU Options' CONFIG_CPU_ADVANCED @@ -191,7 +192,7 @@ if [ "$CONFIG_DECSTATION" = "y" -o "$CONFIG_DDB5074" = "y" -o "$CONFIG_DDB5476" else bool 'Generate little endian code' CONFIG_CPU_LITTLE_ENDIAN fi -bool ' Kernel floating-point emulation' CONFIG_MIPS_FPU_EMULATOR +bool 'Kernel floating-point emulation' CONFIG_MIPS_FPU_EMULATOR if [ "$CONFIG_PROC_FS" = "y" ]; then define_bool CONFIG_KCORE_ELF y diff --git a/arch/mips/defconfig b/arch/mips/defconfig index bf1c13cc6..6f64e8a9a 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -56,6 +56,7 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-atlas b/arch/mips/defconfig-atlas index fd5ac58d5..4b0740fe9 100644 --- a/arch/mips/defconfig-atlas +++ b/arch/mips/defconfig-atlas @@ -51,6 +51,7 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-cp7000 b/arch/mips/defconfig-cp7000 index 3b35bccd4..d67e287ba 100644 --- a/arch/mips/defconfig-cp7000 +++ b/arch/mips/defconfig-cp7000 @@ -29,6 +29,7 @@ CONFIG_PMC_CP7000=y # CONFIG_SBUS is not set CONFIG_PCI=y CONFIG_SYSCLK_100=y +CONFIG_SWAP_IO_SPACE=y # CONFIG_ISA is not set # CONFIG_EISA is not set # CONFIG_I8259 is not set @@ -53,6 +54,7 @@ CONFIG_CPU_RM7000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-ddb5476 b/arch/mips/defconfig-ddb5476 index 55012c74d..21f540a76 100644 --- a/arch/mips/defconfig-ddb5476 +++ b/arch/mips/defconfig-ddb5476 @@ -52,6 +52,7 @@ CONFIG_CPU_R5432=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-decstation b/arch/mips/defconfig-decstation index 67e1579eb..dece17abb 100644 --- a/arch/mips/defconfig-decstation +++ b/arch/mips/defconfig-decstation @@ -52,6 +52,7 @@ CONFIG_CPU_R3000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set # CONFIG_CPU_HAS_LLSC is not set CONFIG_CPU_HAS_WB=y diff --git a/arch/mips/defconfig-ev64120 b/arch/mips/defconfig-ev64120 index d29fc3edd..38dd7bbfb 100644 --- a/arch/mips/defconfig-ev64120 +++ b/arch/mips/defconfig-ev64120 @@ -58,6 +58,7 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-ev96100 b/arch/mips/defconfig-ev96100 index 5362d2500..262fd226a 100644 --- a/arch/mips/defconfig-ev96100 +++ b/arch/mips/defconfig-ev96100 @@ -54,6 +54,7 @@ CONFIG_CPU_RM7000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set CONFIG_CPU_ADVANCED=y CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-ip22 b/arch/mips/defconfig-ip22 index bf1c13cc6..6f64e8a9a 100644 --- a/arch/mips/defconfig-ip22 +++ b/arch/mips/defconfig-ip22 @@ -56,6 +56,7 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-malta b/arch/mips/defconfig-malta index fbf765903..826c3f871 100644 --- a/arch/mips/defconfig-malta +++ b/arch/mips/defconfig-malta @@ -51,6 +51,7 @@ CONFIG_CPU_R4X00=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/defconfig-rm200 b/arch/mips/defconfig-rm200 index 718e6612a..8fced9009 100644 --- a/arch/mips/defconfig-rm200 +++ b/arch/mips/defconfig-rm200 @@ -55,6 +55,7 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_WB is not set diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index ea8610da3..890a1bf33 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -15,6 +15,14 @@ * Copyright (C) 1999 Silicon Graphics, Inc. * * Head.S contains the MIPS exception handler and startup code. + * + ************************************************************************** + * 9 Nov, 2000. + * Added Cache Error exception handler and SBDDP EJTAG debug exception. + * + * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + ************************************************************************** */ #include <linux/config.h> #include <linux/threads.h> @@ -68,9 +76,9 @@ mtc0 k0, CP0_ENTRYLO0 # load it srl k1, k1, 6 # convert to entrylo1 mtc0 k1, CP0_ENTRYLO1 # load it - b 1f - tlbwr # write random tlb entry -1: + nop # Need 2 cycles between mtc0 + nop # and tlbwr (CP0 hazard). + tlbwr # write random tlb entry nop eret # return from trap END(except_vec0_r4000) @@ -308,12 +316,26 @@ /* Cache Error */ LEAF(except_vec2_generic) - /* Famous last words: unreached */ - mfc0 a1,CP0_ERROREPC - PRINT("Cache error exception: c0_errorepc == %08x\n") -1: - j 1b - nop + .set noat + .set mips0 + /* + * This is a very bad place to be. Our cache error + * detection has triggered. If we have write-back data + * in the cache, we may not be able to recover. As a + * first-order desperate measure, turn off KSEG0 cacheing. + */ + mfc0 k0,CP0_CONFIG + li k1,~CONF_CM_CMASK + and k0,k0,k1 + ori k0,k0,CONF_CM_UNCACHED + mtc0 k0,CP0_CONFIG + /* Give it a few cycles to sink in... */ + nop + nop + nop + + j cache_parity_error + nop END(except_vec2_generic) /* General exception vector R4000 version. */ @@ -338,6 +360,7 @@ * c0_badvaddr because after return from this exception handler the load / * store will be re-executed. */ + .set mips3 handle_vced: mfc0 k0, CP0_BADVADDR li k1, -4 @@ -393,6 +416,19 @@ handle_vcei: nop END(except_vec4) + /* + * SBDDP EJTAG debug exception handler. + * The EJTAG debug exception entry point is 0xbfc00480, which + * normally is in the boot PROM, so the boot PROM must do a + * unconditional jump to this vector. + */ + NESTED(except_vec_ejtag_debug, 0, sp) + PRINT("SDBBP EJTAG debug exception - not handled yet, hang!\n"); +1: j 1b + nop + END(except_vec_ejtag_debug) + + /* * Kernel entry point */ diff --git a/arch/mips/kernel/r4k_misc.S b/arch/mips/kernel/r4k_misc.S index 35493e182..bfa3cb82c 100644 --- a/arch/mips/kernel/r4k_misc.S +++ b/arch/mips/kernel/r4k_misc.S @@ -7,6 +7,13 @@ * Multi-cpu abstraction and reworking: * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) */ +/************************************************************************** + * 14 Nov, 2000. + * Made support for MIPS32 CPUs. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + *************************************************************************/ #include <asm/asm.h> #include <asm/current.h> #include <asm/offset.h> @@ -102,7 +109,6 @@ sw pte, (ptr); .set noreorder - .set mips3 /* * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: @@ -147,7 +153,9 @@ invalid_tlbl: tlbwi 1: nop + .set mips3 eret + .set mips0 #endif nopage_tlbl: @@ -169,7 +177,9 @@ nopage_tlbl: tlbwi 1: nop + .set mips3 eret + .set mips0 #endif nopage_tlbs: @@ -201,7 +211,9 @@ nopage_tlbs: tlbwi 1: nop + .set mips3 eret + .set mips0 #endif nowrite_mod: diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 75244e6c3..e1d10f92d 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -9,6 +9,14 @@ * Copyright (C) 1994, 1995, 1996, by Andreas Busse * Copyright (C) 1999 Silicon Graphics, Inc. */ +/************************************************************************** + * 13 Nov, 2000. + * Made support for MIPS32 CPUs and restoring of fp registers. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + *************************************************************************/ + #include <asm/asm.h> #include <asm/bootinfo.h> #include <asm/cachectl.h> @@ -24,8 +32,6 @@ #include <asm/asmmacro.h> - .set mips3 - /* * task_struct *r4xx0_resume(task_struct *prev, task_struct *next) */ @@ -113,6 +119,7 @@ LEAF(restore_fp) #define FPU_DEFAULT 0x00000000 LEAF(init_fpu) + .set mips3 mfc0 t0, CP0_STATUS li t1, 0x20000000 or t0, t1 @@ -143,3 +150,4 @@ LEAF(init_fpu) dmtc1 t0, $f30 .set reorder END(init_fpu) + diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d5fdc5f6a..ee08dd5ac 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -31,6 +31,7 @@ #include <asm/mipsregs.h> #include <asm/ptrace.h> +#include <asm/div64.h> #include <linux/mc146818rtc.h> #include <linux/timex.h> @@ -274,6 +275,7 @@ void __init time_init(void) /* This is for machines which generate the exact clock. */ #define USECS_PER_JIFFY (1000000/HZ) +#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff) /* Cycle counter value at the previous timer interrupt.. */ @@ -303,6 +305,15 @@ static unsigned long do_fast_gettimeoffset(void) if (tmp && last_jiffies != tmp) { last_jiffies = tmp; +#ifdef CONFIG_CPU_MIPS32 + if (last_jiffies != 0) { + unsigned long r0; + do_div64_32(r0, timerhi, timerlo, tmp); + do_div64_32(quotient, USECS_PER_JIFFY, + USECS_PER_JIFFY_FRAC, r0); + cached_quotient = quotient; + } +#else __asm__(".set\tnoreorder\n\t" ".set\tnoat\n\t" ".set\tmips3\n\t" @@ -325,6 +336,7 @@ static unsigned long do_fast_gettimeoffset(void) "r" (USECS_PER_JIFFY) :"$1"); cached_quotient = quotient; +#endif } /* Get last timer tick in absolute kernel time */ diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index c57b9cfa1..4febbefd2 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -38,6 +38,10 @@ ifdef CONFIG_CPU_NEVADA O_OBJS += r4xx0.o endif +ifdef CONFIG_CPU_MIPS32 +O_OBJS += mips32.o +endif + ifdef CONFIG_SGI_IP22 O_OBJS += umap.o endif diff --git a/arch/mips/mm/loadmmu.c b/arch/mips/mm/loadmmu.c index 17cca62ee..26b287f4c 100644 --- a/arch/mips/mm/loadmmu.c +++ b/arch/mips/mm/loadmmu.c @@ -2,6 +2,8 @@ * loadmmu.c: Setup cpu/cache specific function ptrs at boot time. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. */ #include <linux/config.h> #include <linux/init.h> @@ -42,10 +44,22 @@ extern void ld_mmu_r6000(void); extern void ld_mmu_rm7k(void); extern void ld_mmu_tfp(void); extern void ld_mmu_andes(void); +extern void ld_mmu_mips32(void); void __init loadmmu(void) { - switch (mips_cpu.cputype) { + + if (mips_cpu.options & MIPS_CPU_4KTLB) { +#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_R4300) || \ + defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA) + printk("Loading R4000 MMU routines.\n"); + ld_mmu_r4xx0(); +#endif +#if defined(CONFIG_CPU_MIPS32) + printk("Loading MIPS32 MMU routines.\n"); + ld_mmu_mips32(); +#endif + } else switch(mips_cpu.cputype) { #ifdef CONFIG_CPU_R3000 case CPU_R2000: case CPU_R3000: @@ -56,28 +70,6 @@ void __init loadmmu(void) break; #endif -#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_R4300) || \ - defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA) - case CPU_R4000PC: - case CPU_R4000SC: - case CPU_R4000MC: - case CPU_R4200: - case CPU_R4300: - case CPU_R4400PC: - case CPU_R4400SC: - case CPU_R4400MC: - case CPU_R4600: - case CPU_R4640: - case CPU_R4650: - case CPU_R4700: - case CPU_R5000: - case CPU_R5000A: - case CPU_NEVADA: - printk("Loading R4000 MMU routines.\n"); - ld_mmu_r4xx0(); - break; -#endif - #if defined(CONFIG_CPU_R5432) case CPU_R5432: printk("Loading R5432 MMU routines.\n"); diff --git a/arch/mips/mm/mips32.c b/arch/mips/mm/mips32.c new file mode 100644 index 000000000..407793fdc --- /dev/null +++ b/arch/mips/mm/mips32.c @@ -0,0 +1,1088 @@ +/* + * mips32.c + * + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * MIPS32 CPU variant specific MMU/Cache routines. + * + * This file is the original r4xx0.c file with modification that makes the + * cache and tlb handling more generic. + * + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/mm.h> + +#include <asm/bootinfo.h> +#include <asm/cpu.h> +#include <asm/bcache.h> +#include <asm/io.h> +#include <asm/page.h> +#include <asm/pgtable.h> +#include <asm/system.h> +#include <asm/mmu_context.h> + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +/* Primary cache parameters. */ +static int icache_size, dcache_size; /* Size in bytes */ +static int ic_lsize, dc_lsize; /* LineSize in bytes */ + +/* Secondary cache (if present) parameters. */ +static unsigned int scache_size, sc_lsize; /* Again, in bytes */ + +#include <asm/cacheops.h> +#include <asm/mips32_cache.h> + +#undef DEBUG_CACHE + +/* + * Dummy cache handling routines for machines without boardcaches + */ +static void no_sc_noop(void) {} + +static struct bcache_ops no_sc_ops = { + (void *)no_sc_noop, (void *)no_sc_noop, + (void *)no_sc_noop, (void *)no_sc_noop +}; + +struct bcache_ops *bcops = &no_sc_ops; + + +/* + * Zero an entire page. + */ + +static void mips32_clear_page_dc(unsigned long page) +{ + unsigned long i; + + if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) + { + for (i=page; i<page+PAGE_SIZE; i+=dc_lsize) + { + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "cache\t%2,(%0)\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (i) + :"0" (i), + "I" (Create_Dirty_Excl_D)); + } + } + for (i=page; i<page+PAGE_SIZE; i+=4) + *(unsigned long *)(i) = 0; +} + +static void mips32_clear_page_sc(unsigned long page) +{ + unsigned long i; + + if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) + { + for (i=page; i<page+PAGE_SIZE; i+=sc_lsize) + { + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "cache\t%2,(%0)\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (i) + :"0" (i), + "I" (Create_Dirty_Excl_SD)); + } + } + for (i=page; i<page+PAGE_SIZE; i+=4) + *(unsigned long *)(i) = 0; +} + +static void mips32_copy_page_dc(unsigned long to, unsigned long from) +{ + unsigned long i; + + if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) + { + for (i=to; i<to+PAGE_SIZE; i+=dc_lsize) + { + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "cache\t%2,(%0)\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (i) + :"0" (i), + "I" (Create_Dirty_Excl_D)); + } + } + for (i=0; i<PAGE_SIZE; i+=4) + *(unsigned long *)(to+i) = *(unsigned long *)(from+i); +} + +static void mips32_copy_page_sc(unsigned long to, unsigned long from) +{ + unsigned long i; + + if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) + { + for (i=to; i<to+PAGE_SIZE; i+=sc_lsize) + { + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "cache\t%2,(%0)\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (i) + :"0" (i), + "I" (Create_Dirty_Excl_SD)); + } + } + for (i=0; i<PAGE_SIZE; i+=4) + *(unsigned long *)(to+i) = *(unsigned long *)(from+i); +} + +static inline void mips32_flush_cache_all_sc(void) +{ + unsigned long flags; + + __save_and_cli(flags); + blast_dcache(); blast_icache(); blast_scache(); + __restore_flags(flags); +} + +static inline void mips32_flush_cache_all_pc(void) +{ + unsigned long flags; + + __save_and_cli(flags); + blast_dcache(); blast_icache(); + __restore_flags(flags); +} + +static void +mips32_flush_cache_range_sc(struct mm_struct *mm, + unsigned long start, + unsigned long end) +{ + struct vm_area_struct *vma; + unsigned long flags; + + if(mm->context == 0) + return; + + start &= PAGE_MASK; +#ifdef DEBUG_CACHE + printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); +#endif + vma = find_vma(mm, start); + if(vma) { + if(mm->context != current->mm->context) { + mips32_flush_cache_all_sc(); + } else { + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + + __save_and_cli(flags); + while(start < end) { + pgd = pgd_offset(mm, start); + pmd = pmd_offset(pgd, start); + pte = pte_offset(pmd, start); + + if(pte_val(*pte) & _PAGE_VALID) + blast_scache_page(start); + start += PAGE_SIZE; + } + __restore_flags(flags); + } + } +} + +static void mips32_flush_cache_range_pc(struct mm_struct *mm, + unsigned long start, + unsigned long end) +{ + if(mm->context != 0) { + unsigned long flags; + +#ifdef DEBUG_CACHE + printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); +#endif + __save_and_cli(flags); + blast_dcache(); blast_icache(); + __restore_flags(flags); + } +} + +/* + * On architectures like the Sparc, we could get rid of lines in + * the cache created only by a certain context, but on the MIPS + * (and actually certain Sparc's) we cannot. + */ +static void mips32_flush_cache_mm_sc(struct mm_struct *mm) +{ + if(mm->context != 0) { +#ifdef DEBUG_CACHE + printk("cmm[%d]", (int)mm->context); +#endif + mips32_flush_cache_all_sc(); + } +} + +static void mips32_flush_cache_mm_pc(struct mm_struct *mm) +{ + if(mm->context != 0) { +#ifdef DEBUG_CACHE + printk("cmm[%d]", (int)mm->context); +#endif + mips32_flush_cache_all_pc(); + } +} + + + + + +static void mips32_flush_cache_page_sc(struct vm_area_struct *vma, + unsigned long page) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (mm->context == 0) + return; + +#ifdef DEBUG_CACHE + printk("cpage[%d,%08lx]", (int)mm->context, page); +#endif + __save_and_cli(flags); + page &= PAGE_MASK; + pgdp = pgd_offset(mm, page); + pmdp = pmd_offset(pgdp, page); + ptep = pte_offset(pmdp, page); + + /* + * If the page isn't marked valid, the page cannot possibly be + * in the cache. + */ + if (!(pte_val(*ptep) & _PAGE_VALID)) + goto out; + + /* + * Doing flushes for another ASID than the current one is + * too difficult since R4k caches do a TLB translation + * for every cache flush operation. So we do indexed flushes + * in that case, which doesn't overly flush the cache too much. + */ + if (mm->context != current->active_mm->context) { + /* + * Do indexed flush, too much work to get the (possible) + * tlb refills to work correctly. + */ + page = (KSEG0 + (page & (scache_size - 1))); + blast_dcache_page_indexed(page); + blast_scache_page_indexed(page); + } else + blast_scache_page(page); +out: + __restore_flags(flags); +} + +static void mips32_flush_cache_page_pc(struct vm_area_struct *vma, + unsigned long page) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (mm->context == 0) + return; + +#ifdef DEBUG_CACHE + printk("cpage[%d,%08lx]", (int)mm->context, page); +#endif + __save_and_cli(flags); + page &= PAGE_MASK; + pgdp = pgd_offset(mm, page); + pmdp = pmd_offset(pgdp, page); + ptep = pte_offset(pmdp, page); + + /* + * If the page isn't marked valid, the page cannot possibly be + * in the cache. + */ + if (!(pte_val(*ptep) & _PAGE_VALID)) + goto out; + + /* + * Doing flushes for another ASID than the current one is + * too difficult since Mips32 caches do a TLB translation + * for every cache flush operation. So we do indexed flushes + * in that case, which doesn't overly flush the cache too much. + */ + if (mm == current->active_mm) { + blast_dcache_page(page); + } else { + /* Do indexed flush, too much work to get the (possible) + * tlb refills to work correctly. + */ + page = (KSEG0 + (page & (dcache_size - 1))); + blast_dcache_page_indexed(page); + } +out: + __restore_flags(flags); +} + +/* If the addresses passed to these routines are valid, they are + * either: + * + * 1) In KSEG0, so we can do a direct flush of the page. + * 2) In KSEG2, and since every process can translate those + * addresses all the time in kernel mode we can do a direct + * flush. + * 3) In KSEG1, no flush necessary. + */ +static void mips32_flush_page_to_ram_sc(struct page *page) +{ + blast_scache_page((unsigned long)page_address(page)); +} + +static void mips32_flush_page_to_ram_pc(struct page *page) +{ + blast_dcache_page((unsigned long)page_address(page)); +} + +static void +mips32_flush_icache_page_s(struct vm_area_struct *vma, struct page *page) +{ + /* + * We did an scache flush therefore PI is already clean. + */ +} + +static void +mips32_flush_icache_range(unsigned long start, unsigned long end) +{ + flush_cache_all(); +} + +static void +mips32_flush_icache_page(struct vm_area_struct *vma, struct page *page) +{ + int address; + + if (!(vma->vm_flags & VM_EXEC)) + return; + + address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1)); + blast_icache_page_indexed(address); +} + +/* + * Writeback and invalidate the primary cache dcache before DMA. + */ +static void +mips32_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + unsigned int flags; + + if (size >= dcache_size) { + flush_cache_all(); + } else { + __save_and_cli(flags); + a = addr & ~(dc_lsize - 1); + end = (addr + size) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) break; + a += dc_lsize; + } + __restore_flags(flags); + } + bc_wback_inv(addr, size); +} + +static void +mips32_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (size >= scache_size) { + flush_cache_all(); + return; + } + + a = addr & ~(sc_lsize - 1); + end = (addr + size) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) break; + a += sc_lsize; + } +} + +static void +mips32_dma_cache_inv_pc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + unsigned int flags; + + if (size >= dcache_size) { + flush_cache_all(); + } else { + __save_and_cli(flags); + a = addr & ~(dc_lsize - 1); + end = (addr + size) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) break; + a += dc_lsize; + } + __restore_flags(flags); + } + + bc_inv(addr, size); +} + +static void +mips32_dma_cache_inv_sc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (size >= scache_size) { + flush_cache_all(); + return; + } + + a = addr & ~(sc_lsize - 1); + end = (addr + size) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) break; + a += sc_lsize; + } +} + +static void +mips32_dma_cache_wback(unsigned long addr, unsigned long size) +{ + panic("mips32_dma_cache called - should not happen.\n"); +} + +/* + * While we're protected against bad userland addresses we don't care + * very much about what happens in that case. Usually a segmentation + * fault will dump the process later on anyway ... + */ +static void mips32_flush_cache_sigtramp(unsigned long addr) +{ + unsigned long daddr, iaddr; + + daddr = addr & ~(dc_lsize - 1); + protected_writeback_dcache_line(daddr); + protected_writeback_dcache_line(daddr + dc_lsize); + iaddr = addr & ~(ic_lsize - 1); + protected_flush_icache_line(iaddr); + protected_flush_icache_line(iaddr + ic_lsize); +} + +#undef DEBUG_TLB +#undef DEBUG_TLBUPDATE + +void flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + int entry; + +#ifdef DEBUG_TLB + printk("[tlball]"); +#endif + + __save_and_cli(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = (get_entryhi() & 0xff); + set_entryhi(KSEG0); + set_entrylo0(0); + set_entrylo1(0); + BARRIER; + + entry = get_wired(); + + /* Blast 'em all away. */ + while(entry < mips_cpu.tlbsize) { + /* Make sure all entries differ. */ + set_entryhi(KSEG0+entry*0x2000); + set_index(entry); + BARRIER; + tlb_write_indexed(); + BARRIER; + entry++; + } + BARRIER; + set_entryhi(old_ctx); + __restore_flags(flags); +} + +void flush_tlb_mm(struct mm_struct *mm) +{ + if (mm->context != 0) { + unsigned long flags; + +#ifdef DEBUG_TLB + printk("[tlbmm<%d>]", mm->context); +#endif + __save_and_cli(flags); + get_new_mmu_context(mm, asid_cache); + if (mm == current->active_mm) + set_entryhi(mm->context & 0xff); + __restore_flags(flags); + } +} + +void flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long end) +{ + if(mm->context != 0) { + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), + start, end); +#endif + __save_and_cli(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if(size <= mips_cpu.tlbsize/2) { + int oldpid = (get_entryhi() & 0xff); + int newpid = (mm->context & 0xff); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + while(start < end) { + int idx; + + set_entryhi(start | newpid); + start += (PAGE_SIZE << 1); + BARRIER; + tlb_probe(); + BARRIER; + idx = get_index(); + set_entrylo0(0); + set_entrylo1(0); + if(idx < 0) + continue; + /* Make sure all entries differ. */ + set_entryhi(KSEG0+idx*0x2000); + BARRIER; + tlb_write_indexed(); + BARRIER; + } + set_entryhi(oldpid); + } else { + get_new_mmu_context(mm, asid_cache); + if (mm == current->active_mm) + set_entryhi(mm->context & 0xff); + } + __restore_flags(flags); + } +} + +void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + if (vma->vm_mm->context != 0) { + unsigned long flags; + int oldpid, newpid, idx; + +#ifdef DEBUG_TLB + printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); +#endif + newpid = (vma->vm_mm->context & 0xff); + page &= (PAGE_MASK << 1); + __save_and_cli(flags); + oldpid = (get_entryhi() & 0xff); + set_entryhi(page | newpid); + BARRIER; + tlb_probe(); + BARRIER; + idx = get_index(); + set_entrylo0(0); + set_entrylo1(0); + if(idx < 0) + goto finish; + /* Make sure all entries differ. */ + set_entryhi(KSEG0+idx*0x2000); + BARRIER; + tlb_write_indexed(); + + finish: + BARRIER; + set_entryhi(oldpid); + __restore_flags(flags); + } +} + +/* Load a new root pointer into the TLB. */ +void load_pgd(unsigned long pg_dir) +{ +} + +void pgd_init(unsigned long page) +{ + unsigned long *p = (unsigned long *) page; + int i; + + for(i = 0; i < USER_PTRS_PER_PGD; i+=8) { + p[i + 0] = (unsigned long) invalid_pte_table; + p[i + 1] = (unsigned long) invalid_pte_table; + p[i + 2] = (unsigned long) invalid_pte_table; + p[i + 3] = (unsigned long) invalid_pte_table; + p[i + 4] = (unsigned long) invalid_pte_table; + p[i + 5] = (unsigned long) invalid_pte_table; + p[i + 6] = (unsigned long) invalid_pte_table; + p[i + 7] = (unsigned long) invalid_pte_table; + } +} + +/* + * Updates the TLB with the new pte(s). + */ +void update_mmu_cache(struct vm_area_struct * vma, + unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + pid = get_entryhi() & 0xff; + +#ifdef DEBUG_TLB + if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) { + printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n", + (int) (vma->vm_mm->context & 0xff), pid); + } +#endif + + __save_and_cli(flags); + address &= (PAGE_MASK << 1); + set_entryhi(address | (pid)); + pgdp = pgd_offset(vma->vm_mm, address); + BARRIER; + tlb_probe(); + BARRIER; + pmdp = pmd_offset(pgdp, address); + idx = get_index(); + ptep = pte_offset(pmdp, address); + BARRIER; + set_entrylo0(pte_val(*ptep++) >> 6); + set_entrylo1(pte_val(*ptep) >> 6); + set_entryhi(address | (pid)); + BARRIER; + if(idx < 0) { + tlb_write_random(); + } else { + tlb_write_indexed(); + } + BARRIER; + set_entryhi(pid); + BARRIER; + __restore_flags(flags); +} + +void show_regs(struct pt_regs * regs) +{ + /* Saved main processor registers. */ + printk("$0 : %08lx %08lx %08lx %08lx\n", + 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); + printk("$4 : %08lx %08lx %08lx %08lx\n", + regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); + printk("$8 : %08lx %08lx %08lx %08lx\n", + regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); + printk("$12: %08lx %08lx %08lx %08lx\n", + regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); + printk("$16: %08lx %08lx %08lx %08lx\n", + regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); + printk("$20: %08lx %08lx %08lx %08lx\n", + regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); + printk("$24: %08lx %08lx\n", + regs->regs[24], regs->regs[25]); + printk("$28: %08lx %08lx %08lx %08lx\n", + regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); + + /* Saved cp0 registers. */ + printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\n", + regs->cp0_epc, regs->cp0_status, regs->cp0_cause); +} + +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) +{ + unsigned long flags; + unsigned long wired; + unsigned long old_pagemask; + unsigned long old_ctx; + + __save_and_cli(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = (get_entryhi() & 0xff); + old_pagemask = get_pagemask(); + wired = get_wired(); + set_wired (wired + 1); + set_index (wired); + BARRIER; + set_pagemask (pagemask); + set_entryhi(entryhi); + set_entrylo0(entrylo0); + set_entrylo1(entrylo1); + BARRIER; + tlb_write_indexed(); + BARRIER; + + set_entryhi(old_ctx); + BARRIER; + set_pagemask (old_pagemask); + flush_tlb_all(); + __restore_flags(flags); +} + +/* Detect and size the various caches. */ +static void __init probe_icache(unsigned long config) +{ + unsigned long config1; + unsigned int lsize; + + if (!(config & (1 << 31))) { + /* + * Not a MIPS32 complainant CPU. + * Config 1 register not supported, we assume R4k style. + */ + icache_size = 1 << (12 + ((config >> 9) & 7)); + ic_lsize = 16 << ((config >> 5) & 1); + mips_cpu.icache.linesz = ic_lsize; + + /* + * We cannot infer associativity - assume direct map + * unless probe template indicates otherwise + */ + if(!mips_cpu.icache.ways) mips_cpu.icache.ways = 1; + mips_cpu.icache.sets = + (icache_size / ic_lsize) / mips_cpu.icache.ways; + } else { + config1 = read_mips32_cp0_config1(); + + if ((lsize = ((config1 >> 19) & 7))) + mips_cpu.icache.linesz = 2 << lsize; + else + mips_cpu.icache.linesz = lsize; + mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7); + mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7); + + ic_lsize = mips_cpu.icache.linesz; + icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways * + ic_lsize; + } + printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n", + icache_size >> 10, ic_lsize, mips_cpu.icache.ways); +} + +static void __init probe_dcache(unsigned long config) +{ + unsigned long config1; + unsigned int lsize; + + if (!(config & (1 << 31))) { + /* + * Not a MIPS32 complainant CPU. + * Config 1 register not supported, we assume R4k style. + */ + dcache_size = 1 << (12 + ((config >> 6) & 7)); + dc_lsize = 16 << ((config >> 4) & 1); + mips_cpu.dcache.linesz = dc_lsize; + /* + * We cannot infer associativity - assume direct map + * unless probe template indicates otherwise + */ + if(!mips_cpu.dcache.ways) mips_cpu.dcache.ways = 1; + mips_cpu.dcache.sets = + (dcache_size / dc_lsize) / mips_cpu.dcache.ways; + } else { + config1 = read_mips32_cp0_config1(); + + if ((lsize = ((config1 >> 10) & 7))) + mips_cpu.dcache.linesz = 2 << lsize; + else + mips_cpu.dcache.linesz= lsize; + mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7); + mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7); + + dc_lsize = mips_cpu.dcache.linesz; + dcache_size = + mips_cpu.dcache.sets * mips_cpu.dcache.ways + * dc_lsize; + } + printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n", + dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways); +} + + +/* If you even _breathe_ on this function, look at the gcc output + * and make sure it does not pop things on and off the stack for + * the cache sizing loop that executes in KSEG1 space or else + * you will crash and burn badly. You have been warned. + */ +static int __init probe_scache(unsigned long config) +{ + extern unsigned long stext; + unsigned long flags, addr, begin, end, pow2; + int tmp; + + tmp = ((config >> 17) & 1); + if(tmp) + return 0; + tmp = ((config >> 22) & 3); + switch(tmp) { + case 0: + sc_lsize = 16; + break; + case 1: + sc_lsize = 32; + break; + case 2: + sc_lsize = 64; + break; + case 3: + sc_lsize = 128; + break; + } + + begin = (unsigned long) &stext; + begin &= ~((4 * 1024 * 1024) - 1); + end = begin + (4 * 1024 * 1024); + + /* This is such a bitch, you'd think they would make it + * easy to do this. Away you daemons of stupidity! + */ + __save_and_cli(flags); + + /* Fill each size-multiple cache line with a valid tag. */ + pow2 = (64 * 1024); + for(addr = begin; addr < end; addr = (begin + pow2)) { + unsigned long *p = (unsigned long *) addr; + __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ + pow2 <<= 1; + } + + /* Load first line with zero (therefore invalid) tag. */ + set_taglo(0); + set_taghi(0); + __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ + __asm__ __volatile__("\n\t.set noreorder\n\t" + ".set mips3\n\t" + "cache 8, (%0)\n\t" + ".set mips0\n\t" + ".set reorder\n\t" : : "r" (begin)); + __asm__ __volatile__("\n\t.set noreorder\n\t" + ".set mips3\n\t" + "cache 9, (%0)\n\t" + ".set mips0\n\t" + ".set reorder\n\t" : : "r" (begin)); + __asm__ __volatile__("\n\t.set noreorder\n\t" + ".set mips3\n\t" + "cache 11, (%0)\n\t" + ".set mips0\n\t" + ".set reorder\n\t" : : "r" (begin)); + + /* Now search for the wrap around point. */ + pow2 = (128 * 1024); + tmp = 0; + for(addr = (begin + (128 * 1024)); addr < (end); addr = (begin + pow2)) { + __asm__ __volatile__("\n\t.set noreorder\n\t" + ".set mips3\n\t" + "cache 7, (%0)\n\t" + ".set mips0\n\t" + ".set reorder\n\t" : : "r" (addr)); + __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ + if(!get_taglo()) + break; + pow2 <<= 1; + } + __restore_flags(flags); + addr -= begin; + printk("Secondary cache sized at %dK linesize %d bytes.\n", + (int) (addr >> 10), sc_lsize); + scache_size = addr; + return 1; +} + +static void __init setup_noscache_funcs(void) +{ + _clear_page = (void *)mips32_clear_page_dc; + _copy_page = (void *)mips32_copy_page_dc; + _flush_cache_all = mips32_flush_cache_all_pc; + _flush_cache_mm = mips32_flush_cache_mm_pc; + _flush_cache_range = mips32_flush_cache_range_pc; + _flush_cache_page = mips32_flush_cache_page_pc; + _flush_page_to_ram = mips32_flush_page_to_ram_pc; + + _flush_icache_page = mips32_flush_icache_page; + + _dma_cache_wback_inv = mips32_dma_cache_wback_inv_pc; + _dma_cache_wback = mips32_dma_cache_wback; + _dma_cache_inv = mips32_dma_cache_inv_pc; +} + +static void __init setup_scache_funcs(void) +{ + _flush_cache_all = mips32_flush_cache_all_sc; + _flush_cache_mm = mips32_flush_cache_mm_sc; + _flush_cache_range = mips32_flush_cache_range_sc; + _flush_cache_page = mips32_flush_cache_page_sc; + _flush_page_to_ram = mips32_flush_page_to_ram_sc; + _clear_page = (void *)mips32_clear_page_sc; + _copy_page = (void *)mips32_copy_page_sc; + + _flush_icache_page = mips32_flush_icache_page_s; + + _dma_cache_wback_inv = mips32_dma_cache_wback_inv_sc; + _dma_cache_wback = mips32_dma_cache_wback; + _dma_cache_inv = mips32_dma_cache_inv_sc; +} + +typedef int (*probe_func_t)(unsigned long); + +static inline void __init setup_scache(unsigned int config) +{ + probe_func_t probe_scache_kseg1; + int sc_present = 0; + + /* Maybe the cpu knows about a l2 cache? */ + probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache)); + sc_present = probe_scache_kseg1(config); + + if (sc_present) { + mips_cpu.scache.linesz = sc_lsize; + /* + * We cannot infer associativity - assume direct map + * unless probe template indicates otherwise + */ + if(!mips_cpu.scache.ways) mips_cpu.scache.ways = 1; + mips_cpu.scache.sets = + (scache_size / sc_lsize) / mips_cpu.scache.ways; + + setup_scache_funcs(); + return; + } + + setup_noscache_funcs(); +} + +static void __init probe_tlb(unsigned long config) +{ + unsigned long config1; + + if (!(config & (1 << 31))) { + /* + * Not a MIPS32 complainant CPU. + * Config 1 register not supported, we assume R4k style. + */ + mips_cpu.tlbsize = 48; + } else { + config1 = read_mips32_cp0_config1(); + if (!((config >> 7) & 3)) + panic("No MMU present"); + else + mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1; + } + + printk("Number of TLB entries %d.\n", mips_cpu.tlbsize); +} + +void __init ld_mmu_mips32(void) +{ + unsigned long config = read_32bit_cp0_register(CP0_CONFIG); + + printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); + +#ifdef CONFIG_MIPS_UNCACHED + set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); +#else + set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); +#endif + + probe_icache(config); + probe_dcache(config); + setup_scache(config); + probe_tlb(config); + + _flush_cache_sigtramp = mips32_flush_cache_sigtramp; + _flush_icache_range = mips32_flush_icache_range; /* Ouch */ + + flush_cache_all(); + write_32bit_cp0_register(CP0_WIRED, 0); + + /* + * You should never change this register: + * - The entire mm handling assumes the c0_pagemask register to + * be set for 4kb pages. + */ + write_32bit_cp0_register(CP0_PAGEMASK, PM_4K); + flush_tlb_all(); +} diff --git a/include/asm-mips/mips32_cache.h b/include/asm-mips/mips32_cache.h new file mode 100644 index 000000000..2de18bd7c --- /dev/null +++ b/include/asm-mips/mips32_cache.h @@ -0,0 +1,288 @@ +/* + * mips32_cache.h + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Inline assembly cache operations. + * + * This file is the original r4cache.c file with modification that makes the + * cache handling more generic. + * + * FIXME: Handle split L2 caches. + * + */ +#ifndef _MIPS_R4KCACHE_H +#define _MIPS_R4KCACHE_H + +#include <asm/asm.h> +#include <asm/cacheops.h> + +extern inline void flush_icache_line_indexed(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Invalidate_I)); +} + +extern inline void flush_dcache_line_indexed(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Writeback_Inv_D)); +} + +extern inline void flush_scache_line_indexed(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Writeback_Inv_SD)); +} + +extern inline void flush_icache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Invalidate_I)); +} + +extern inline void flush_dcache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Writeback_Inv_D)); +} + +extern inline void invalidate_dcache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Invalidate_D)); +} + +extern inline void invalidate_scache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Invalidate_SD)); +} + +extern inline void flush_scache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Writeback_Inv_SD)); +} + +/* + * The next two are for badland addresses like signal trampolines. + */ +extern inline void protected_flush_icache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n" + "1:\tcache %1,(%0)\n" + "2:\t.set mips0\n\t" + ".set reorder\n\t" + ".section\t__ex_table,\"a\"\n\t" + STR(PTR)"\t1b,2b\n\t" + ".previous" + : + : "r" (addr), + "i" (Hit_Invalidate_I)); +} + +extern inline void protected_writeback_dcache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n" + "1:\tcache %1,(%0)\n" + "2:\t.set mips0\n\t" + ".set reorder\n\t" + ".section\t__ex_table,\"a\"\n\t" + STR(PTR)"\t1b,2b\n\t" + ".previous" + : + : "r" (addr), + "i" (Hit_Writeback_D)); +} + +#define cache_unroll(base,op) \ + __asm__ __volatile__(" \ + .set noreorder; \ + .set mips3; \ + cache %1, (%0); \ + .set mips0; \ + .set reorder" \ + : \ + : "r" (base), \ + "i" (op)); + + +extern inline void blast_dcache(void) +{ + unsigned long start = KSEG0; + unsigned long end = (start + dcache_size); + + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_D); + start += dc_lsize; + } +} + +extern inline void blast_dcache_page(unsigned long page) +{ + unsigned long start = page; + unsigned long end = (start + PAGE_SIZE); + + while(start < end) { + cache_unroll(start,Hit_Writeback_Inv_D); + start += dc_lsize; + } +} + +extern inline void blast_dcache_page_indexed(unsigned long page) +{ + unsigned long start = page; + unsigned long end = (start + PAGE_SIZE); + + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_D); + start += dc_lsize; + } +} + +extern inline void blast_icache(void) +{ + unsigned long start = KSEG0; + unsigned long end = (start + icache_size); + + while(start < end) { + cache_unroll(start,Index_Invalidate_I); + start += ic_lsize; + } +} + +extern inline void blast_icache_page(unsigned long page) +{ + unsigned long start = page; + unsigned long end = (start + PAGE_SIZE); + + while(start < end) { + cache_unroll(start,Hit_Invalidate_I); + start += ic_lsize; + } +} + +extern inline void blast_icache_page_indexed(unsigned long page) +{ + unsigned long start = page; + unsigned long end = (start + PAGE_SIZE); + + while(start < end) { + cache_unroll(start,Index_Invalidate_I); + start += ic_lsize; + } +} + +extern inline void blast_scache(void) +{ + unsigned long start = KSEG0; + unsigned long end = KSEG0 + scache_size; + + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_SD); + start += sc_lsize; + } +} + +extern inline void blast_scache_page(unsigned long page) +{ + unsigned long start = page; + unsigned long end = page + PAGE_SIZE; + + while(start < end) { + cache_unroll(start,Hit_Writeback_Inv_SD); + start += sc_lsize; + } +} + +extern inline void blast_scache_page_indexed(unsigned long page) +{ + unsigned long start = page; + unsigned long end = page + PAGE_SIZE; + + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_SD); + start += sc_lsize; + } +} + +#endif /* !(_MIPS_R4KCACHE_H) */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index a3c3f64ba..cbedf0ae5 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -6,9 +6,11 @@ * Copyright (C) 1994, 1995, 1996, 1997, 2000 by Ralf Baechle * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. */ -#ifndef __ASM_MIPS_MIPSREGS_H -#define __ASM_MIPS_MIPSREGS_H +#ifndef _ASM_MIPSREGS_H +#define _ASM_MIPSREGS_H #include <linux/linkage.h> @@ -187,6 +189,24 @@ "dmtc0\t%0,"STR(register)"\n\t" \ ".set\tmips0" \ : : "r" (value)) + +#ifdef CONFIG_CPU_MIPS32 +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. + */ +#define read_mips32_cp0_config1() \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ +:"=r" (__res)); \ + __res;}) +#endif + /* * R4x00 interrupt enable / cause bits */ @@ -421,4 +441,4 @@ extern asmlinkage unsigned int read_perf_cntl(unsigned int counter); extern asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val); #endif -#endif /* __ASM_MIPS_MIPSREGS_H */ +#endif /* _ASM_MIPSREGS_H */ diff --git a/include/asm-mips/semaphore-helper.h b/include/asm-mips/semaphore-helper.h index c183834e7..c281a4f3e 100644 --- a/include/asm-mips/semaphore-helper.h +++ b/include/asm-mips/semaphore-helper.h @@ -1,10 +1,11 @@ /* * SMP- and interrupt-safe semaphores helper functions. * - * (C) Copyright 1996 Linus Torvalds - * (C) Copyright 1999 Andrea Arcangeli - * (C) Copyright 1999 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. + * Copyright (C) 1996 Linus Torvalds + * Copyright (C) 1999 Andrea Arcangeli + * Copyright (C) 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2000 MIPS Technologies, Inc. */ #ifndef _ASM_SEMAPHORE_HELPER_H #define _ASM_SEMAPHORE_HELPER_H @@ -19,7 +20,7 @@ static inline void wake_one_more(struct semaphore * sem) atomic_inc(&sem->waking); } -#if !defined(CONFIG_CPU_HAS_LLSC) +#if !defined(CONFIG_CPU_HAS_LLSC) || defined(CONFIG_CPU_MIPS32) /* * It doesn't make sense, IMHO, to endlessly turn interrupts off and on again. diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h index 19fb03efc..ebd77bd39 100644 --- a/include/asm-mips/semaphore.h +++ b/include/asm-mips/semaphore.h @@ -8,6 +8,7 @@ * (C) Copyright 1996 Linus Torvalds * (C) Copyright 1998, 1999, 2000 Ralf Baechle * (C) Copyright 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. */ #ifndef _ASM_SEMAPHORE_H #define _ASM_SEMAPHORE_H @@ -104,7 +105,7 @@ static inline int down_interruptible(struct semaphore * sem) return ret; } -#if !defined(CONFIG_CPU_HAS_LLSC) +#if !defined(CONFIG_CPU_HAS_LLSC) || defined(CONFIG_CPU_MIPS32) static inline int down_trylock(struct semaphore * sem) { |