3 files changed, 37 insertions, 32 deletions

diff --git a/arch/mips/boot/compressed/cache.S b/arch/mips/boot/compressed/cache.S
index 3e6a3d57d..7cc97b53e 100644
--- a/arch/mips/boot/compressed/cache.S
+++ b/arch/mips/boot/compressed/cache.S
@@ -18,10 +18,7 @@
 #include <asm/asm.h>
 #include <asm/cachectl.h>
 #include <asm/mipsregs.h>
-#include <asm/uaccess.h>
-
-#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS5)
+#include <asm/segment.h>
 
 /*
  * Some bits in the config register
@@ -29,8 +26,6 @@
 #define CONFIG_IB       (1<<5)
 #define CONFIG_DB       (1<<4)
 
-#define CACHEBLOCKS 32
-
  /*
   * Flush instruction/data caches
   *
@@ -45,14 +40,16 @@
 		.set	noreorder
 		LEAF(cacheflush)
 		andi	t1,a2,DCACHE
+
 		beqz	t1,do_icache
-		li	t0,KSEG0		# delay slot
+		 li	t0,KSEG0
 
 		/*
 		 * Writeback data cache, even lines
 		 */
-		li	t1,CACHEBLOCKS-1
-1:		cache	Index_Writeback_Inv_D,0(t0)
+		li	t1,CACHELINES-1
+1:
+		cache	Index_Writeback_Inv_D,0(t0)
 		cache	Index_Writeback_Inv_D,32(t0)
 		cache	Index_Writeback_Inv_D,64(t0)
 		cache	Index_Writeback_Inv_D,96(t0)
@@ -69,8 +66,9 @@
 		cache	Index_Writeback_Inv_D,448(t0)
 		cache	Index_Writeback_Inv_D,480(t0)
 		addiu	t0,512
+
 		bnez	t1,1b
-		subu	t1,1
+		 subu	t1,1
 
 		/*
 		 * Writeback data cache, odd lines
@@ -79,8 +77,9 @@
 		mfc0	t1,CP0_CONFIG
 		andi	t1,CONFIG_IB
 		bnez	t1,do_icache
-		li	t1,CACHEBLOCKS-1
-1:		cache	Index_Writeback_Inv_D,16(t0)
+		 li	t1,CACHELINES-1
+1:
+		cache	Index_Writeback_Inv_D,16(t0)
 		cache	Index_Writeback_Inv_D,48(t0)
 		cache	Index_Writeback_Inv_D,80(t0)
 		cache	Index_Writeback_Inv_D,112(t0)
@@ -97,18 +96,21 @@
 		cache	Index_Writeback_Inv_D,464(t0)
 		cache	Index_Writeback_Inv_D,496(t0)
 		addiu	t0,512
+
 		bnez	t1,1b
-		subu	t1,1
+		 subu	t1,1
 
-do_icache:	andi	t1,a2,ICACHE
+do_icache:
+		andi	t1,a2,ICACHE
 		beqz	t1,done
+		 lui	t0,0x8000
 
 		/*
 		 * Flush instruction cache, even lines
 		 */
-		lui	t0,0x8000
-		li	t1,CACHEBLOCKS-1
-1: 		cache	Index_Invalidate_I,0(t0)	
+		li	t1,CACHELINES-1
+1:
+		cache	Index_Invalidate_I,0(t0)	
 		cache	Index_Invalidate_I,32(t0)
 		cache	Index_Invalidate_I,64(t0)
 		cache	Index_Invalidate_I,96(t0)
@@ -125,8 +127,9 @@ do_icache:	andi	t1,a2,ICACHE
 		cache	Index_Invalidate_I,448(t0)
 		cache	Index_Invalidate_I,480(t0)
 		addiu	t0,512
+
 		bnez	t1,1b
-		subu	t1,1
+		 subu	t1,1
 
 		/*
 		 * Flush instruction cache, even lines
@@ -135,8 +138,10 @@ do_icache:	andi	t1,a2,ICACHE
 		mfc0	t1,CP0_CONFIG
 		andi	t1,CONFIG_DB
 		bnez	t1,done
-		li	t1,CACHEBLOCKS-1
-1:		cache	Index_Invalidate_I,16(t0)
+		 li	t1,CACHELINES-1
+
+1:
+		cache	Index_Invalidate_I,16(t0)
 		cache	Index_Invalidate_I,48(t0)
 		cache	Index_Invalidate_I,80(t0)
 		cache	Index_Invalidate_I,112(t0)
@@ -153,13 +158,11 @@ do_icache:	andi	t1,a2,ICACHE
 		cache	Index_Invalidate_I,464(t0)
 		cache	Index_Invalidate_I,496(t0)
 		addiu	t0,512
+
 		bnez	t1,1b
-		subu	t1,1
+		 subu	t1,1
 
-done:		j	ra
-		nop
+done:
+		j	ra
+		 nop
 		END(sys_cacheflush)
-
-#else
-#error "No R3000 cacheflushing implemented yet!"
-#endif
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 0ca599563..dad90855e 100644
--- a/arch/mips/boot/compressed/head.S
+++ b/arch/mips/boot/compressed/head.S
@@ -28,16 +28,18 @@
 		la	t0,_edata
 		la	t1,_end
 		sw	zero,(t0)
-1:		addiu	t0,4
+1:
+		addiu	t0,4
+
 		bnel	t0,t1,1b
-		sw	zero,(t0)
+		 sw	zero,(t0)
 		END(kernel_entry)
 
 		/*
 		 * Do the decompression, and jump to the new kernel..
 		 */
 		jal	C_LABEL(decompress_kernel)
-		nop
+		 nop
 
 		/*
 		 * Flush caches
@@ -49,4 +51,4 @@
 		 */
 		la	t0,KSEG0
 		jr	t0
-		nop
+		 nop
diff --git a/arch/mips/boot/compressed/misc.c b/arch/mips/boot/compressed/misc.c
index 625a75cd0..1e3bb5f82 100644
--- a/arch/mips/boot/compressed/misc.c
+++ b/arch/mips/boot/compressed/misc.c
@@ -12,7 +12,7 @@
 #include "gzip.h"
 #include "lzw.h"
 
-#include <asm/uaccess.h>
+#include <asm/segment.h>
 
 /*
  * These are set up by the setup-routine at boot-time: