summaryrefslogtreecommitdiffstats
path: root/arch/mips/mm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/andes.c11
-rw-r--r--arch/mips/mm/init.c59
-rw-r--r--arch/mips/mm/loadmmu.c4
-rw-r--r--arch/mips/mm/r2300.c8
-rw-r--r--arch/mips/mm/r4xx0.c10
-rw-r--r--arch/mips/mm/r6000.c9
-rw-r--r--arch/mips/mm/tfp.c10
7 files changed, 53 insertions, 58 deletions
diff --git a/arch/mips/mm/andes.c b/arch/mips/mm/andes.c
index 4ef02dfa0..529c12465 100644
--- a/arch/mips/mm/andes.c
+++ b/arch/mips/mm/andes.c
@@ -1,7 +1,9 @@
-/* $Id: andes.c,v 1.1.1.1 1997/06/01 03:16:38 ralf Exp $
+/*
* andes.c: MMU and cache operations for the R10000 (ANDES).
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ *
+ * $Id: andes.c,v 1.3 1998/03/21 08:03:53 ralf Exp $
*/
#include <linux/kernel.h>
@@ -85,6 +87,11 @@ static void andes_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1
/* XXX */
}
+static void andes_user_mode(struct pt_regs *regs)
+{
+ return regs->cp0_status & ST0_KSU == KSU_USER;
+}
+
void ld_mmu_andes(void)
{
flush_cache_all = andes_flush_cache_all;
@@ -101,6 +108,8 @@ void ld_mmu_andes(void)
add_wired_entry = andes_add_wired_entry;
+ user_mode = andes_user_mode;
+
load_pgd = andes_load_pgd;
pgd_init = andes_pgd_init;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 9cb47cefa..3e309e438 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -1,8 +1,11 @@
/*
- * arch/mips/mm/init.c
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
*
- * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
- * Ported to MIPS by Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ *
+ * $Id: init.c,v 1.4 1998/03/21 08:01:45 ralf Exp $
*/
#include <linux/config.h>
#include <linux/signal.h>
@@ -113,58 +116,12 @@ pte_t * __bad_pagetable(void)
return (pte_t *)page;
}
-static inline void
-__zeropage(unsigned long page)
-{
- unsigned long dummy1, dummy2;
-
-#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4)
- /*
- * Use 64bit code even for Linux/MIPS 32bit on R4000
- */
- __asm__ __volatile__(
- ".set\tnoreorder\n"
- ".set\tnoat\n\t"
- ".set\tmips3\n"
- "1:\tsd\t$0,(%0)\n\t"
- "subu\t%1,1\n\t"
- "bnez\t%1,1b\n\t"
- "addiu\t%0,8\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n"
- ".set\treorder"
- :"=r" (dummy1),
- "=r" (dummy2)
- :"0" (page),
- "1" (PAGE_SIZE/8));
-#else /* (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) */
- __asm__ __volatile__(
- ".set\tnoreorder\n"
- "1:\tsw\t$0,(%0)\n\t"
- "subu\t%1,1\n\t"
- "bnez\t%1,1b\n\t"
- "addiu\t%0,4\n\t"
- ".set\treorder"
- :"=r" (dummy1),
- "=r" (dummy2)
- :"0" (page),
- "1" (PAGE_SIZE/4));
-#endif
-}
-
-static inline void
-zeropage(unsigned long page)
-{
- flush_page_to_ram(page);
- __zeropage(page);
-}
-
pte_t __bad_page(void)
{
extern char empty_bad_page[PAGE_SIZE];
unsigned long page = (unsigned long)empty_bad_page;
- zeropage(page);
+ clear_page(page);
return pte_mkdirty(mk_pte(page, PAGE_SHARED));
}
@@ -221,7 +178,7 @@ void mem_init(unsigned long start_mem, unsigned long end_mem)
high_memory = (void *)end_mem;
/* clear the zero-page */
- memset(empty_zero_page, 0, PAGE_SIZE);
+ clear_page(empty_zero_page);
/* mark usable pages in the mem_map[] */
start_mem = PAGE_ALIGN(start_mem);
diff --git a/arch/mips/mm/loadmmu.c b/arch/mips/mm/loadmmu.c
index 2f9312ab9..9f4624ba6 100644
--- a/arch/mips/mm/loadmmu.c
+++ b/arch/mips/mm/loadmmu.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*
- * $Id: loadmmu.c,v 1.5 1998/01/13 04:39:35 ralf Exp $
+ * $Id: loadmmu.c,v 1.5 1998/03/03 16:57:25 ralf Exp $
*/
#include <linux/kernel.h>
@@ -51,6 +51,8 @@ void (*show_regs)(struct pt_regs *);
void (*add_wired_entry)(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask);
+int (*user_mode)(struct pt_regs *);
+
asmlinkage void (*resume)(void *tsk);
extern void ld_mmu_r2300(void);
diff --git a/arch/mips/mm/r2300.c b/arch/mips/mm/r2300.c
index 98dbaaf5c..822cb1a1a 100644
--- a/arch/mips/mm/r2300.c
+++ b/arch/mips/mm/r2300.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*
- * $Id: r2300.c,v 1.2 1997/07/01 09:00:49 ralf Exp $
+ * $Id: r2300.c,v 1.3 1997/07/29 22:54:51 tsbogend Exp $
*/
#include <linux/kernel.h>
@@ -253,6 +253,11 @@ static void r2300_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1
*/
}
+static int r2300_user_mode(struct pt_regs *regs)
+{
+ return !(regs->cp0_status & 0x4);
+}
+
void ld_mmu_r2300(void)
{
clear_page = r2300_clear_page;
@@ -278,5 +283,6 @@ void ld_mmu_r2300(void)
add_wired_entry = r2300_add_wired_entry;
+ user_mode = r2300_user_mode;
flush_tlb_all();
}
diff --git a/arch/mips/mm/r4xx0.c b/arch/mips/mm/r4xx0.c
index e86f3e4eb..2cd1c9236 100644
--- a/arch/mips/mm/r4xx0.c
+++ b/arch/mips/mm/r4xx0.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*
- * $Id: r4xx0.c,v 1.12 1998/03/03 16:57:26 ralf Exp $
+ * $Id: r4xx0.c,v 1.13 1998/03/18 17:18:13 ralf Exp $
*
* To do:
*
@@ -2631,6 +2631,12 @@ static inline void setup_scache(unsigned int config)
setup_noscache_funcs();
}
+static int r4k_user_mode(struct pt_regs *regs)
+{
+ return (regs->cp0_status & ST0_KSU) == KSU_USER;
+}
+
+
void ld_mmu_r4xx0(void)
{
unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
@@ -2669,6 +2675,8 @@ void ld_mmu_r4xx0(void)
add_wired_entry = r4k_add_wired_entry;
+ user_mode = r4k_user_mode;
+
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
diff --git a/arch/mips/mm/r6000.c b/arch/mips/mm/r6000.c
index 4f792fcd6..d656c897c 100644
--- a/arch/mips/mm/r6000.c
+++ b/arch/mips/mm/r6000.c
@@ -1,4 +1,4 @@
-/* $Id: r6000.c,v 1.1.1.1 1997/06/01 03:16:38 ralf Exp $
+/* $Id: r6000.c,v 1.2 1997/07/29 22:54:52 tsbogend Exp $
* r6000.c: MMU and cache routines for the R6000 processors.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
@@ -162,6 +162,11 @@ static void r6000_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1
/* XXX */
}
+static int r6000_user_mode(struct pt_regs *regs)
+{
+ return !(regs->cp0_status & 0x4);
+}
+
void ld_mmu_r6000(void)
{
flush_cache_all = r6000_flush_cache_all;
@@ -184,6 +189,8 @@ void ld_mmu_r6000(void)
add_wired_entry = r6000_add_wired_entry;
+ user_mode = r6000_user_mode;
+
flush_cache_all();
flush_tlb_all();
}
diff --git a/arch/mips/mm/tfp.c b/arch/mips/mm/tfp.c
index 04db52b98..931661f82 100644
--- a/arch/mips/mm/tfp.c
+++ b/arch/mips/mm/tfp.c
@@ -1,4 +1,4 @@
-/* $Id: tfp.c,v 1.1.1.1 1997/06/01 03:16:38 ralf Exp $
+/* $Id: tfp.c,v 1.2 1997/07/29 22:54:53 tsbogend Exp $
* tfp.c: MMU and cache routines specific to the r8000 (TFP).
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
@@ -85,6 +85,11 @@ static void tfp_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
/* XXX */
}
+static int tfp_user_mode(struct pt_regs *regs)
+{
+ return regs->cp0_status & ST0_KSU == KSU_USER;
+}
+
void ld_mmu_tfp(void)
{
flush_cache_all = tfp_flush_cache_all;
@@ -101,10 +106,11 @@ void ld_mmu_tfp(void)
add_wired_entry = tfp_add_wired_entry;
+ user_mode = tfp_user_mode;
+
load_pgd = tfp_load_pgd;
pgd_init = tfp_pgd_init;
flush_cache_all();
flush_tlb_all();
}
-
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-20 08:41:20 +0000