diff options
Diffstat (limited to 'arch/mips')
37 files changed, 708 insertions, 2025 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index bf6c7fd36..23a56b044 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -209,12 +209,11 @@ LOADADDR += 0x80100000 endif # -# PMC Sierra Momentum / Ocelot / CP7000 board -# Whatever you want to call it today. +# Momentum Ocelot board # -ifdef CONFIG_PMC_CP7000 -LIBS += arch/mips/pmc/cp7000/cp7000.o -SUBDIRS += arch/mips/pmc/cp7000 +ifdef CONFIG_MOMENCO_OCELOT +LIBS += arch/mips/gt64120/common/gt64120.o arch/mips/gt64120/momenco_ocelot/momenco_ocelot.o +SUBDIRS += arch/mips/gt64120/common arch/mips/gt64120/momenco_ocelot LOADADDR += 0x80100000 endif diff --git a/arch/mips/config.in b/arch/mips/config.in index 1afcb98d2..6e0267008 100644 --- a/arch/mips/config.in +++ b/arch/mips/config.in @@ -19,7 +19,6 @@ if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then bool 'Support for BAGET MIPS series (EXPERIMENTAL)' CONFIG_BAGET_MIPS bool 'Support for DECstations (EXPERIMENTAL)' CONFIG_DECSTATION bool 'Support for NEC DDB Vrc-5074 (EXPERIMENTAL)' CONFIG_DDB5074 - bool 'Support for NEC DDB Vrc-5476 (EXPERIMENTAL)' CONFIG_DDB5476 bool 'Support for Galileo EV96100 Evaluation board' CONFIG_MIPS_EV96100 bool 'Support for Galileo EV64120 Evaluation board' CONFIG_MIPS_EV64120 if [ "$CONFIG_MIPS_EV64120" = "y" ]; then @@ -33,8 +32,9 @@ if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then bool 'Support for MIPS Malta board' CONFIG_MIPS_MALTA fi bool 'Support for Mips Magnum 4000' CONFIG_MIPS_MAGNUM_4000 +bool 'Support for Momentum Ocelot board' CONFIG_MOMENCO_OCELOT +bool 'Support for NEC DDB Vrc-5476' CONFIG_DDB5476 bool 'Support for Olivetti M700-10' CONFIG_OLIVETTI_M700 -bool 'Support for PMC Sierra CP7000' CONFIG_PMC_CP7000 bool 'Support for SGI IP22' CONFIG_SGI_IP22 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI @@ -99,7 +99,7 @@ if [ "$CONFIG_MIPS_MALTA" = "y" ]; then define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y define_bool CONFIG_SWAP_IO_SPACE y fi -if [ "$CONFIG_PMC_CP7000" = "y" ]; then +if [ "$CONFIG_MOMENCO_OCELOT" = "y" ]; then define_bool CONFIG_PCI y define_bool CONFIG_SYSCLK_100 y define_bool CONFIG_SWAP_IO_SPACE y diff --git a/arch/mips/defconfig b/arch/mips/defconfig index 924a848c7..f7adf3a26 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set CONFIG_SGI_IP22=y # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-atlas b/arch/mips/defconfig-atlas index 73d74c356..7f60e5747 100644 --- a/arch/mips/defconfig-atlas +++ b/arch/mips/defconfig-atlas @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set CONFIG_MIPS_ATLAS=y # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-ddb5476 b/arch/mips/defconfig-ddb5476 index 3c54bca48..c44d68875 100644 --- a/arch/mips/defconfig-ddb5476 +++ b/arch/mips/defconfig-ddb5476 @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -CONFIG_DDB5476=y # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +CONFIG_DDB5476=y # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-decstation b/arch/mips/defconfig-decstation index d633b27a2..d14fdbe42 100644 --- a/arch/mips/defconfig-decstation +++ b/arch/mips/defconfig-decstation @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set CONFIG_DECSTATION=y # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-ev64120 b/arch/mips/defconfig-ev64120 index 1e7b21a5f..35ef59c55 100644 --- a/arch/mips/defconfig-ev64120 +++ b/arch/mips/defconfig-ev64120 @@ -16,7 +16,6 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set CONFIG_MIPS_EV64120=y # CONFIG_EVB_PCI1 is not set @@ -26,8 +25,9 @@ CONFIG_SYSCLK_100=y # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-ev96100 b/arch/mips/defconfig-ev96100 index 48b2bcd61..1c864281f 100644 --- a/arch/mips/defconfig-ev96100 +++ b/arch/mips/defconfig-ev96100 @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set CONFIG_MIPS_EV96100=y # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-ip22 b/arch/mips/defconfig-ip22 index 924a848c7..f7adf3a26 100644 --- a/arch/mips/defconfig-ip22 +++ b/arch/mips/defconfig-ip22 @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set CONFIG_SGI_IP22=y # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-malta b/arch/mips/defconfig-malta index 66125a703..4c626babf 100644 --- a/arch/mips/defconfig-malta +++ b/arch/mips/defconfig-malta @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set CONFIG_MIPS_MALTA=y # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set diff --git a/arch/mips/defconfig-cp7000 b/arch/mips/defconfig-ocelot index 60cb12ad0..03c52c202 100644 --- a/arch/mips/defconfig-cp7000 +++ b/arch/mips/defconfig-ocelot @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +CONFIG_MOMENCO_OCELOT=y +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -CONFIG_PMC_CP7000=y # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MCA is not set @@ -38,9 +38,7 @@ CONFIG_SWAP_IO_SPACE=y # # Loadable module support # -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -# CONFIG_KMOD is not set +# CONFIG_MODULES is not set # # CPU selection @@ -64,7 +62,7 @@ CONFIG_CPU_HAS_LLSC=y # General setup # # CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_MIPS_FPU_EMULATOR=y +# CONFIG_MIPS_FPU_EMULATOR is not set CONFIG_KCORE_ELF=y CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_IRIX is not set @@ -126,7 +124,7 @@ CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y -# CONFIG_IP_PNP_BOOTP is not set +CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set @@ -217,7 +215,7 @@ CONFIG_NET_PCI=y # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_APRICOT is not set # CONFIG_CS89x0 is not set -CONFIG_TULIP=y +# CONFIG_TULIP is not set # CONFIG_DE4X5 is not set # CONFIG_DGRS is not set # CONFIG_DM9102 is not set @@ -249,13 +247,7 @@ CONFIG_EEPRO100=y # CONFIG_SK98LIN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -# CONFIG_PPP_DEFLATE is not set -# CONFIG_PPP_BSDCOMP is not set -# CONFIG_PPPOE is not set +# CONFIG_PPP is not set # CONFIG_SLIP is not set # @@ -292,12 +284,7 @@ CONFIG_PPP_ASYNC=y # CONFIG_VT is not set CONFIG_SERIAL=y CONFIG_SERIAL_CONSOLE=y -CONFIG_SERIAL_EXTENDED=y -# CONFIG_SERIAL_MANY_PORTS is not set -# CONFIG_SERIAL_SHARE_IRQ is not set -# CONFIG_SERIAL_DETECT_IRQ is not set -# CONFIG_SERIAL_MULTIPORT is not set -# CONFIG_HUB6 is not set +# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_UNIX98_PTYS is not set @@ -365,7 +352,7 @@ CONFIG_SERIAL_EXTENDED=y # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set # CONFIG_CRAMFS is not set -CONFIG_RAMFS=y +# CONFIG_RAMFS is not set # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_MINIX_FS is not set @@ -395,7 +382,7 @@ CONFIG_EXT2_FS=y CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set +CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set CONFIG_SUNRPC=y CONFIG_LOCKD=y @@ -437,7 +424,6 @@ CONFIG_MSDOS_PARTITION=y # Kernel hacking # CONFIG_CROSSCOMPILE=y -# CONFIG_MIPS_FPE_MODULE is not set # CONFIG_REMOTE_DEBUG is not set # CONFIG_MAGIC_SYSRQ is not set # CONFIG_MIPS_UNCACHED is not set diff --git a/arch/mips/defconfig-rm200 b/arch/mips/defconfig-rm200 index a04708b93..282b59758 100644 --- a/arch/mips/defconfig-rm200 +++ b/arch/mips/defconfig-rm200 @@ -16,14 +16,14 @@ CONFIG_EXPERIMENTAL=y # CONFIG_BAGET_MIPS is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_DDB5476 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set # CONFIG_OLIVETTI_M700 is not set -# CONFIG_PMC_CP7000 is not set # CONFIG_SGI_IP22 is not set CONFIG_SNI_RM200_PCI=y # CONFIG_MCA is not set diff --git a/arch/mips/galileo-boards/ev64120/reset.c b/arch/mips/galileo-boards/ev64120/reset.c index b145a3446..8f801c8f3 100644 --- a/arch/mips/galileo-boards/ev64120/reset.c +++ b/arch/mips/galileo-boards/ev64120/reset.c @@ -1,6 +1,9 @@ /* - * EVB96100 -Galileo reset subroutines + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * + * Copyright (C) 1997 Ralf Baechle */ #include <linux/sched.h> #include <linux/mm.h> @@ -10,18 +13,6 @@ #include <asm/reboot.h> #include <asm/system.h> -/******************************************************************** - *galileo_machine_restart - - * - *Restart the machine - * - * - *Inputs : - *command - not used - * - *Outpus : - * - *********************************************************************/ void galileo_machine_restart(char *command) { *(volatile char *) 0xbc000000 = 0x0f; @@ -38,35 +29,16 @@ void galileo_machine_restart(char *command) __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); } -/******************************************************************** - *galileo_machine_halt - - * - *Halt the machine - * - * - *Inputs : - * - *Outpus : - * - *********************************************************************/ void galileo_machine_halt(void) { - printk("\n** You can safely turn off the power\n"); - while (1) { - } + printk(KERN_NOTICE "You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); + } -/******************************************************************** - *galileo_machine_power_off - - * - *Halt the machine - * - * - *Inputs : - * - *Outpus : - * - *********************************************************************/ void galileo_machine_power_off(void) { galileo_machine_halt(); diff --git a/arch/mips/pmc/cp7000/.cvsignore b/arch/mips/gt64120/common/.cvsignore index 857dd22e9..857dd22e9 100644 --- a/arch/mips/pmc/cp7000/.cvsignore +++ b/arch/mips/gt64120/common/.cvsignore diff --git a/arch/mips/pmc/cp7000/Makefile b/arch/mips/gt64120/common/Makefile index a7ad746d5..ccf50a55b 100644 --- a/arch/mips/pmc/cp7000/Makefile +++ b/arch/mips/gt64120/common/Makefile @@ -1,5 +1,5 @@ # -# Makefile for PMC Sierra's Ocelot CP7000 board. +# Makefile for common code of gt64120-based boards. # # Note! Dependencies are done automagically by 'make dep', which also # removes any old dependencies. DON'T put your own dependencies here @@ -11,9 +11,8 @@ .S.o: $(CC) $(CFLAGS) -c $< -o $*.o -O_TARGET := cp7000.o +O_TARGET:= gt64120.o -obj-y := i2o.o int-handler.o irq.o irq-handler.o pci.o promcon.o reset.o \ - serialGT.o setup.o +obj-y := gt_irq.o irq.o pci.o include $(TOPDIR)/Rules.make diff --git a/arch/mips/pmc/cp7000/irq-handler.c b/arch/mips/gt64120/common/gt_irq.c index d2da8376e..afd91e4ba 100644 --- a/arch/mips/pmc/cp7000/irq-handler.c +++ b/arch/mips/gt64120/common/gt_irq.c @@ -1,9 +1,19 @@ -/* - * Galileo Technology chip interrupt handler +/*********************************************************************** + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * arch/mips/gt64120/common/gt_irq.c + * Interrupt routines for gt64120. Currently it only handles timer irq. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. * - * Modified by RidgeRun, Inc. - * + *********************************************************************** */ + #include <linux/module.h> #include <linux/interrupt.h> #include <linux/kernel.h> @@ -12,9 +22,7 @@ #include <linux/sched.h> #include <linux/kernel_stat.h> #include <asm/io.h> -#include <asm/gt64120.h> -#include <asm/pmc/ev64120.h> -#include <asm/pmc/ev64120int.h> +#include <asm/gt64120/gt64120.h> /* * These are interrupt handlers for the GT on-chip interrupts. They @@ -96,13 +104,11 @@ int disable_galileo_irq(int int_cause, int bit_num) * Interrupt handler for interrupts coming from the Galileo chip. * It could be timer interrupt, built in ethernet ports etc... */ -static void galileo_irq(int irq, void *dev_id, struct pt_regs *regs) +static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs) { unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; int handled; - unsigned int count; - static int counter = 0; GT_READ(GT_INTRCAUSE_OFS, &irq_src); GT_READ(GT_INTRMASK_OFS, &irq_src_mask); @@ -192,7 +198,7 @@ static void galileo_irq(int irq, void *dev_id, struct pt_regs *regs) * that is passed in as *irq (=irq0 in ../kernel/time.c). * We will do our own timer interrupt handling. */ -void galileo_time_init(struct irqaction *irq) +void gt64120_time_init(struct irqaction *irq) { extern irq_desc_t irq_desc[NR_IRQS]; static struct irqaction timer; @@ -207,7 +213,7 @@ void galileo_time_init(struct irqaction *irq) * in the boot process to use the "request_irq()" call, we'll hard-code * the values to the correct interrupt line. */ - timer.handler = &galileo_irq; + timer.handler = >64120_irq; timer.flags = SA_SHIRQ | SA_INTERRUPT; timer.name = "timer"; timer.dev_id = NULL; @@ -215,6 +221,8 @@ void galileo_time_init(struct irqaction *irq) timer.mask = 0; irq_desc[TIMER].action = &timer; + enable_irq(TIMER); + /* Enable timer ints */ GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); /* clear Cause register first */ @@ -227,11 +235,11 @@ void galileo_time_init(struct irqaction *irq) GT_WRITE(GT_HINTRMASK_OFS, 0x0); } -void galileo_irq_init(void) +void gt64120_irq_init(void) { +#if CURRENTLY_UNUSED int i, j; -#if CURRENTLY_UNUSED /* Reset irq handlers pointers to NULL */ for (i = 0; i < MAX_CAUSE_REGS; i++) { for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) { diff --git a/arch/mips/pmc/cp7000/irq.c b/arch/mips/gt64120/common/irq.c index 173bdfbfb..c0fdcc44a 100644 --- a/arch/mips/pmc/cp7000/irq.c +++ b/arch/mips/gt64120/common/irq.c @@ -1,12 +1,15 @@ /* - * BRIEF MODULE DESCRIPTION - * Code to handle irqs on GT64120A boards - * Derived from mips/orion and Cort <cort@fsmlabs.com> + * arch/mips/gt64120/common/irq.c + * Top-level irq code. This is really common among all MIPS boards. + * Should be "upgraded" to arch/mips/kernel/irq.c * * Copyright (C) 2000 RidgeRun, Inc. * Author: RidgeRun, Inc. * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -59,113 +62,6 @@ #endif -asmlinkage void do_IRQ(int irq, struct pt_regs *regs); - -#define MAX_AGENTS_PER_INT 21 /* Random number */ -unsigned char pci_int_irq[MAX_AGENTS_PER_INT]; -static int max_interrupts = 0; - -/* Duplicate interrupt handlers. */ -/* - * pci_int(A/B/C/D) - - * - * Calls all the handlers connected to PCI interrupt A/B/C/D - * - * Inputs : - * - * Outpus : - * - */ -asmlinkage void pci_intA(struct pt_regs *regs) -{ - unsigned int count = 0; - DBG(KERN_INFO "pci_intA, max_interrupts %d\n", max_interrupts); - for (count = 0; count < max_interrupts; count++) { - do_IRQ(pci_int_irq[count], regs); - } -} - -asmlinkage void pci_intB(struct pt_regs *regs) -{ - unsigned int count = 0; - DBG(KERN_INFO "pci_intB, max_interrupts %d\n", max_interrupts); - for (count = 0; count < max_interrupts; count++) { - do_IRQ(pci_int_irq[count], regs); - } -} - -asmlinkage void pci_intC(struct pt_regs *regs) -{ - unsigned int count = 0; - DBG(KERN_INFO "pci_intC, max_interrupts %d\n", max_interrupts); - for (count = 0; count < max_interrupts; count++) { - do_IRQ(pci_int_irq[count], regs); - } -} -asmlinkage void pci_intD(struct pt_regs *regs) -{ - unsigned int count = 0; - DBG(KERN_INFO "pci_intD, max_interrupts %d\n", max_interrupts); - for (count = 0; count < max_interrupts; count++) { - do_IRQ(pci_int_irq[count], regs); - } -} - - -/* Function for careful CP0 interrupt mask access */ -static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) -{ - unsigned long status = read_32bit_cp0_register(CP0_STATUS); - DBG(KERN_INFO "modify_cp0_intmask clr %x, set %x\n", clr_mask, - set_mask); - DBG(KERN_INFO "modify_cp0_intmask status %x\n", status); - status &= ~((clr_mask & 0xFF) << 8); - status |= (set_mask & 0xFF) << 8; - DBG(KERN_INFO "modify_cp0_intmask status %x\n", status); - write_32bit_cp0_register(CP0_STATUS, status); -} - -static inline void mask_irq(unsigned int irq_nr) -{ - modify_cp0_intmask(irq_nr, 0); -} - -static inline void unmask_irq(unsigned int irq_nr) -{ - modify_cp0_intmask(0, irq_nr); -} - -void disable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - DBG(KERN_INFO "disable_irq, irq %d\n", irq_nr); - save_and_cli(flags); - if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 XXX - mask_irq(9 << 2); - } else { - mask_irq(1 << irq_nr); - } - restore_flags(flags); -} - -void enable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - DBG(KERN_INFO "enable_irq, irq %d\n", irq_nr); - save_and_cli(flags); - if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 XXX - DBG(KERN_INFO __FUNCTION__ " pci interrupt %d\n", irq_nr); - unmask_irq(9 << 2); - } else { - DBG(KERN_INFO __FUNCTION__ " interrupt set mask %d\n", - 1 << irq_nr); - unmask_irq(1 << irq_nr); - } - restore_flags(flags); -} - /* * Generic no controller code */ @@ -179,12 +75,10 @@ static unsigned int no_irq_startup(unsigned int irq) return 0; } -#if 0 static void no_irq_ack(unsigned int irq) { printk(KERN_CRIT "Unexpected IRQ trap at vector %u\n", irq); } -#endif struct hw_interrupt_type no_irq_type = { typename: "none", @@ -192,11 +86,12 @@ struct hw_interrupt_type no_irq_type = { shutdown: no_irq_enable_disable, enable: no_irq_enable_disable, disable: no_irq_enable_disable, + // ack: no_irq_ack, + // [jsun] cannot use it yet. gt64120 does not have its own handler ack: NULL, end: no_irq_enable_disable, }; -// ack: no_irq_ack, re-enable later -- SKJ /* @@ -242,22 +137,9 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) { struct irqaction *action; int cpu; - -#ifdef IRQ_DEBUG - if (irq != TIMER) - DBG(KERN_INFO __FUNCTION__ " irq = %d\n", irq); - if (irq != TIMER) - DBG(KERN_INFO "cause register = %x\n", - read_32bit_cp0_register(CP0_CAUSE)); - if (irq != TIMER) - DBG(KERN_INFO "status register = %x\n", - read_32bit_cp0_register(CP0_STATUS)); -#endif - cpu = smp_processor_id(); irq_enter(cpu, irq); kstat.irqs[cpu][irq]++; - if (irq_desc[irq].handler->ack) { irq_desc[irq].handler->ack(irq); } @@ -302,9 +184,6 @@ int request_irq(unsigned int irq, { struct irqaction *old, **p, *action; unsigned long flags; - - DBG(KERN_INFO "rr:dev %s irq %d handler %x\n", devname, irq, - handler); if (irq >= NR_IRQS) return -EINVAL; @@ -338,12 +217,6 @@ int request_irq(unsigned int irq, *p = action; restore_flags(flags); - if (irq >= 8) { - DBG(KERN_INFO "request_irq, max_interrupts %d\n", - max_interrupts); - // NOTE: Add error-handling if > max - pci_int_irq[max_interrupts++] = irq; - } enable_irq(irq); return 0; @@ -374,25 +247,6 @@ void free_irq(unsigned int irq, void *dev_id) break; } } - - /* - Remove PCI interrupts from the pci_int_irq list. Make sure - that some handler was removed before decrementing max_interrupts. - */ - if ((irq >= 8) && (removed)) { - for (count = 0; count < max_interrupts; count++) { - if (pci_int_irq[count] == irq) { - for (tmp = count; tmp < max_interrupts; - tmp++) { - pci_int_irq[tmp] = - pci_int_irq[tmp + 1]; - } - } - } - max_interrupts--; - DBG(KERN_INFO "free_irq, max_interrupts %d\n", - max_interrupts); - } } unsigned long probe_irq_on(void) @@ -407,55 +261,6 @@ int probe_irq_off(unsigned long irqs) return 0; } -/* - * galileo_irq_setup - - * - * Initializes CPU interrupts - * - * - * Inputs : - * - * Outpus : - * - */ -void galileo_irq_setup(void) -{ - extern asmlinkage void galileo_handle_int(void); - extern void galileo_irq_init(void); - - DBG(KERN_INFO "rr: galileo_irq_setup entry\n"); - - galileo_irq_init(); - - /* - * Clear all of the interrupts while we change the able around a bit. - */ - set_cp0_status(ST0_IM, 0); - set_cp0_status(ST0_BEV, 1); /* int-handler is not on bootstrap */ - - /* Sets the exception_handler array. */ - set_except_vector(0, galileo_handle_int); - - cli(); - - /* - * Enable timer. Other interrupts will be enabled as they are - * registered. - */ - set_cp0_status(ST0_IM, IE_IRQ4); - - -#ifdef CONFIG_REMOTE_DEBUG - { - extern int DEBUG_CHANNEL; - serial_init(DEBUG_CHANNEL); - serial_set(DEBUG_CHANNEL, 115200); - set_debug_traps(); - breakpoint(); /* you may move this line to whereever you want :-) */ - } -#endif -} - void __init init_IRQ(void) { int i; @@ -471,7 +276,7 @@ void __init init_IRQ(void) irq_desc[i].lock = SPIN_LOCK_UNLOCKED; } - galileo_irq_setup(); + irq_setup(); } /* diff --git a/arch/mips/pmc/cp7000/pci.c b/arch/mips/gt64120/common/pci.c index b5d2f1d65..d6b647e11 100644 --- a/arch/mips/pmc/cp7000/pci.c +++ b/arch/mips/gt64120/common/pci.c @@ -12,6 +12,9 @@ * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -40,8 +43,7 @@ #include <linux/version.h> #include <asm/pci.h> #include <asm/io.h> -#include <asm/pmc/ev64120.h> -#include <asm/gt64120.h> +#include <asm/gt64120/gt64120.h> #include <linux/init.h> @@ -66,8 +68,6 @@ static void __init scan_and_initialize_pci(void); static u32 __init scan_pci_bus(struct pci_device *pci_devices); static void __init allocate_pci_space(struct pci_device *pci_devices); -static void __init galileo_pcibios_fixup_bus(struct pci_bus *bus); - /* * The functions that actually read and write to the controller. * @@ -801,7 +801,6 @@ static void galileo_pcibios_set_master(struct pci_dev *dev) int pcibios_enable_resources(struct pci_dev *dev) { u16 cmd, old_cmd; - u16 tmp; u8 tmp1; int idx; struct resource *r; @@ -917,49 +916,13 @@ struct pci_ops galileo_pci_ops = { galileo_pcibios_write_config_dword }; -/* - * galileo_pcibios_fixup_bus - - * - * After detecting all agents over the PCI , this function is called - * in order to give an interrupt number for each PCI device starting - * from IRQ 20. It does also enables master for each device. - * - * Inputs : - * mem_start , mem_end are not relevant in MIPS architecture. - * - * Outpus : - * return always mem_start - */ -static void __init galileo_pcibios_fixup_bus(struct pci_bus *bus) -{ - unsigned int Current_IRQ = 20; - struct pci_bus *current_bus = bus; - struct pci_dev *devices; - struct list_head *devices_link; - - list_for_each(devices_link, &(current_bus->devices)) { - devices = pci_dev_b(devices_link); - if (devices != NULL) { - devices->irq = Current_IRQ++; - - /* Assign an interrupt number for the device */ - galileo_pcibios_write_config_byte(devices, - PCI_INTERRUPT_LINE, - Current_IRQ); - galileo_pcibios_set_master(devices); - - } - } -} - struct pci_fixup pcibios_fixups[] = { -// { PCI_FIXUP_HEADER, 0x4620, 0x11ab, galileo_pcibios_fixup }, {0} }; void __init pcibios_fixup_bus(struct pci_bus *c) { - galileo_pcibios_fixup_bus(c); + gt64120_board_pcibios_fixup_bus(c); } /* @@ -1163,12 +1126,15 @@ void __init pcibios_init(void) pci_scan_bus(0, &galileo_pci_ops, NULL); } +/* + * for parsing "pci=" kernel boot arguments. + */ char *pcibios_setup(char *str) { - printk(KERN_INFO "rr: pcibios_setup\n"); - /* Nothing to do for now. */ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ - return str; + return str; } #endif /* CONFIG_PCI */ diff --git a/arch/mips/gt64120/momenco_ocelot/.cvsignore b/arch/mips/gt64120/momenco_ocelot/.cvsignore new file mode 100644 index 000000000..857dd22e9 --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/.cvsignore @@ -0,0 +1,2 @@ +.depend +.*.flags diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile new file mode 100644 index 000000000..ff7ee4a21 --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/Makefile @@ -0,0 +1,20 @@ +# +# Makefile for Momentum's Ocelot board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +.S.s: + $(CPP) $(CFLAGS) $< -o $*.s +.S.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +O_TARGET:= momenco_ocelot.o + +obj-y += int-handler.o irq.o pci.o prom.o reset.o setup.o + +obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o + +include $(TOPDIR)/Rules.make diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c new file mode 100644 index 000000000..68dfb17e0 --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/dbg_io.c @@ -0,0 +1,124 @@ +#include <linux/config.h> + +#if defined(CONFIG_REMOTE_DEBUG) + +/* --- CONFIG --- */ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +/* --- END OF CONFIG --- */ + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* ----------------------------------------------------- */ + +/* === CONFIG === */ + +/* [jsun] we use the second serial port for kdb */ +#define BASE 0xbd000020 +#define MAX_BAUD 115200 + +/* === END OF CONFIG === */ + +#define REG_OFFSET 4 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) + +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + +static int remoteDebugInitialized = 0; + +uint8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_38400, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +int putDebugChar(uint8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_9600, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} + +#endif diff --git a/arch/mips/pmc/cp7000/int-handler.S b/arch/mips/gt64120/momenco_ocelot/int-handler.S index a075fb52c..df0525833 100644 --- a/arch/mips/pmc/cp7000/int-handler.S +++ b/arch/mips/gt64120/momenco_ocelot/int-handler.S @@ -1,3 +1,14 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * First-level interrupt dispatcher for ocelot board. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ #include <linux/config.h> #include <asm/asm.h> #include <asm/mipsregs.h> @@ -6,12 +17,12 @@ #include <asm/stackframe.h> /* - * galileo_handle_int - + * first level interrupt dispatcher for ocelot board - * We check for the timer first, then check PCI ints A and D. * Then check for serial IRQ and fall through. */ .align 5 - NESTED(galileo_handle_int, PT_SIZE, sp) + NESTED(ocelot_handle_int, PT_SIZE, sp) SAVE_ALL CLI .set at @@ -20,79 +31,59 @@ and t0, t2 -#if 0 - andi t1, t0, STATUSF_IP4 /* int2 hardware line (timer) */ - .set noreorder - bnez t1, ll_galileo_irq andi t1, t0, STATUSF_IP2 /* int0 hardware line */ - bnez t1, ll_pci_intA + bnez t1, ll_pri_enet_irq andi t1, t0, STATUSF_IP3 /* int1 hardware line */ - bnez t1, ll_pci_intB + bnez t1, ll_sec_enet_irq andi t1, t0, STATUSF_IP4 /* int2 hardware line */ - bnez t1, ll_pci_intC + bnez t1, ll_uart1_irq andi t1, t0, STATUSF_IP5 /* int3 hardware line */ - bnez t1, ll_pci_intD -#endif + bnez t1, ll_cpci_irq andi t1, t0, STATUSF_IP6 /* int4 hardware line */ bnez t1, ll_galileo_irq -#if 0 - andi t1, t0, STATUSF_IP7 /* count / compare int */ - bnez t1, ll_compare_irq -#endif + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_cputimer_irq .set reorder /* wrong alarm or masked ... */ j spurious_interrupt nop - END(galileo_handle_int) + END(ocelot_handle_int) .align 5 -ll_galileo_irq: - li a0, 4 +ll_pri_enet_irq: + li a0, 2 move a1, sp jal do_IRQ j ret_from_irq - .align 5 -ll_compare_irq: - PRINT("ll_compare_irq\n") - li a0, 7 +ll_sec_enet_irq: + li a0, 3 move a1, sp jal do_IRQ j ret_from_irq - .align 5 -ll_pci_intA: - PRINT("ll_pci_intA\n") - move a0, sp - jal pci_intA - j ret_from_irq - - .align 5 -ll_pci_intB: - PRINT("ll_pci_intB\n") - move a0, sp - jal pci_intB +ll_uart1_irq: + li a0, 4 + move a1, sp + jal do_IRQ j ret_from_irq - - .align 5 -ll_pci_intC: - PRINT("ll_pci_intC\n") - move a0, sp - jal pci_intC + +ll_cpci_irq: + li a0, 5 + move a1, sp + jal do_IRQ j ret_from_irq - .align 5 -ll_pci_intD: - PRINT("ll_pci_intD\n") - move a0,sp - jal pci_intD +ll_galileo_irq: + li a0, 6 + move a1, sp + jal do_IRQ j ret_from_irq - .align 5 -ll_serial_irq: - PRINT("ll_serial_irq\n") - li a0,6 - move a1,sp +ll_cputimer_irq: + li a0, 7 + move a1, sp jal do_IRQ j ret_from_irq + diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c new file mode 100644 index 000000000..8d832aadb --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/irq.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel_stat.h> +#include <linux/module.h> +#include <linux/signal.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/malloc.h> +#include <linux/random.h> +#include <linux/irq.h> +#include <asm/bitops.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/system.h> + + +#undef IRQ_DEBUG + +#ifdef IRQ_DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + + +/* Function for careful CP0 interrupt mask access */ +static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) +{ + unsigned long status = read_32bit_cp0_register(CP0_STATUS); + DBG(KERN_INFO "modify_cp0_intmask clr %x, set %x\n", clr_mask, + set_mask); + DBG(KERN_INFO "modify_cp0_intmask status %x\n", status); + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + DBG(KERN_INFO "modify_cp0_intmask status %x\n", status); + write_32bit_cp0_register(CP0_STATUS, status); +} + +static inline void mask_irq(unsigned int irq_nr) +{ + modify_cp0_intmask(irq_nr, 0); +} + +static inline void unmask_irq(unsigned int irq_nr) +{ + modify_cp0_intmask(0, irq_nr); +} + +void disable_irq(unsigned int irq_nr) +{ + unsigned long flags; + + DBG(KERN_INFO "disable_irq, irq %d\n", irq_nr); + save_and_cli(flags); + /* we don't support higher interrupts, nor cascaded interrupts */ + if (irq_nr >= 8) + panic("irq_nr is greater than 8"); + + mask_irq(1 << irq_nr); + restore_flags(flags); +} + +void enable_irq(unsigned int irq_nr) +{ + unsigned long flags; + + save_and_cli(flags); + + if ( irq_nr >= 8 ) + panic("irq_nr is greater than 8"); + + unmask_irq( 1 << irq_nr ); + restore_flags(flags); +} + +/* + * Ocelot irq setup - + * + * Initializes CPU interrupts + * + * + * Inputs : + * + * Outpus : + * + */ +void momenco_ocelot_irq_setup(void) +{ + extern asmlinkage void ocelot_handle_int(void); + extern void gt64120_irq_init(void); + + DBG(KERN_INFO "rr: momenco_ocelot_irq_setup entry\n"); + + gt64120_irq_init(); + + /* + * Clear all of the interrupts while we change the able around a bit. + */ + set_cp0_status(ST0_IM, 0); + set_cp0_status(ST0_BEV, 1); /* int-handler is not on bootstrap */ + + /* Sets the first-level interrupt dispatcher. */ + set_except_vector(0, ocelot_handle_int); + + cli(); + + /* + * Enable timer. Other interrupts will be enabled as they are + * registered. + */ + // set_cp0_status(ST0_IM, IE_IRQ4); + + +#ifdef CONFIG_REMOTE_DEBUG + { + /* + extern int DEBUG_CHANNEL; + serial_init(DEBUG_CHANNEL); + serial_set(DEBUG_CHANNEL, 115200); + */ + printk("start kgdb ...\n"); + set_debug_traps(); + breakpoint(); /* you may move this line to whereever you want :-) */ + } +#endif +} diff --git a/arch/mips/gt64120/momenco_ocelot/pci.c b/arch/mips/gt64120/momenco_ocelot/pci.c new file mode 100644 index 000000000..0c1d0a7b0 --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/pci.c @@ -0,0 +1,69 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/gt64120/momenco_ocelot/pci.c + * Board-specific PCI routines for gt64120 controller. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/version.h> +#include <linux/init.h> +#include <asm/pci.h> + + +void __init gt64120_board_pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_bus *current_bus = bus; + struct pci_dev *devices; + struct list_head *devices_link; + u16 cmd; + + list_for_each(devices_link, &(current_bus->devices)) { + + devices = pci_dev_b(devices_link); + if (devices == NULL) + continue; + + if (PCI_SLOT(devices->devfn) == 1) { + /* + * Slot 1 is primary ether port, i82559 + * we double-check against that assumption + / + if ((devices->vendor != 0x8086) || + (devices->device != 0x1209) ) { + panic("gt64120_board_pcibios_fixup_bus: found " + "unexpected PCI device in slot 1."); + } + devices->irq = 2; /* irq_nr is 2 for INT0 */ + } else if (PCI_SLOT(devices->devfn) == 2) { + /* + * Slot 2 is secondary ether port, i21143 + * we double-check against that assumption + */ + if ((devices->vendor != 0x1011) || + (devices->device != 0x19) ) { + panic("galileo_pcibios_fixup_bus: " + "found unexpected PCI device in slot 2."); + } + devices->irq = 3; /* irq_nr is 3 for INT1 */ + } else { + /* We don't have assign interrupts for other devices. */ + devices->irq = 0; /* irq_nr is 3 for INT1 */ + } + + /* Assign an interrupt number for the device */ + bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, devices->irq); + + /* enable master */ + bus->ops->read_word(devices, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + bus->ops->write_word(devices, PCI_COMMAND, cmd); + } +} diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c new file mode 100644 index 000000000..6dfadf1fe --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/prom.c @@ -0,0 +1,49 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/bootmem.h> + +#include <asm/addrspace.h> +#include <asm/bootinfo.h> + + +char arcs_cmdline[COMMAND_LINE_SIZE]; + +/* [jsun@junsun.net] PMON passes arguments in C main() style */ +void __init prom_init(int argc, const char **arg) +{ + int i; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_MOMENCO; + mips_machtype = MACH_MOMENCO_OCELOT; + + /* 128MB - we should detect this through ocelot board status register */ + add_memory_region(0, 128 << 20, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ +} diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c new file mode 100644 index 000000000..0f4c7fee6 --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/reset.c @@ -0,0 +1,48 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 1997, 2001 Ralf Baechle + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + */ +#include <linux/sched.h> +#include <linux/mm.h> +#include <asm/io.h> +#include <asm/pgtable.h> +#include <asm/processor.h> +#include <asm/reboot.h> +#include <asm/system.h> + +void momenco_ocelot_restart(char *command) +{ + *(volatile char *) 0xbc000000 = 0x0f; + + /* + * Ouch, we're still alive ... This time we take the silver bullet ... + * ... and find that we leave the hardware in a state in which the + * kernel in the flush locks up somewhen during of after the PCI + * detection stuff. + */ + set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL)); + set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_32bit_cp0_register(CP0_WIRED, 0); + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +} + +void momenco_ocelot_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void momenco_ocelot_power_off(void) +{ + momenco_ocelot_halt(); +} diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c new file mode 100644 index 000000000..0ffc8c317 --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/setup.c @@ -0,0 +1,95 @@ +/* + * setup.c + * + * BRIEF MODULE DESCRIPTION + * Galileo Evaluation Boards - board dependent boot routines + * + * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/mm.h> +#include <linux/swap.h> +#include <linux/ioport.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/pci.h> +#include <linux/timex.h> +#include <asm/bootinfo.h> +#include <asm/page.h> +#include <asm/bootinfo.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/pci.h> +#include <asm/processor.h> +#include <asm/ptrace.h> +#include <asm/reboot.h> +#include <asm/mc146818rtc.h> +#include <linux/version.h> +#include <linux/bootmem.h> +#include <linux/blk.h> +#include <asm/gt64120/gt64120.h> + +extern struct rtc_ops no_rtc_ops; +struct rtc_ops *rtc_ops; + +/* These functions are used for rebooting or halting the machine*/ +extern void momenco_ocelot_restart(char *command); +extern void momenco_ocelot_halt(void); +extern void momenco_ocelot_power_off(void); + +char arcs_cmdline[COMMAND_LINE_SIZE]= { ""/*console=ttyS0,9600"*/ }; + +void (*board_time_init) (struct irqaction * irq); + +extern void gt64120_time_init(void); +extern void momenco_ocelot_irq_setup(void); + +void momenco_ocelot_setup(void) +{ + unsigned int i, j; + + irq_setup = momenco_ocelot_irq_setup; + board_time_init = gt64120_time_init; + + mips_io_port_base = KSEG1; + + _machine_restart = momenco_ocelot_restart; + _machine_halt = momenco_ocelot_halt; + _machine_power_off = momenco_ocelot_power_off; + + /* + * initrd_start = (ulong)ocelot_initrd_start; + * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; + * initrd_below_start_ok = 1; + */ + rtc_ops = &no_rtc_ops; +} diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 615031946..6725f1864 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -38,12 +38,12 @@ int get_cpuinfo(char *buffer) const char *mach_baget_names[] = GROUP_BAGET_NAMES; const char *mach_cosine_names[] = GROUP_COSINE_NAMES; const char *mach_galileo_names[] = GROUP_GALILEO_NAMES; - const char *mach_pmc_names[] = GROUP_PMC_NAMES; + const char *mach_momenco_names[] = GROUP_MOMENCO_NAMES; const char **mach_group_to_name[] = { mach_unknown_names, mach_jazz_names, mach_dec_names, mach_arc_names, mach_sni_rm_names, mach_acn_names, mach_sgi_names, mach_cobalt_names, mach_nec_ddb_names, mach_baget_names, - mach_cosine_names, mach_galileo_names, mach_pmc_names }; + mach_cosine_names, mach_galileo_names, mach_momenco_names }; unsigned int version = read_32bit_cp0_register(CP0_PRID); int len; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 5f8662bd9..ac5c909d0 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -447,7 +447,7 @@ void __init setup_arch(char **cmdline_p) void sgi_setup(void); void ev96100_setup(void); void malta_setup(void); - void cp7000_setup(void); + void momenco_ocelot_setup(void); unsigned long bootmap_size; unsigned long start_pfn, max_pfn; @@ -497,9 +497,9 @@ void __init setup_arch(char **cmdline_p) malta_setup(); break; #endif -#ifdef CONFIG_PMC_CP7000 - case MACH_GROUP_PMC: - cp7000_setup(); +#ifdef CONFIG_MOMENCO_OCELOT + case MACH_GROUP_MOMENCO: + momenco_ocelot_setup(); break; #endif #ifdef CONFIG_SGI_IP22 diff --git a/arch/mips/mm/loadmmu.c b/arch/mips/mm/loadmmu.c index b77ef4079..8d618e913 100644 --- a/arch/mips/mm/loadmmu.c +++ b/arch/mips/mm/loadmmu.c @@ -56,6 +56,10 @@ void __init loadmmu(void) printk("Loading R4000 MMU routines.\n"); ld_mmu_r4xx0(); #endif +#if defined(CONFIG_CPU_RM7000) + printk("Loading RM7000 MMU routines.\n"); + ld_mmu_rm7k(); +#endif #if defined(CONFIG_CPU_MIPS32) printk("Loading MIPS32 MMU routines.\n"); ld_mmu_mips32(); @@ -78,13 +82,6 @@ void __init loadmmu(void) break; #endif -#if defined(CONFIG_CPU_RM7000) - case CPU_RM7000: - printk("Loading RM7000 MMU routines.\n"); - ld_mmu_rm7k(); - break; -#endif - #ifdef CONFIG_CPU_R10000 case CPU_R10000: printk("Loading R10000 MMU routines.\n"); diff --git a/arch/mips/pmc/cp7000/cntmr.c b/arch/mips/pmc/cp7000/cntmr.c deleted file mode 100644 index 568a88cb0..000000000 --- a/arch/mips/pmc/cp7000/cntmr.c +++ /dev/null @@ -1,207 +0,0 @@ -/* cntmr.c - GT counters/timers functions */ - -/* Copyright - Galileo technology. 9/3/2000 */ - -/* -DESCRIPTION -This file contains function which serves the user with a complete interface -to the GT internal counters and timers, please advise: each counter/timer unit -can function only as a counter or a timer at current time. -Counter/timer 0 is 32 bit wide. -Counters/timers 1-3 are 24 bit wide. -*/ - -/* includes */ - -#ifdef __linux__ -#include <asm/galileo/evb64120A/cntmr.h> -#include <asm/galileo/evb64120A/core.h> -#else -#include "cntmr.h" -#include "core.h" -#endif - -/******************************************************************** -* cntTmrStart - Starts a counter/timer with given an initiate value. -* -* INPUTS: unsigned int countNum - Selects one of the 8 counters/timers. -* unsigned int countValue - Initial value for count down. -* CNT_TMR_OP_MODES opMode - Set Mode, Counter or Timer. -* -* RETURNS: false if one of the parameters is erroneous, true otherwise. -*********************************************************************/ - -bool cntTmrStart(CNTMR_NUM countNum, unsigned int countValue, - CNT_TMR_OP_MODES opMode) -{ - unsigned int command = 1; - unsigned int value; - - if (countNum > LAST_CNTMR) - return false; - else { - GT_REG_READ(TIMER_COUNTER_CONTROL, &value); - cntTmrDisable(countNum); - GT_REG_WRITE((TIMER_COUNTER0 + (4 * countNum)), - countValue); - command = command << countNum * 2; - value = value | command; - command = command << 1; - switch (opMode) { - case TIMER: /* The Timer/Counter bit set to logic '1' */ - value = value | command; - break; - case COUNTER: /* The Timer/Counter bit set to logic '0' */ - value = value & ~command; - break; - default: - return false; - } - GT_REG_WRITE(TIMER_COUNTER_CONTROL, value); - return true; - } -} - -/******************************************************************** -* cntTmrDisable - Disables the timer/counter operation and return its -* value. -* -* INPUTS: unsigned int countNum - Selects one of the 8 counters/timers. -* RETURNS: The counter/timer value (unsigned int), if any of the arguments are -* erroneous return 0. -*********************************************************************/ - -unsigned int cntTmrDisable(CNTMR_NUM countNum) -{ - unsigned int command = 1; - unsigned int regValue; - unsigned int value; - - GT_REG_READ(TIMER_COUNTER_CONTROL, &value); - if (countNum > LAST_CNTMR) - return 0; - GT_REG_READ(TIMER_COUNTER0 + 4 * countNum, ®Value); - command = command << countNum * 2; /* Disable the timer/counter */ - value = value & ~command; - GT_REG_WRITE(TIMER_COUNTER_CONTROL, value); - return regValue; -} - -/******************************************************************** -* cntTmrRead - Reads a timer or a counter value. (This operation can be -* perform while the counter/timer is active). -* -* RETURNS: The counter/timer value. If wrong input value, return 0. -*********************************************************************/ - -unsigned int cntTmrRead(CNTMR_NUM countNum) -{ - unsigned int value; - if (countNum > LAST_CNTMR) - return 0; - else - GT_REG_READ(TIMER_COUNTER0 + countNum * 4, &value); - return value; -} - -/******************************************************************** -* cntTmrEnable - Set enable-bit of timer/counter. -* Be aware: If the counter/timer is active, this function -* will terminate with an false. -* -* INPUTS: unsigned int countNum - Selects one of the 8 counters/timers. -* RETURNS: false if one of the parameters is erroneous, true otherwise. -*********************************************************************/ - -bool cntTmrEnable(CNTMR_NUM countNum) -{ - unsigned int command = 1; - unsigned int value; - GT_REG_READ(TIMER_COUNTER_CONTROL, &value); - if (countNum > LAST_CNTMR) - return false; - else { - command = command << countNum * 2; - if ((command & value) != 0) /* ==> The counter/timer is enabled */ - return false; /* doesn't make sense to Enable an "enabled" counter */ - value = value | command; - GT_REG_WRITE(TIMER_COUNTER_CONTROL, value); - return true; - } -} - -/******************************************************************** -* cntTmrLoad - loading value for timer number countNum. -* Be aware: If this function try to load value to an enabled -* counter/timer it terminate with false. -* -* INPUTS: unsigned int countNum - Selects one of the 8 counters/timers. -* unsigned int countValue - The value for load the register. -* RETURNS: false if one of the parameters is erroneous, true otherwise. -*********************************************************************/ - -bool cntTmrLoad(unsigned int countNum, unsigned int countValue) -{ - unsigned int command = 1; - unsigned int value; - GT_REG_READ(TIMER_COUNTER_CONTROL, &value); - if (countNum > LAST_CNTMR) - return false; - else { - command = command << countNum * 2; - value = value & command; - if (value != 0) { /* ==> The counter/timer is enabled */ - return false; /* can't reload value when counter/timer is enabled */ - } else { - GT_REG_WRITE((TIMER_COUNTER0 + (4 * countNum)), - countValue); - return true; - } - - } -} - -/******************************************************************** -* cntTmrSetMode - Configurate the Mode of the channel to work as a counter -* or as a timer. (for more details on the different between -* those two modes is written in the Data Sheet). -* NOTE: This function only set the counter/timer mode and -* don't enable it. -* Be aware: If this function try to load value to an enabled -* counter/timer it terminate with false. -* -* INPUTS: unsigned int countNum - Selects one of the 8 counters/timers. -* CNT_TMR_OP_MODES opMode - TIMER or COUNTER mode. -* RETURNS: false if one of the parameters is erroneous true otherwise . -*********************************************************************/ - -bool cntTmrSetMode(CNTMR_NUM countNum, CNT_TMR_OP_MODES opMode) -{ - unsigned int command = 1; - unsigned int value; - - GT_REG_READ(TIMER_COUNTER_CONTROL, &value); - if (countNum > LAST_CNTMR) - return false; - else { - command = command << countNum * 2; - value = value & command; - if (value != 0) { /* ==> The counter/timer is enabled */ - return false; /* can't set the Mode when counter/timer is enabled */ - } else { - command = command << 1; - switch (opMode) { - case TIMER: - value = value | command; /* The Timer/Counter bit set to logic '1' */ - break; - case COUNTER: - value = value & ~command; /*The Timer/Counter bit set to logic '0' */ - break; - default: - return false; - } - GT_REG_WRITE(TIMER_COUNTER_CONTROL, value); - return true; - } - } -} diff --git a/arch/mips/pmc/cp7000/dma.c b/arch/mips/pmc/cp7000/dma.c deleted file mode 100644 index e7f7362c2..000000000 --- a/arch/mips/pmc/cp7000/dma.c +++ /dev/null @@ -1,163 +0,0 @@ -/* DMA.C - DMA functions and definitions */ - -/* Copyright Galileo Technology. */ - -/* - * DESCRIPTION - * This file gives the user a complete interface to the powerful DMA engines, - * including functions for controling the priority mechanism. - * To fully understand the capabilities of the DMA engines please spare some - * time to go trough the spec. - */ - -#include <asm/galileo/evb64120A/core.h> -#include <asm/galileo/evb64120A/dma.h> - -/* - * dmaCommand - Write a command to a DMA channel - * - * Inputs: DMA_ENGINE channel - choosing one of the four engine. - * unsigned int command - The command to be written to the control - * register. - * Returns: false if one of the parameters is erroneous else returns true. - */ - -bool dmaCommand(DMA_ENGINE channel, unsigned int command) -{ - if (channel > LAST_DMA_ENGINE) - return false; - - GT_REG_WRITE(CHANNEL0CONTROL + channel * 4, command); - return true; -} - -/* - * dmaTransfer - transfer data from sourceAddr to destAddr on DMA channel - * Inputs: - * DMA_RECORED *nextRecoredPointer: If we are using chain mode DMA transfer, - * then this pointer should point to the next recored,otherwise it should be - * NULL. - * VERY IMPORTANT !!! When using chain mode, the records must be 16 Bytes - * aligned, the function will take care of that for you, but you need to - * allocate one more record for that, meaning: if you are having 3 records , - * declare 4 (see the example bellow) and start using the second one. - * Example: - * Performing a chain mode DMA transfer(Copy a 1/4 mega of data using - * chain mode DMA): - * DMA_RECORED dmaRecoredArray[4]; - * dmaRecoredArray[1].ByteCnt = _64KB; - * dmaRecoredArray[1].DestAdd = destAddress + _64KB; - * dmaRecoredArray[1].SrcAdd = sourceAddress + _64KB; - * dmaRecoredArray[1].NextRecPtr = &dmaRecoredArray[2]; - * dmaRecoredArray[2].ByteCnt = _64KB; - * dmaRecoredArray[2].DestAdd = destAddress + 2*_64KB; - * dmaRecoredArray[2].SrcAdd = sourceAddress + 2*_64KB; - * dmaRecoredArray[2].NextRecPtr = &dmaRecoredArray[3]; - * dmaRecoredArray[3].ByteCnt = _64KB; - * dmaRecoredArray[3].DestAdd = destAddress + 3*_64KB; - * dmaRecoredArray[3].SrcAdd = sourceAddress + 3*_64KB; - * dmaRecoredArray[3].NextRecPtr = NULL; - * performCmDma(0,sourceAddress,destAddress,_64KB,PLAIN,WAIT_TO_END, - * &dmaRecoredArray[1]); - * Returns: NO_SUCH_CHANNEL if channel does not exist, CHANNEL_BUSY if channel - * is active and true if the transfer ended successfully - */ - -DMA_STATUS dmaTransfer(DMA_ENGINE channel, unsigned int sourceAddr, - unsigned int destAddr, unsigned int numOfBytes, - unsigned int command, - DMA_RECORED * nextRecoredPointer) -{ - unsigned int tempData, checkBits, alignmentOffset = 0; - DMA_RECORED *next = nextRecoredPointer; - - if (channel > LAST_DMA_ENGINE) - return NO_SUCH_CHANNEL; - if (numOfBytes > 0xffff) - return GENERAL_ERROR; - if (isDmaChannelActive(channel)) - return CHANNEL_BUSY; - if (next != NULL) { /* case of chain Mode */ - alignmentOffset = ((unsigned int) next % 16); - } - checkBits = command & 0x6000000; - if (checkBits == 0) { - while (next != NULL) { - WRITE_WORD((unsigned int) next - alignmentOffset, - next->ByteCnt); - tempData = (unsigned int) next->SrcAdd; - WRITE_WORD((unsigned int) next + 4 - - alignmentOffset, tempData & 0x5fffffff); - tempData = (unsigned int) next->DestAdd; - WRITE_WORD((unsigned int) next + 8 - - alignmentOffset, tempData & 0x5fffffff); - tempData = (unsigned int) next->NextRecPtr; - WRITE_WORD((unsigned int) next + 12 - - alignmentOffset, - tempData & 0x5fffffff - - alignmentOffset); - next = (DMA_RECORED *) tempData; - if (next == nextRecoredPointer) - next = NULL; - } - } - GT_REG_WRITE(CHANNEL0_DMA_BYTE_COUNT + channel * 4, numOfBytes); - tempData = sourceAddr; - GT_REG_WRITE(CHANNEL0_DMA_SOURCE_ADDRESS + channel * 4, - tempData & 0x5fffffff); - tempData = destAddr; - GT_REG_WRITE(CHANNEL0_DMA_DESTINATION_ADDRESS + channel * 4, - tempData & 0x5fffffff); - if (nextRecoredPointer != NULL) { - tempData = - (unsigned int) nextRecoredPointer - alignmentOffset; - GT_REG_WRITE(CHANNEL0NEXT_RECORD_POINTER + 4 * channel, - tempData & 0x5fffffff); - command = command | CHANNEL_ENABLE; - } else { - command = command | CHANNEL_ENABLE | NON_CHAIN_MOD; - } - /* Activate DMA engine By writting to dmaControlRegister */ - GT_REG_WRITE(CHANNEL0CONTROL + channel * 4, command); - - return DMA_OK; -} - -/* - * isDmaChannelActive - check if channel is busy - * - * Inputs: channel number - * RETURNS: True if the channel is busy, false otherwise. - */ -bool isDmaChannelActive(DMA_ENGINE channel) -{ - unsigned int data; - - if (channel > LAST_DMA_ENGINE) - return false; - - GT_REG_READ(CHANNEL0CONTROL + 4 * channel, &data); - if (data & DMA_ACTIVITY_STATUS) - return true; - - return false; -} - - -/* - * changeDmaPriority - update the arbiter`s priority for channels 0-3 - * - * Inputs: priority for channels 0-1, priority for channels 2-3, - * priority for groups and other priority options - * RETURNS: false if one of the parameters is erroneous and true else - */ -bool changeDmaPriority(PRIO_CHAN_0_1 prio_01, PRIO_CHAN_2_3 prio_23, - PRIO_GROUP prioGrp, PRIO_OPT prioOpt) -{ - unsigned int prioReg = 0; - - prioReg = (prio_01 & 0x3) + ((prio_23 & 0x3) << 2) + - ((prioGrp & 0x3) << 4) + (prioOpt << 6); - GT_REG_WRITE(ARBITER_CONTROL, prioReg); - return true; -} diff --git a/arch/mips/pmc/cp7000/i2o.c b/arch/mips/pmc/cp7000/i2o.c deleted file mode 100644 index b78519a14..000000000 --- a/arch/mips/pmc/cp7000/i2o.c +++ /dev/null @@ -1,684 +0,0 @@ -/* i2o.c - Drivers for the I2O */ - -/* Copyright - Galileo technology. */ - -/*includes*/ - -#include <linux/module.h> - -#include <asm/galileo-boards/evb64120A/core.h> -#include <asm/galileo-boards/evb64120A/i2o.h> - -/* - * getInBoundMessage - When the GT is configured for I2O support - * it can receive a message from an agent on the pci bus. - * This message is a 32 bit wide and can be read by - * the CPU. - * The messaging unit contains two sets of registers - * so, actually it can receive a 64 bit message. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * OUTPUT: N/A. - * RETURNS: Data received from the remote agent. - */ -unsigned int getInBoundMessage(I2O_MESSAGE_REG messageRegNum) -{ - unsigned int regValue; - - GT_REG_READ(INBOUND_MESSAGE_REGISTER0_CPU_SIDE + 4 * messageRegNum, - ®Value); - return (regValue); -} - - -/* - * checkInboundIntAndClear - When a message is received an interrupt is - * generated, to enable polling instead the use of - * an interrupt handler the user can use this fuction. - * You will need to mask the incomming interrupt for - * proper use. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * OUTPUT: N/A. - * RETURNS: true if the corresponding bit in the cause register is set otherwise - * false. - */ -bool checkInBoundIntAndClear(I2O_MESSAGE_REG messageRegNum) -{ - unsigned int regValue; - - GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Value); - /* clears bit 0 for message register 0 or bit 1 for message register 1 */ - GT_REG_WRITE(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, - BIT1 * messageRegNum); - switch (messageRegNum) { - case MESSAGE_REG_0: - if (regValue & BIT0) - return true; - break; - case MESSAGE_REG_1: - if (regValue & BIT1) - return true; - break; - } - return false; -} - -/* - * sendOutBoundMessage - When the GT is configured for I2O support - * it can send a message to an agent on the pci bus. - * This message is a 32 bit wide and can be read by - * the PCI agent. - * The messaging unit contains two sets of registers - * so, actually it can send a 64 bit message. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * unsigned int message - Message to be sent. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool sendOutBoundMessage(I2O_MESSAGE_REG messageRegNum, - unsigned int message) -{ - GT_REG_WRITE(OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE + - 4 * messageRegNum, message); - return true; -} - -/* - * checkOutboundInt - When the CPU sends a message to the Outbound - * register it generates an interrupt which is refelcted on - * the Outbound Interrupt cause register, the interrupt can - * be cleard only by the PCI agent which read the message. - * After sending the message you can acknowledge it by - * monitoring the corresponding bit in the cause register. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * OUTPUT: N/A. - * RETURNS: true if the corresponding bit in the cause register is set otherwise - * false. - */ -bool outBoundMessageAcknowledge(I2O_MESSAGE_REG messageRegNum) -{ - unsigned int regValue; - - GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Value); - switch (messageRegNum) { - case MESSAGE_REG_0: - if (regValue & BIT0) - return true; - break; - case MESSAGE_REG_1: - if (regValue & BIT1) - return true; - break; - } - return false; -} - -/* - * maskInBoundMessageInterrupt - Mask the inbound interrupt, when masking - * the interrupt you can work in polling mode - * using the checkInboundIntAndClear function. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool maskInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) -{ - switch (messageRegNum) { - case MESSAGE_REG_0: - SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT0); - break; - case MESSAGE_REG_1: - SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT1); - break; - } - return true; -} - -/* - * enableInBoundMessageInterrupt - unMask the inbound interrupt. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool enableInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) -{ - switch (messageRegNum) { - case MESSAGE_REG_0: - RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT0); - break; - case MESSAGE_REG_1: - RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT1); - break; - } - return true; -} - -/* - * maskOutboundMessageInterrupt - Mask the out bound interrupt, when doing so - * the PCI agent needs to poll on the interrupt - * cause register to monitor an incoming message. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool maskOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) -{ - switch (messageRegNum) { - case MESSAGE_REG_0: - SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT0); - break; - case MESSAGE_REG_1: - SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT1); - break; - } - return true; -} - -/* - * enableOutboundMessageInterrupt - Mask the out bound interrupt, when doing so - * the PCI agent needs to poll on the interrupt - * cause register to monitor an incoming message. - * - * INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool enableOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) -{ - switch (messageRegNum) { - case MESSAGE_REG_0: - RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT0); - break; - case MESSAGE_REG_1: - RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - BIT1); - break; - } - return true; -} - -/* - * initiateOutBoundDoorBellInt - Setting a bit in this register to '1' by the - * CPU generates a PCI interrupt (if it is not masked by - * the Outbound interrupt Mask register) - * Only the PCI agent which recieved the interrupt can - * clear it, only after clearing all the bits the - * interrupt will be de-asserted. - * - * INPUTS: unsigned int data - Requested interrupt bits. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool initiateOutBoundDoorBellInt(unsigned int data) -{ - GT_REG_WRITE(OUTBOUND_DOORBELL_REGISTER_CPU_SIDE, data); - return true; -} - -/* - * readInBoundDoorBellInt - Read the in bound door bell interrupt cause - * register. - * - * OUTPUT: N/A. - * RETURNS: The 32 bit interrupt cause register. - */ -unsigned int readInBoundDoorBellInt() -{ - unsigned int regData; - GT_REG_READ(INBOUND_DOORBELL_REGISTER_CPU_SIDE, ®Data); - return regData; -} - -/* - * clearInBoundDoorBellInt - An interrupt generated by a PCI agent through - * the in bound door bell mechanisem can be cleared - * only by the CPU. The interrupt will be de-asserted - * only if all the bits which where set by the PCI - * agent are cleared. - * - * INPUTS: unsigned int data - Bits to be cleared. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool clearInBoundDoorBellInt(unsigned int data) -{ - GT_REG_WRITE(INBOUND_DOORBELL_REGISTER_CPU_SIDE, data); - return true; -} - -/* - * isInBoundDoorBellInterruptSet - Check if Inbound Doorbell Interrupt is set, - * can be used for polling mode. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true if the corresponding bit in the cause register is set otherwise - * false. - */ -bool isInBoundDoorBellInterruptSet() -{ - unsigned int regData; - - GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); - return (regData & BIT2); -} - -/* - * isOutBoundDoorBellInterruptSet - Check if out bound Doorbell Interrupt is - * set, can be used for acknowledging interrupt - * handling by the agent who recieived the - * interrupt. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true if the corresponding bit in the cause register is set otherwise - * false. - */ -bool isOutBoundDoorBellInterruptSet() -{ - unsigned int regData; - - GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); - return (regData & BIT2); -} - -/* - * maskInboundDoorBellInterrupt - Mask the Inbound Doorbell Interrupt. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool maskInBoundDoorBellInterrupt() -{ - SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); - return true; -} - -/* - * enableInboundDoorBellInterrupt - unMask the Inbound Doorbell Interrupt. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool enableInBoundDoorBellInterrupt() -{ - RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); - return true; -} - -/* - * maskOutboundDoorBellInterrupt - Mask the Outbound Doorbell Interrupt. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool maskOutBoundDoorBellInterrupt() -{ - SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); - return true; -} - -/* - * enableOutboundDoorBellInterrupt - unMask the Outbound Doorbell Interrupt. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool enableOutBoundDoorBellInterrupt() -{ - RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); - return true; -} - -/* - * circularQueueEnable - Initialize the I2O messaging mechanism. - * - * INPUTS: CIRCULE_QUEUE_SIZE cirQueSize - Bits 5:1 in the: - * Queue Control Register, Offset 0x50 (0x1c50). - * Defines the queues size (refer to the data sheet - * for more information) - * unsigned int queueBaseAddr - The base address for the first queue. - * The other queues base Address will be determined as follows: - * Inbound Free = queueBaseAddr - * Inbound Post = queueBaseAddr + cirQueSize - * Outbound Post = queueBaseAddr + cirQueSize - * - * OUTPUT: N/A. - * RETURNS: true. - * - * The Circular Queue Starting Addresses as written in the spec: - * ---------------------------------------- - * | Queue | Starting Address | - * |----------------|---------------------| - * | Inbound Free | QBAR | - * | Inbound Post | QBAR + Queue Size | - * | Outbound Post | QBAR + 2*Queue Size | - * | Outbound Free | QBAR + 3*Queue Size | - * ---------------------------------------- - */ -bool circularQueueEnable(CIRCULAR_QUEUE_SIZE cirQueSize, - unsigned int queueBaseAddr) -{ - unsigned int regData; - - regData = BIT0 | (cirQueSize << 1); - /* Enable Queue Operation */ - GT_REG_WRITE(QUEUE_CONTROL_REGISTER_CPU_SIDE, regData); - /* Writing The base Address for the 4 Queues */ - GT_REG_WRITE(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, queueBaseAddr); - /* Update The Inbound Free Queue Base Address, offset=0 */ - GT_REG_WRITE(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, 0); - GT_REG_WRITE(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, 0); - /* Update The Inbound Post Queue Base Address, offset=_16K*cirQueSize */ - GT_REG_WRITE(INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, - _16K * cirQueSize); - GT_REG_WRITE(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, - _16K * cirQueSize); - /* Update The Outbound Post Queue Base Address, offset=2*_16K*cirQueSize */ - GT_REG_WRITE(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, - 2 * _16K * cirQueSize); - GT_REG_WRITE(OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, - 2 * _16K * cirQueSize); - /* Update The Outbound Free Queue Base Address, offset=3*_16K*cirQueSize */ - GT_REG_WRITE(OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, - 3 * _16K * cirQueSize); - GT_REG_WRITE(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, - 3 * _16K * cirQueSize); - return true; -} - -/* - * inBoundPostQueuePop - Two actions are being taken upon pop: - * 1) Getting out the data from the Queue`s head. - * 2) Increment the tail pointer in a cyclic way (The HEAD is - * incremented automaticaly by the GT) - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: Data pointed by tail. - */ -unsigned int inBoundPostQueuePop() -{ - unsigned int tailAddrPointer; - unsigned int data; - unsigned int cirQueSize; - unsigned int qBar; - unsigned int inBoundPostQbase; - - /* Gets the Inbound Post TAIL pointer */ - GT_REG_READ(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, - &tailAddrPointer); - /* Gets the Data From the pointer Address */ - READ_WORD(tailAddrPointer, &data); - /* incrementing head process: */ - /* Gets the fifo's base Address */ - GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); - qBar = qBar & 0xfff00000; - /* Gets the fifo's size */ - GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); - cirQueSize = 0x1f && (cirQueSize >> 1); - /* calculating The Inbound Post Queue Base Address */ - inBoundPostQbase = qBar + 1 * cirQueSize * _16K; - /* incrementing Inbound Post queue TAIL in a cyclic loop */ - tailAddrPointer = inBoundPostQbase + ((tailAddrPointer + 4) % - (_16K * cirQueSize)); - /* updating the pointer back to INBOUND_POST_TAIL_POINTER_REGISTER */ - GT_REG_WRITE(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, - tailAddrPointer); - return data; -} - -/* - * isInBoundPostQueueInterruptSet - Check if in bound interrupt is set. - * can be used for polling mode. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true if the corresponding bit in the cause register is set otherwise - * false. - */ -bool isInBoundPostQueueInterruptSet() -{ - unsigned int regData; - - GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); - return (regData & BIT4); /* if set return '1' (true), else '0' (false) */ -} - -/* - * clearInBoundPostQueueInterrupt - Clears the Post queue interrupt. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool clearInBoundPostQueueInterrupt() -{ - GT_REG_WRITE(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, BIT4); - return true; -} - -/* - * maskInBoundPostQueueInterrupt - Mask the inbound interrupt, when masking - * the interrupt you can work in polling mode. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: - */ -void maskInBoundPostQueueInterrupt() -{ - unsigned int regData; - - GT_REG_READ(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, ®Data); - GT_REG_WRITE(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - regData | BIT4); - -} - -/* - * enableInBoundPostQueueInterrupt - Enable interrupt when ever there is a new - * message from the PCI agent. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: - */ -void enableInBoundPostQueueInterrupt() -{ - unsigned int regData; - - GT_REG_READ(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, ®Data); - GT_REG_WRITE(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, - regData & 0xfffffffb); -} - -/* - * inBoundFreeQueuePush - Two actions are being taken upon push: - * 1) Place the user`s data on the Queue`s head. - * 2) Increment the haed pointer in a cyclic way (The tail is - * decremented automaticaly by the GT) - * - * INPUTS: unsigned int data - Data to be placed in the queue. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool inBoundFreeQueuePush(unsigned int data) -{ - unsigned int headPointer; - unsigned int cirQueSize; - unsigned int qBar; - unsigned int inBoundFreeQbase; - - GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, - &headPointer); - /* placing the data in the queue */ - WRITE_WORD(headPointer, data); - /* incrementing head process: */ - /* Gets the fifo's base Address */ - GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); - qBar = qBar & 0xfff00000; - /* Gets the fifo's size */ - GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); - cirQueSize = 0x1f && (cirQueSize >> 1); - /* calculating The Inbound Free Queue Base Address */ - inBoundFreeQbase = qBar; - /* incrementing Inbound Free queue HEAD in a cyclic loop */ - headPointer = - inBoundFreeQbase + ((headPointer + 4) % (_16K * cirQueSize)); - /* updating the pointer back to OUTBOUND_POST_HEAD_POINTER_REGISTER */ - GT_REG_WRITE(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, - headPointer); - return true; -} - -/* - * isInBoundFreeQueueEmpty - Check if Inbound Free Queue Empty. - * Can be used for acknowledging the messages - * being sent by us to the PCI agent. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true if the queue is empty , otherwise false. - */ -bool isInBoundFreeQueueEmpty() -{ - unsigned int inBoundFreeQueHead; - unsigned int inBoundFreeQueTail; - - GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, - &inBoundFreeQueHead); - GT_REG_READ(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, - &inBoundFreeQueTail); - if (inBoundFreeQueHead == inBoundFreeQueTail) { - return true; - } else - return false; -} - -/* - * outBoundPostQueuePush - Two actions are being taken upon push: - * 1) Place the user`s data on the Queue`s head. - * 2) Increment the haed pointer in a cyclic way (The tail is - * decremented automaticaly by the GT when the Agent on the - * PCI have read data from the Outbound Port). - * - * INPUTS: unsigned int data - Data to be placed in the queue`s head. - * OUTPUT: N/A. - * RETURNS: true. - */ -bool outBoundPostQueuePush(unsigned int data) -{ - unsigned int headPointer; - unsigned int cirQueSize; - unsigned int qBar; - unsigned int outBoundPostQbase; - - GT_REG_READ(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, - &headPointer); - /* placing the data in the queue (where the head point to..) */ - WRITE_WORD(headPointer, data); - /* incrementing head process: */ - /* Gets the fifo's base Address */ - GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); - qBar = qBar & 0xfff00000; - /* Gets the fifo's size */ - GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); - cirQueSize = 0x1f && (cirQueSize >> 1); - /* calculating The Outbound Post Queue Base Address */ - outBoundPostQbase = qBar + 2 * cirQueSize * _16K; - /* incrementing Outbound Post queue in a cyclic loop */ - headPointer = - outBoundPostQbase + ((headPointer + 4) % (_16K * cirQueSize)); - /* updating the pointer back to OUTBOUND_POST_HEAD_POINTER_REGISTER */ - GT_REG_WRITE(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, - headPointer); - return true; -} - -/* - * isOutBoundPostQueueEmpty - Check if Outbound Post Queue Empty. - * Can be used for acknowledging the messages - * being sent by us to the PCI agent. - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: true if the queue is empty , otherwise false. - */ -bool isOutBoundPostQueueEmpty() -{ - unsigned int outBoundPostQueHead; - unsigned int outBoundPostQueTail; - - GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, - &outBoundPostQueHead); - GT_REG_READ(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, - &outBoundPostQueTail); - if (outBoundPostQueHead == outBoundPostQueTail) { - return true; - } else - return false; -} - -/* - * outBoundFreeQueuePop - Two actions are being taken upon pop: - * 1) Getting out the data from the Queue`s head. - * 2) Increment the tail pointer in a cyclic way (The HEAD is - * incremented automaticaly by the GT) - * - * INPUTS: N/A. - * OUTPUT: N/A. - * RETURNS: Data pointed by tail. - */ -unsigned int outBoundFreeQueuePop() -{ - unsigned int tailAddrPointer; - unsigned int data; - unsigned int cirQueSize; - unsigned int qBar; - unsigned int outBoundFreeQbase; - - /* Gets the Inbound Post TAIL pointer */ - GT_REG_READ(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, - &tailAddrPointer); - /* Gets the Data From the pointer Address */ - READ_WORD(tailAddrPointer, &data); - /* incrementing head process: */ - /* Gets the fifo's base Address */ - GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); - qBar = qBar & 0xfff00000; - /* Gets the fifo's size */ - GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); - cirQueSize = 0x1f && (cirQueSize >> 1); - /* calculating The Inbound Post Queue Base Address */ - outBoundFreeQbase = qBar + 3 * cirQueSize * _16K; - /* incrementing Outbound Free queue TAlL in a cyclic loop */ - tailAddrPointer = outBoundFreeQbase + ((tailAddrPointer + 4) % - (_16K * cirQueSize)); - /* updating the pointer back to OUTBOUND_FREE_TAIL_POINTER_REGISTER */ - GT_REG_WRITE(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, - tailAddrPointer); - return data; -} - - -EXPORT_SYMBOL(isInBoundDoorBellInterruptSet); -EXPORT_SYMBOL(initiateOutBoundDoorBellInt); -EXPORT_SYMBOL(clearInBoundDoorBellInt); diff --git a/arch/mips/pmc/cp7000/promcon.c b/arch/mips/pmc/cp7000/promcon.c deleted file mode 100644 index 313cd2435..000000000 --- a/arch/mips/pmc/cp7000/promcon.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/console.h> -#include <linux/kdev_t.h> -#include <linux/major.h> - -#include <asm/serial.h> - -/* SUPERIO uart register map */ -typedef volatile struct uartregs { - union { - volatile u8 rbr; /* read only, DLAB == 0 */ - volatile u8 thr; /* write only, DLAB == 0 */ - volatile u8 dll; /* DLAB == 1 */ - } u1; - u8 __pad0[3]; - union { - volatile u8 ier; /* DLAB == 0 */ - volatile u8 dlm; /* DLAB == 1 */ - } u2; - u8 __pad1[3]; - union { - volatile u8 iir; /* read only */ - volatile u8 fcr; /* write only */ - } u3; - u8 __pad2[3]; - volatile u8 iu_lcr; - u8 __pad3[3]; - volatile u8 iu_mcr; - u8 __pad4[3]; - volatile u8 iu_lsr; - u8 __pad5[3]; - volatile u8 iu_msr; - u8 __pad6[3]; - volatile u8 iu_scr; - u8 __pad7[3]; -} ioc3_uregs_t; - -#define iu_rbr u1.rbr -#define iu_thr u1.thr -#define iu_dll u1.dll -#define iu_ier u2.ier -#define iu_dlm u2.dlm -#define iu_iir u3.iir -#define iu_fcr u3.fcr - -void ns_putchar(char c) -{ - struct uartregs *uart = (struct uartregs *) CP7000_SERIAL1_BASE; - - while ((uart->iu_lsr & 0x20) == 0); - uart->iu_thr = c; -} - -char __init prom_getchar(void) -{ - return 0; -} - -//static void -void -ns_console_write(struct console *con, const char *s, unsigned n) -{ - int i; - - /* Somewhat oversimplified because only used during early startup. */ - for (i = 0; i < n; i++, s++) { - ns_putchar(*s); - if (*s == 10) - ns_putchar(13); - } -} - -static kdev_t -ns_console_dev(struct console *c) -{ - return MKDEV(TTY_MAJOR, 64 + c->index); -} - -static struct console ns_console = { - name: "ns16552", - write: ns_console_write, - device: ns_console_dev, - flags: CON_PRINTBUFFER, - index: -1, -}; - -__init void ns_setup_console(void) -{ - register_console(&ns_console); -} diff --git a/arch/mips/pmc/cp7000/reset.c b/arch/mips/pmc/cp7000/reset.c deleted file mode 100644 index b145a3446..000000000 --- a/arch/mips/pmc/cp7000/reset.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * EVB96100 -Galileo reset subroutines - * - */ -#include <linux/sched.h> -#include <linux/mm.h> -#include <asm/io.h> -#include <asm/pgtable.h> -#include <asm/processor.h> -#include <asm/reboot.h> -#include <asm/system.h> - -/******************************************************************** - *galileo_machine_restart - - * - *Restart the machine - * - * - *Inputs : - *command - not used - * - *Outpus : - * - *********************************************************************/ -void galileo_machine_restart(char *command) -{ - *(volatile char *) 0xbc000000 = 0x0f; - /* - * Ouch, we're still alive ... This time we take the silver bullet ... - * ... and find that we leave the hardware in a state in which the - * kernel in the flush locks up somewhen during of after the PCI - * detection stuff. - */ - set_cp0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL)); - set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_32bit_cp0_register(CP0_WIRED, 0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -/******************************************************************** - *galileo_machine_halt - - * - *Halt the machine - * - * - *Inputs : - * - *Outpus : - * - *********************************************************************/ -void galileo_machine_halt(void) -{ - printk("\n** You can safely turn off the power\n"); - while (1) { - } -} - -/******************************************************************** - *galileo_machine_power_off - - * - *Halt the machine - * - * - *Inputs : - * - *Outpus : - * - *********************************************************************/ -void galileo_machine_power_off(void) -{ - galileo_machine_halt(); -} diff --git a/arch/mips/pmc/cp7000/serialGT.c b/arch/mips/pmc/cp7000/serialGT.c deleted file mode 100644 index 3d2d4452d..000000000 --- a/arch/mips/pmc/cp7000/serialGT.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * serialGT.c - * - * BRIEF MODULE DESCRIPTION - * Low Level Serial Port control for use - * with the Galileo EVB64120A MIPS eval board and - * its on board two channel 16552 Uart. - * - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -// Note: -// Serial CHANNELS - 0 is the bottom connector of evb64120A. -// (The one that maps to the "B" channel of the -// board's uart) -// 1 is the top connector of evb64120A. -// (The one that maps to the "A" channel of the -// board's uart) -int DEBUG_CHANNEL = 0; // See Note Above -int CONSOLE_CHANNEL = 1; // See Note Above - -#define DUART 0xBD000000 /* Base address of Uart. */ -#define CHANNELOFFSET 0x20 /* DUART+CHANNELOFFSET gets you to the ChanA - register set of the 16552 Uart device. - DUART+0 gets you to the ChanB register set. - */ -#define DUART_DELTA 0x4 -#define FIFO_ENABLE 0x07 -#define INT_ENABLE 0x04 /* default interrupt mask */ - -#define RBR 0x00 -#define THR 0x00 -#define DLL 0x00 -#define IER 0x01 -#define DLM 0x01 -#define IIR 0x02 -#define FCR 0x02 -#define LCR 0x03 -#define MCR 0x04 -#define LSR 0x05 -#define MSR 0x06 -#define SCR 0x07 - -#define LCR_DLAB 0x80 -#define XTAL 1843200 -#define LSR_THRE 0x20 -#define LSR_BI 0x10 -#define LSR_DR 0x01 -#define MCR_LOOP 0x10 -#define ACCESS_DELAY 0x10000 - -/****************************** - Routine: - Description: - ******************************/ -int inreg(int channel, int reg) -{ - int val; - val = - *((volatile unsigned char *) DUART + - (channel * CHANNELOFFSET) + (reg * DUART_DELTA)); - return val; -} - -/****************************** - Routine: - Description: - ******************************/ -void outreg(int channel, int reg, unsigned char val) -{ - *((volatile unsigned char *) DUART + (channel * CHANNELOFFSET) - + (reg * DUART_DELTA)) = val; -} - -/****************************** - Routine: - Description: - Initialize the device driver. - ******************************/ -void serial_init(int channel) -{ - /* - * Configure active port, (CHANNELOFFSET already set.) - * - * Set 8 bits, 1 stop bit, no parity. - * - * LCR<7> 0 divisor latch access bit - * LCR<6> 0 break control (1=send break) - * LCR<5> 0 stick parity (0=space, 1=mark) - * LCR<4> 0 parity even (0=odd, 1=even) - * LCR<3> 0 parity enable (1=enabled) - * LCR<2> 0 # stop bits (0=1, 1=1.5) - * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8) - */ - outreg(channel, LCR, 0x3); - - outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */ - - outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */ -} - -/****************************** - Routine: - Description: - Set the baud rate. - ******************************/ -void serial_set(int channel, unsigned long baud) -{ - unsigned char sav_lcr; - - /* - * Enable access to the divisor latches by setting DLAB in LCR. - * - */ - sav_lcr = inreg(channel, LCR); - -#if 0 - /* - * Set baud rate - */ - outreg(channel, LCR, LCR_DLAB | sav_lcr); - // outreg(DLL,(XTAL/(16*2*(baud))-2)); - outreg(channel, DLL, XTAL / (16 * baud)); - // outreg(DLM,(XTAL/(16*2*(baud))-2)>>8); - outreg(channel, DLM, (XTAL / (16 * baud)) >> 8); -#else - /* - * Note: Set baud rate, hardcoded here for rate of 115200 - * since became unsure of above "buad rate" algorithm (??). - */ - outreg(channel, LCR, 0x83); - outreg(channel, DLM, 0x00); // See note above - outreg(channel, DLL, 0x02); // See note above. - outreg(channel, LCR, 0x03); -#endif - - /* - * Restore line control register - */ - outreg(channel, LCR, sav_lcr); -} - - -/****************************** - Routine: - Description: - Transmit a character. - ******************************/ -void serial_putc(int channel, int c) -{ - while ((inreg(channel, LSR) & LSR_THRE) == 0); - outreg(channel, THR, c); -} - -/****************************** - Routine: - Description: - Read a received character if one is - available. Return -1 otherwise. - ******************************/ -int serial_getc(int channel) -{ - if (inreg(channel, LSR) & LSR_DR) { - return inreg(channel, RBR); - } - return -1; -} - -/****************************** - Routine: - Description: - Used by embedded gdb client. (example; gdb-stub.c) - ******************************/ -char getDebugChar() -{ - int val; - while ((val = serial_getc(DEBUG_CHANNEL)) == -1); // loop until we get a character in. - return (char) val; -} - -/****************************** - Routine: - Description: - Used by embedded gdb target. (example; gdb-stub.c) - ******************************/ -void putDebugChar(char c) -{ - serial_putc(DEBUG_CHANNEL, (int) c); -} diff --git a/arch/mips/pmc/cp7000/setup.c b/arch/mips/pmc/cp7000/setup.c deleted file mode 100644 index ad91ba551..000000000 --- a/arch/mips/pmc/cp7000/setup.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * setup.c - * - * BRIEF MODULE DESCRIPTION - * Galileo Evaluation Boards - board dependent boot routines - * - * Copyright (C) 2000 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/mm.h> -#include <linux/swap.h> -#include <linux/ioport.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/pci.h> -#include <linux/timex.h> -#include <asm/bootinfo.h> -#include <asm/page.h> -#include <asm/bootinfo.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/pci.h> -#include <asm/processor.h> -#include <asm/ptrace.h> -#include <asm/reboot.h> -#include <asm/mc146818rtc.h> -#include <linux/version.h> -#include <linux/bootmem.h> - -extern struct rtc_ops no_rtc_ops; -struct rtc_ops *rtc_ops; - -/* These functions are used for rebooting or halting the machine*/ -extern void galileo_machine_restart(char *command); -extern void galileo_machine_halt(void); -extern void galileo_machine_power_off(void); -/* - *This structure holds pointers to the pci configuration space accesses - *and interrupts allocating routine for device over the PCI - */ -extern struct pci_ops galileo_pci_ops; - -extern unsigned long mips_machgroup; - -char arcs_cmdline[COMMAND_LINE_SIZE]; - -//struct eeprom_parameters eeprom_param; - -/* - * These two functions are added because arch/mips/mm/init.c needs them - * basically they do nothing - */ -void __init prom_fixup_mem_map(unsigned long start, unsigned long end) -{ -} - -void prom_free_prom_memory(void) -{ -} - -int /*__init*/ page_is_ram(unsigned long pagenr) -{ - return 1; -} - -void (*board_time_init) (struct irqaction * irq); - -static unsigned char galileo_rtc_read_data(unsigned long addr) -{ - return 0; -} - -static void galileo_rtc_write_data(unsigned char data, unsigned long addr) -{ -} - -static int galileo_rtc_bcd_mode(void) -{ - return 0; -} - -struct rtc_ops galileo_rtc_ops = { - &galileo_rtc_read_data, - &galileo_rtc_write_data, - &galileo_rtc_bcd_mode -}; - -extern void galileo_time_init(); -void cp7000_setup(void) -{ - unsigned int i, j; - - _machine_restart = galileo_machine_restart; - _machine_halt = galileo_machine_halt; - _machine_power_off = galileo_machine_power_off; - - rtc_ops = &galileo_rtc_ops; - - board_time_init = galileo_time_init; - mips_io_port_base = KSEG1; - set_cp0_status(ST0_FR, 0); - -#ifdef CONFIG_L2_L3_CACHE -#error "external cache not implemented yet" - config_register = read_32bit_cp0_register(CP0_CONFIG); - printk("\n\n\nchecking second level cache cp0_config = %08lx\n", - config_register); - if (config_register & CONF_SC) { // second/third level cache available - config_register = config_register & (1 << 12); - write_32bit_cp0_register(CP0_CONFIG, config_register); - printk - ("\n\n\nchecking second level cache cp0_config = %08lx\n", - config_register); - } -#endif - -} - -/* - * SetUpBootInfo - - * - * This function is called at very first stages of kernel startup. - * It specifies for the kernel the evaluation board that the linux - * is running on. Then it saves the eprom parameters that holds the - * command line, memory size etc... - */ -void SetUpBootInfo(int argc, char **argv, char **envp) -{ - mips_machgroup = MACH_GROUP_GALILEO; - mips_machtype = MACH_EV64120A; -} - -#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) -#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) - -extern void ns_setup_console(void); - -void __init prom_init(int a, char **b, char **c, int *d) -{ - ns_setup_console(); - - mips_machgroup = MACH_GROUP_PMC; - - /* 128mb soldered on the board. */ - add_memory_region(0, 128 << 20, BOOT_MEM_RAM); -} |