diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/Config.in | 3 | ||||
| -rw-r--r-- | drivers/net/Makefile | 1 | ||||
| -rw-r--r-- | drivers/net/saa9730.c | 1086 | ||||
| -rw-r--r-- | drivers/net/saa9730.h | 410 |
4 files changed, 1500 insertions, 0 deletions
diff --git a/drivers/net/Config.in b/drivers/net/Config.in index 4957883f9..7cb160fb7 100644 --- a/drivers/net/Config.in +++ b/drivers/net/Config.in @@ -167,6 +167,9 @@ if [ "$CONFIG_NET_ETHERNET" = "y" ]; then if [ "$CONFIG_OBSOLETE" = "y" ]; then bool ' Zenith Z-Note support (EXPERIMENTAL)' CONFIG_ZNET fi + if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then + bool ' Philips SAA9730 Ethernet support (EXPERIMENTAL)' CONFIG_LAN_SAA9730 + fi fi bool ' Pocket and portable adapters' CONFIG_NET_POCKET if [ "$CONFIG_NET_POCKET" = "y" ]; then diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 145747078..a76f921fe 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -245,6 +245,7 @@ obj-$(CONFIG_8139TOO) += 8139too.o obj-$(CONFIG_WAVELAN) += wavelan.o obj-$(CONFIG_ARLAN) += arlan.o arlan-proc.o obj-$(CONFIG_ZNET) += znet.o +obj-$(CONFIG_LAN_SAA9730) += saa9730.o obj-$(CONFIG_DEPCA) += depca.o obj-$(CONFIG_EWRK3) += ewrk3.o obj-$(CONFIG_ATP) += atp.o diff --git a/drivers/net/saa9730.c b/drivers/net/saa9730.c new file mode 100644 index 000000000..43063a1c1 --- /dev/null +++ b/drivers/net/saa9730.c @@ -0,0 +1,1086 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * SAA9730 ethernet driver. + * + */ + +#include <linux/netdevice.h> +#include <linux/delay.h> +#include <linux/etherdevice.h> +#include <linux/module.h> +#include <linux/skbuff.h> +#include <linux/pci.h> + +#include <asm/addrspace.h> +#include <asm/mips-boards/prom.h> + +#include "saa9730.h" + +#ifdef LAN_SAA9730_DEBUG +int lan_saa9730_debug = LAN_SAA9730_DEBUG; +#else +int lan_saa9730_debug; +#endif + + +/* Non-zero only if the current card is a PCI with BIOS-set IRQ. */ +static unsigned int pci_irq_line = 0; + +#define INL(a) le32_to_cpu(inl((unsigned long)a)) +#define OUTL(x,a) outl(cpu_to_le32(x),(unsigned long)a) + +static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp) +{ + OUTL(INL(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT, + &lp->evm_saa9730_regs->InterruptBlock1); + OUTL(INL(&lp->evm_saa9730_regs->InterruptStatus1) | EVM_LAN_INT, + &lp->evm_saa9730_regs->InterruptStatus1); + OUTL(INL(&lp->evm_saa9730_regs->InterruptEnable1) | EVM_LAN_INT | + EVM_MASTER_EN, &lp->evm_saa9730_regs->InterruptEnable1); +} +static void evm_saa9730_disable_lan_int(struct lan_saa9730_private *lp) +{ + OUTL(INL(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT, + &lp->evm_saa9730_regs->InterruptBlock1); + OUTL(INL(&lp->evm_saa9730_regs->InterruptEnable1) & ~EVM_LAN_INT, + &lp->evm_saa9730_regs->InterruptEnable1); +} + +static void evm_saa9730_clear_lan_int(struct lan_saa9730_private *lp) +{ + OUTL(EVM_LAN_INT, &lp->evm_saa9730_regs->InterruptStatus1); +} + +static void evm_saa9730_block_lan_int(struct lan_saa9730_private *lp) +{ + OUTL(INL(&lp->evm_saa9730_regs->InterruptBlock1) & ~EVM_LAN_INT, + &lp->evm_saa9730_regs->InterruptBlock1); +} + +static void evm_saa9730_unblock_lan_int(struct lan_saa9730_private *lp) +{ + OUTL(INL(&lp->evm_saa9730_regs->InterruptBlock1) | EVM_LAN_INT, + &lp->evm_saa9730_regs->InterruptBlock1); +} + +static void show_saa9730_regs(struct lan_saa9730_private *lp) +{ + int i, j; + printk("TxmBufferA = %x\n", lp->TxmBuffer[0][0]); + printk("TxmBufferB = %x\n", lp->TxmBuffer[1][0]); + printk("RcvBufferA = %x\n", lp->RcvBuffer[0][0]); + printk("RcvBufferB = %x\n", lp->RcvBuffer[1][0]); + for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { + for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) { + printk("TxmBuffer[%d][%d] = %x\n", i, j, + le32_to_cpu(*(unsigned int *) + lp->TxmBuffer[i][j])); + } + } + for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { + for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) { + printk("RcvBuffer[%d][%d] = %x\n", i, j, + le32_to_cpu(*(unsigned int *) + lp->RcvBuffer[i][j])); + } + } + printk("lp->evm_saa9730_regs->InterruptBlock1 = %x\n", + INL(&lp->evm_saa9730_regs->InterruptBlock1)); + printk("lp->evm_saa9730_regs->InterruptStatus1 = %x\n", + INL(&lp->evm_saa9730_regs->InterruptStatus1)); + printk("lp->evm_saa9730_regs->InterruptEnable1 = %x\n", + INL(&lp->evm_saa9730_regs->InterruptEnable1)); + printk("lp->lan_saa9730_regs->Ok2Use = %x\n", + INL(&lp->lan_saa9730_regs->Ok2Use)); + printk("lp->NextTxmBufferIndex = %x\n", lp->NextTxmBufferIndex); + printk("lp->NextTxmPacketIndex = %x\n", lp->NextTxmPacketIndex); + printk("lp->PendingTxmBufferIndex = %x\n", + lp->PendingTxmBufferIndex); + printk("lp->PendingTxmPacketIndex = %x\n", + lp->PendingTxmPacketIndex); + printk("lp->lan_saa9730_regs->LanDmaCtl = %x\n", + INL(&lp->lan_saa9730_regs->LanDmaCtl)); + printk("lp->lan_saa9730_regs->DmaStatus = %x\n", + INL(&lp->lan_saa9730_regs->DmaStatus)); + printk("lp->lan_saa9730_regs->CamCtl = %x\n", + INL(&lp->lan_saa9730_regs->CamCtl)); + printk("lp->lan_saa9730_regs->TxCtl = %x\n", + INL(&lp->lan_saa9730_regs->TxCtl)); + printk("lp->lan_saa9730_regs->TxStatus = %x\n", + INL(&lp->lan_saa9730_regs->TxStatus)); + printk("lp->lan_saa9730_regs->RxCtl = %x\n", + INL(&lp->lan_saa9730_regs->RxCtl)); + printk("lp->lan_saa9730_regs->RxStatus = %x\n", + INL(&lp->lan_saa9730_regs->RxStatus)); + for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) { + OUTL(i, &lp->lan_saa9730_regs->CamAddress); + printk("lp->lan_saa9730_regs->CamData = %x\n", + INL(&lp->lan_saa9730_regs->CamData)); + } + printk("lp->stats.tx_packets = %lx\n", lp->stats.tx_packets); + printk("lp->stats.tx_errors = %lx\n", lp->stats.tx_errors); + printk("lp->stats.tx_aborted_errors = %lx\n", + lp->stats.tx_aborted_errors); + printk("lp->stats.tx_window_errors = %lx\n", + lp->stats.tx_window_errors); + printk("lp->stats.tx_carrier_errors = %lx\n", + lp->stats.tx_carrier_errors); + printk("lp->stats.tx_fifo_errors = %lx\n", + lp->stats.tx_fifo_errors); + printk("lp->stats.tx_heartbeat_errors = %lx\n", + lp->stats.tx_heartbeat_errors); + printk("lp->stats.collisions = %lx\n", lp->stats.collisions); + + printk("lp->stats.rx_packets = %lx\n", lp->stats.rx_packets); + printk("lp->stats.rx_errors = %lx\n", lp->stats.rx_errors); + printk("lp->stats.rx_dropped = %lx\n", lp->stats.rx_dropped); + printk("lp->stats.rx_crc_errors = %lx\n", lp->stats.rx_crc_errors); + printk("lp->stats.rx_frame_errors = %lx\n", + lp->stats.rx_frame_errors); + printk("lp->stats.rx_fifo_errors = %lx\n", + lp->stats.rx_fifo_errors); + printk("lp->stats.rx_length_errors = %lx\n", + lp->stats.rx_length_errors); + + printk("lp->lan_saa9730_regs->DebugPCIMasterAddr = %x\n", + INL(&lp->lan_saa9730_regs->DebugPCIMasterAddr)); + printk("lp->lan_saa9730_regs->DebugLanTxStateMachine = %x\n", + INL(&lp->lan_saa9730_regs->DebugLanTxStateMachine)); + printk("lp->lan_saa9730_regs->DebugLanRxStateMachine = %x\n", + INL(&lp->lan_saa9730_regs->DebugLanRxStateMachine)); + printk("lp->lan_saa9730_regs->DebugLanTxFifoPointers = %x\n", + INL(&lp->lan_saa9730_regs->DebugLanTxFifoPointers)); + printk("lp->lan_saa9730_regs->DebugLanRxFifoPointers = %x\n", + INL(&lp->lan_saa9730_regs->DebugLanRxFifoPointers)); + printk("lp->lan_saa9730_regs->DebugLanCtlStateMachine = %x\n", + INL(&lp->lan_saa9730_regs->DebugLanCtlStateMachine)); +} + +static void lan_saa9730_buffer_init(struct lan_saa9730_private *lp) +{ + int i, j; + + /* Init RX buffers */ + for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { + for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) { + *(unsigned int *) lp->RcvBuffer[i][j] = + cpu_to_le32(RXSF_READY << + RX_STAT_CTL_OWNER_SHF); + } + } + + /* Init TX buffers */ + for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { + for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) { + *(unsigned int *) lp->TxmBuffer[i][j] = + cpu_to_le32(TXSF_EMPTY << + TX_STAT_CTL_OWNER_SHF); + } + } +} + +static int lan_saa9730_allocate_buffers(struct lan_saa9730_private *lp) +{ + unsigned int mem_size; + void *Pa; + unsigned int i, j, RcvBufferSize, TxmBufferSize; + unsigned int buffer_start; + + /* + * Allocate all RX and TX packets in one chunk. + * The Rx and Tx packets must be PACKET_SIZE aligned. + */ + mem_size = ((LAN_SAA9730_RCV_Q_SIZE + LAN_SAA9730_TXM_Q_SIZE) * + LAN_SAA9730_PACKET_SIZE * LAN_SAA9730_BUFFERS) + + LAN_SAA9730_PACKET_SIZE; + buffer_start = + (unsigned int) kmalloc(mem_size, GFP_DMA | GFP_KERNEL); + + /* + * Set DMA buffer to kseg1 (uncached). + * Make sure to flush before using it uncached. + */ + Pa = (void *) KSEG1ADDR((buffer_start + LAN_SAA9730_PACKET_SIZE) & + ~(LAN_SAA9730_PACKET_SIZE - 1)); + dma_cache_wback_inv((unsigned long) Pa, mem_size); + + /* Initialize buffer space */ + RcvBufferSize = LAN_SAA9730_PACKET_SIZE; + TxmBufferSize = LAN_SAA9730_PACKET_SIZE; + lp->DmaRcvPackets = LAN_SAA9730_RCV_Q_SIZE; + lp->DmaTxmPackets = LAN_SAA9730_TXM_Q_SIZE; + + /* Init RX buffers */ + for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { + for (j = 0; j < LAN_SAA9730_RCV_Q_SIZE; j++) { + *(unsigned int *) Pa = + cpu_to_le32(RXSF_READY << + RX_STAT_CTL_OWNER_SHF); + lp->RcvBuffer[i][j] = (unsigned int) Pa; + Pa += RcvBufferSize; + } + } + + /* Init TX buffers */ + for (i = 0; i < LAN_SAA9730_BUFFERS; i++) { + for (j = 0; j < LAN_SAA9730_TXM_Q_SIZE; j++) { + *(unsigned int *) Pa = + cpu_to_le32(TXSF_EMPTY << + TX_STAT_CTL_OWNER_SHF); + lp->TxmBuffer[i][j] = (unsigned int) Pa; + Pa += TxmBufferSize; + } + } + + /* + * Set rx buffer A and rx buffer B to point to the first two buffer + * spaces. + */ + OUTL(PHYSADDR(lp->RcvBuffer[0][0]), + &lp->lan_saa9730_regs->RxBuffA); + OUTL(PHYSADDR(lp->RcvBuffer[1][0]), + &lp->lan_saa9730_regs->RxBuffB); + + /* Initialize Buffer Index */ + lp->NextRcvPacketIndex = 0; + lp->NextRcvToUseIsA = 1; + + /* Set current buffer index & next availble packet index */ + lp->NextTxmPacketIndex = 0; + lp->NextTxmBufferIndex = 0; + lp->PendingTxmPacketIndex = 0; + lp->PendingTxmBufferIndex = 0; + + /* + * Set txm_buf_a and txm_buf_b to point to the first two buffer + * space + */ + OUTL(PHYSADDR(lp->TxmBuffer[0][0]), + &lp->lan_saa9730_regs->TxBuffA); + OUTL(PHYSADDR(lp->TxmBuffer[1][0]), + &lp->lan_saa9730_regs->TxBuffB); + + /* Set packet number */ + OUTL((lp->DmaRcvPackets << PK_COUNT_RX_A_SHF) | + (lp->DmaRcvPackets << PK_COUNT_RX_B_SHF) | + (lp->DmaTxmPackets << PK_COUNT_TX_A_SHF) | + (lp->DmaTxmPackets << PK_COUNT_TX_B_SHF), + &lp->lan_saa9730_regs->PacketCount); + + return 0; +} + +static int lan_saa9730_cam_load(struct lan_saa9730_private *lp) +{ + unsigned int i; + unsigned char *NetworkAddress; + + NetworkAddress = (unsigned char *) &lp->PhysicalAddress[0][0]; + + for (i = 0; i < LAN_SAA9730_CAM_DWORDS; i++) { + /* First set address to where data is written */ + OUTL(i, &lp->lan_saa9730_regs->CamAddress); + OUTL((NetworkAddress[0] << 24) | (NetworkAddress[1] << 16) + | (NetworkAddress[2] << 8) | NetworkAddress[3], + &lp->lan_saa9730_regs->CamData); + NetworkAddress += 4; + } + return 0; +} + +static int lan_saa9730_cam_init(struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + unsigned int i; + + /* Copy MAC-address into all entries. */ + for (i = 0; i < LAN_SAA9730_CAM_ENTRIES; i++) { + memcpy((unsigned char *) lp->PhysicalAddress[i], + (unsigned char *) dev->dev_addr, 6); + } + + return 0; +} + +static int lan_saa9730_mii_init(struct lan_saa9730_private *lp) +{ + int i, l; + + /* Check link status, spin here till station is not busy. */ + i = 0; + while (INL(&lp->lan_saa9730_regs->StationMgmtCtl) & MD_CA_BUSY) { + i++; + if (i > 100) { + printk("Error: lan_saa9730_mii_init: timeout\n"); + return -1; + } + udelay(1000); /* wait 1 ms. */ + } + + /* Now set the control and address register. */ + OUTL(MD_CA_BUSY | PHY_STATUS | PHY_ADDRESS << MD_CA_PHY_SHF, + &lp->lan_saa9730_regs->StationMgmtCtl); + + /* check link status, spin here till station is not busy */ + i = 0; + while (INL(&lp->lan_saa9730_regs->StationMgmtCtl) & MD_CA_BUSY) { + i++; + if (i > 100) { + printk("Error: lan_saa9730_mii_init: timeout\n"); + return -1; + } + udelay(1000); /* wait 1 ms. */ + } + + /* Wait for 1 ms. */ + udelay(1000); + + /* Check the link status. */ + if (INL(&lp->lan_saa9730_regs->StationMgmtData) & + PHY_STATUS_LINK_UP) { + /* Link is up. */ + return 0; + } else { + /* Link is down, reset the PHY first. */ + + /* set PHY address = 'CONTROL' */ + OUTL(PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR | PHY_CONTROL, + &lp->lan_saa9730_regs->StationMgmtCtl); + + /* Wait for 1 ms. */ + udelay(1000); + + /* set 'CONTROL' = force reset and renegotiate */ + OUTL(PHY_CONTROL_RESET | PHY_CONTROL_AUTO_NEG | + PHY_CONTROL_RESTART_AUTO_NEG, + &lp->lan_saa9730_regs->StationMgmtData); + + /* Wait for 50 ms. */ + udelay(50 * 1000); + + /* set 'BUSY' to start operation */ + OUTL(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF | MD_CA_WR | + PHY_CONTROL, &lp->lan_saa9730_regs->StationMgmtCtl); + + /* await completion */ + i = 0; + while (INL(&lp->lan_saa9730_regs->StationMgmtCtl) & + MD_CA_BUSY) { + i++; + if (i > 100) { + printk + ("Error: lan_saa9730_mii_init: timeout\n"); + return -1; + } + udelay(1000); /* wait 1 ms. */ + } + + /* Wait for 1 ms. */ + udelay(1000); + + for (l = 0; l < 2; l++) { + /* set PHY address = 'STATUS' */ + OUTL(MD_CA_BUSY | PHY_ADDRESS << MD_CA_PHY_SHF | + PHY_STATUS, + &lp->lan_saa9730_regs->StationMgmtCtl); + + /* await completion */ + i = 0; + while (INL(&lp->lan_saa9730_regs->StationMgmtCtl) & + MD_CA_BUSY) { + i++; + if (i > 100) { + printk + ("Error: lan_saa9730_mii_init: timeout\n"); + return -1; + } + udelay(1000); /* wait 1 ms. */ + } + + /* wait for 3 sec. */ + udelay(3000 * 1000); + + /* check the link status */ + if (INL(&lp->lan_saa9730_regs->StationMgmtData) & + PHY_STATUS_LINK_UP) { + /* link is up */ + break; + } + } + } + + return 0; +} + +static int lan_saa9730_control_init(struct lan_saa9730_private *lp) +{ + /* Initialize DMA control register. */ + OUTL((LANMB_ANY << DMA_CTL_MAX_XFER_SHF) | + (LANEND_LITTLE << DMA_CTL_ENDIAN_SHF) | + (LAN_SAA9730_RCV_Q_INT_THRESHOLD << DMA_CTL_RX_INT_COUNT_SHF) + | DMA_CTL_RX_INT_TO_EN | DMA_CTL_RX_INT_EN | + DMA_CTL_MAC_RX_INT_EN | DMA_CTL_MAC_TX_INT_EN, + &lp->lan_saa9730_regs->LanDmaCtl); + + /* Initial MAC control register. */ + OUTL((MACCM_MII << MAC_CONTROL_CONN_SHF) | MAC_CONTROL_FULL_DUP, + &lp->lan_saa9730_regs->MacCtl); + + /* Initialize CAM control register. */ + OUTL(CAM_CONTROL_COMP_EN | CAM_CONTROL_BROAD_ACC, + &lp->lan_saa9730_regs->CamCtl); + + /* + * Initialize CAM enable register, only turn on first entry, should + * contain own addr. + */ + OUTL(0x0001, &lp->lan_saa9730_regs->CamEnable); + + /* Initialize Tx control register */ + OUTL(TX_CTL_EN_COMP, &lp->lan_saa9730_regs->TxCtl); + + /* Initialize Rcv control register */ + OUTL(RX_CTL_STRIP_CRC, &lp->lan_saa9730_regs->RxCtl); + + /* Reset DMA engine */ + OUTL(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest); + + return 0; +} + +static int lan_saa9730_stop(struct lan_saa9730_private *lp) +{ + int i; + + /* Stop DMA first */ + OUTL(INL(&lp->lan_saa9730_regs->LanDmaCtl) & + ~(DMA_CTL_EN_TX_DMA | DMA_CTL_EN_RX_DMA), + &lp->lan_saa9730_regs->LanDmaCtl); + + /* Set the SW Reset bits in DMA and MAC control registers */ + OUTL(DMA_TEST_SW_RESET, &lp->lan_saa9730_regs->DmaTest); + OUTL(INL(&lp->lan_saa9730_regs->MacCtl) | MAC_CONTROL_RESET, + &lp->lan_saa9730_regs->MacCtl); + + /* + * Wait for MAC reset to have finished. The reset bit is auto cleared + * when the reset is done. + */ + i = 0; + while (INL(&lp->lan_saa9730_regs->MacCtl) & MAC_CONTROL_RESET) { + i++; + if (i > 100) { + printk + ("Error: lan_sa9730_stop: MAC reset timeout\n"); + return -1; + } + udelay(1000); /* wait 1 ms. */ + } + + return 0; +} + +static int lan_saa9730_dma_init(struct lan_saa9730_private *lp) +{ + /* Stop lan controller. */ + lan_saa9730_stop(lp); + + OUTL(LAN_SAA9730_DEFAULT_TIME_OUT_CNT, + &lp->lan_saa9730_regs->Timeout); + + return 0; +} + +static int lan_saa9730_start(struct lan_saa9730_private *lp) +{ + lan_saa9730_buffer_init(lp); + + /* Initialize Rx Buffer Index */ + lp->NextRcvPacketIndex = 0; + lp->NextRcvToUseIsA = 1; + + /* Set current buffer index & next availble packet index */ + lp->NextTxmPacketIndex = 0; + lp->NextTxmBufferIndex = 0; + lp->PendingTxmPacketIndex = 0; + lp->PendingTxmBufferIndex = 0; + + OUTL(INL(&lp->lan_saa9730_regs->LanDmaCtl) | DMA_CTL_EN_TX_DMA | + DMA_CTL_EN_RX_DMA, &lp->lan_saa9730_regs->LanDmaCtl); + + /* For Tx, turn on MAC then DMA */ + OUTL(INL(&lp->lan_saa9730_regs->TxCtl) | TX_CTL_TX_EN, + &lp->lan_saa9730_regs->TxCtl); + + /* For Rx, turn on DMA then MAC */ + OUTL(INL(&lp->lan_saa9730_regs->RxCtl) | RX_CTL_RX_EN, + &lp->lan_saa9730_regs->RxCtl); + + /* Set Ok2Use to let hardware owns the buffers */ + OUTL(OK2USE_RX_A | OK2USE_RX_B | OK2USE_TX_A | OK2USE_TX_B, + &lp->lan_saa9730_regs->Ok2Use); + + return 0; +} + +static int lan_saa9730_restart(struct lan_saa9730_private *lp) +{ + lan_saa9730_stop(lp); + lan_saa9730_start(lp); + + return 0; +} + +static int lan_saa9730_tx(struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + unsigned int *pPacket; + unsigned int tx_status; + + if (lan_saa9730_debug > 5) + printk("lan_saa9730_tx interrupt\n"); + + /* Clear interrupt. */ + OUTL(DMA_STATUS_MAC_TX_INT, &lp->lan_saa9730_regs->DmaStatus); + + while (1) { + pPacket = + (unsigned int *) lp->TxmBuffer[lp-> + PendingTxmBufferIndex] + [lp->PendingTxmPacketIndex]; + + /* Get status of first packet transmitted. */ + tx_status = le32_to_cpu(*pPacket); + + /* Check ownership. */ + if ((tx_status & TX_STAT_CTL_OWNER_MSK) != + (TXSF_HWDONE << TX_STAT_CTL_OWNER_SHF)) break; + + /* Check for error. */ + if (tx_status & TX_STAT_CTL_ERROR_MSK) { + if (lan_saa9730_debug > 1) + printk("lan_saa9730_tx: tx error = %x\n", + tx_status); + + lp->stats.tx_errors++; + if (tx_status & + (TX_STATUS_EX_COLL << TX_STAT_CTL_STATUS_SHF)) + lp->stats.tx_aborted_errors++; + if (tx_status & + (TX_STATUS_LATE_COLL << + TX_STAT_CTL_STATUS_SHF)) lp->stats. + tx_window_errors++; + if (tx_status & + (TX_STATUS_L_CARR << TX_STAT_CTL_STATUS_SHF)) + lp->stats.tx_carrier_errors++; + if (tx_status & + (TX_STATUS_UNDER << TX_STAT_CTL_STATUS_SHF)) + lp->stats.tx_fifo_errors++; + if (tx_status & + (TX_STATUS_SQ_ERR << TX_STAT_CTL_STATUS_SHF)) + lp->stats.tx_heartbeat_errors++; + + lp->stats.collisions += + tx_status & TX_STATUS_TX_COLL_MSK; + } + + /* Free buffer. */ + *pPacket = + cpu_to_le32(TXSF_EMPTY << TX_STAT_CTL_OWNER_SHF); + + /* Update pending index pointer. */ + lp->PendingTxmPacketIndex++; + if (lp->PendingTxmPacketIndex >= LAN_SAA9730_TXM_Q_SIZE) { + lp->PendingTxmPacketIndex = 0; + lp->PendingTxmBufferIndex ^= 1; + } + } + + /* Make sure A and B are available to hardware. */ + OUTL(OK2USE_TX_A | OK2USE_TX_B, &lp->lan_saa9730_regs->Ok2Use); + + if (netif_queue_stopped(dev)) { + /* The tx buffer is no longer full. */ + netif_wake_queue(dev); + } + + return 0; +} + +static int lan_saa9730_rx(struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + int len = 0; + struct sk_buff *skb = 0; + unsigned int rx_status; + int BufferIndex; + int PacketIndex; + unsigned int *pPacket; + unsigned char *pData; + + if (lan_saa9730_debug > 5) + printk("lan_saa9730_rx interrupt\n"); + + /* Clear receive interrupts. */ + OUTL(DMA_STATUS_MAC_RX_INT | DMA_STATUS_RX_INT | + DMA_STATUS_RX_TO_INT, &lp->lan_saa9730_regs->DmaStatus); + + /* Address next packet */ + if (lp->NextRcvToUseIsA) + BufferIndex = 0; + else + BufferIndex = 1; + PacketIndex = lp->NextRcvPacketIndex; + pPacket = (unsigned int *) lp->RcvBuffer[BufferIndex][PacketIndex]; + rx_status = le32_to_cpu(*pPacket); + + /* Process each packet. */ + while ((rx_status & RX_STAT_CTL_OWNER_MSK) == + (RXSF_HWDONE << RX_STAT_CTL_OWNER_SHF)) { + /* Check the rx status. */ + if (rx_status & (RX_STATUS_GOOD << RX_STAT_CTL_STATUS_SHF)) { + /* Received packet is good. */ + len = (rx_status & RX_STAT_CTL_LENGTH_MSK) >> + RX_STAT_CTL_LENGTH_SHF; + + pData = (unsigned char *) pPacket; + pData += 4; + skb = dev_alloc_skb(len + 2); + if (skb == 0) { + printk + ("%s: Memory squeeze, deferring packet.\n", + dev->name); + lp->stats.rx_dropped++; + } else { + lp->stats.rx_bytes += len; + lp->stats.rx_packets++; + skb->dev = dev; + skb_reserve(skb, 2); /* 16 byte align */ + skb_put(skb, len); /* make room */ + eth_copy_and_sum(skb, + (unsigned char *) pData, + len, 0); + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + } + } else { + /* We got an error packet. */ + if (lan_saa9730_debug > 2) + printk + ("lan_saa9730_rx: We got an error packet = %x\n", + rx_status); + + lp->stats.rx_errors++; + if (rx_status & + (RX_STATUS_CRC_ERR << RX_STAT_CTL_STATUS_SHF)) + lp->stats.rx_crc_errors++; + if (rx_status & + (RX_STATUS_ALIGN_ERR << + RX_STAT_CTL_STATUS_SHF)) lp->stats. + rx_frame_errors++; + if (rx_status & + (RX_STATUS_OVERFLOW << RX_STAT_CTL_STATUS_SHF)) + lp->stats.rx_fifo_errors++; + if (rx_status & + (RX_STATUS_LONG_ERR << RX_STAT_CTL_STATUS_SHF)) + lp->stats.rx_length_errors++; + } + + /* Indicate we have processed the buffer. */ + *pPacket = + cpu_to_le32(RXSF_READY << RX_STAT_CTL_OWNER_SHF); + + /* Go to next packet in sequence. */ + lp->NextRcvPacketIndex++; + if (lp->NextRcvPacketIndex >= LAN_SAA9730_RCV_Q_SIZE) { + lp->NextRcvPacketIndex = 0; + if (BufferIndex) { + lp->NextRcvToUseIsA = 1; + } else { + lp->NextRcvToUseIsA = 0; + } + } + OUTL(OK2USE_RX_A | OK2USE_RX_B, + &lp->lan_saa9730_regs->Ok2Use); + + /* Address next packet */ + if (lp->NextRcvToUseIsA) + BufferIndex = 0; + else + BufferIndex = 1; + PacketIndex = lp->NextRcvPacketIndex; + pPacket = + (unsigned int *) lp-> + RcvBuffer[BufferIndex][PacketIndex]; + rx_status = le32_to_cpu(*pPacket); + } + + /* Make sure A and B are available to hardware. */ + OUTL(OK2USE_RX_A | OK2USE_RX_B, &lp->lan_saa9730_regs->Ok2Use); + + return 0; +} + +static void lan_saa9730_interrupt(const int irq, void *dev_id, + struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + + if (lan_saa9730_debug > 5) + printk("lan_saa9730_interrupt\n"); + + /* Disable the EVM LAN interrupt. */ + evm_saa9730_block_lan_int(lp); + + /* Clear the EVM LAN interrupt. */ + evm_saa9730_clear_lan_int(lp); + + /* Service pending transmit interrupts. */ + if (INL(&lp->lan_saa9730_regs->DmaStatus) & DMA_STATUS_MAC_TX_INT) + lan_saa9730_tx(dev); + + /* Service pending receive interrupts. */ + if (INL(&lp->lan_saa9730_regs->DmaStatus) & + (DMA_STATUS_MAC_RX_INT | DMA_STATUS_RX_INT | + DMA_STATUS_RX_TO_INT)) lan_saa9730_rx(dev); + + /* Enable the EVM LAN interrupt. */ + evm_saa9730_unblock_lan_int(lp); + + return; +} + +static int lan_saa9730_open_fail(struct net_device *dev) +{ + return -ENODEV; +} + +static int lan_saa9730_open(struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + + /* Associate IRQ with lan_saa9730_interrupt */ + if (request_irq(dev->irq, &lan_saa9730_interrupt, 0, "SAA9730 Eth", + dev)) { + printk("lan_saa9730_open: Can't get irq %d\n", dev->irq); + return -EAGAIN; + } + + /* Enable the Lan interrupt in the event manager. */ + evm_saa9730_enable_lan_int(lp); + + /* Start the LAN controller */ + if (lan_saa9730_start(lp)) + return -1; + + netif_start_queue(dev); + + return 0; +} + +static int lan_saa9730_write(struct lan_saa9730_private *lp, + struct sk_buff *skb, int skblen) +{ + unsigned char *pbData = skb->data; + unsigned int len = skblen; + unsigned char *pbPacketData; + unsigned int tx_status; + int BufferIndex; + int PacketIndex; + + if (lan_saa9730_debug > 5) + printk("lan_saa9730_write: skb=%08x\n", + (unsigned int) skb); + + BufferIndex = lp->NextTxmBufferIndex; + PacketIndex = lp->NextTxmPacketIndex; + + tx_status = + le32_to_cpu(*(unsigned int *) lp-> + TxmBuffer[BufferIndex][PacketIndex]); + if ((tx_status & TX_STAT_CTL_OWNER_MSK) != + (TXSF_EMPTY << TX_STAT_CTL_OWNER_SHF)) { + if (lan_saa9730_debug > 4) + printk + ("lan_saa9730_write: Tx buffer not available: tx_status = %x\n", + tx_status); + return -1; + } + + lp->NextTxmPacketIndex++; + if (lp->NextTxmPacketIndex >= LAN_SAA9730_TXM_Q_SIZE) { + lp->NextTxmPacketIndex = 0; + lp->NextTxmBufferIndex ^= 1; + } + + pbPacketData = + (unsigned char *) lp->TxmBuffer[BufferIndex][PacketIndex]; + pbPacketData += 4; + + /* copy the bits */ + memcpy(pbPacketData, pbData, len); + + /* Set transmit status for hardware */ + *(unsigned int *) lp->TxmBuffer[BufferIndex][PacketIndex] = + cpu_to_le32((TXSF_READY << TX_STAT_CTL_OWNER_SHF) | + (TX_STAT_CTL_INT_AFTER_TX << TX_STAT_CTL_FRAME_SHF) + | (len << TX_STAT_CTL_LENGTH_SHF)); + + /* Set hardware tx buffer. */ + OUTL(OK2USE_TX_A | OK2USE_TX_B, &lp->lan_saa9730_regs->Ok2Use); + + return 0; +} + +static void lan_saa9730_tx_timeout(struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + + /* Transmitter timeout, serious problems */ + lp->stats.tx_errors++; + printk("%s: transmit timed out, reset\n", dev->name); + /*show_saa9730_regs(lp); */ + lan_saa9730_restart(lp); + + dev->trans_start = jiffies; + netif_start_queue(dev); +} + +static int lan_saa9730_start_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + unsigned long flags; + int skblen; + int len; + + if (lan_saa9730_debug > 4) + printk("Send packet: skb=%08x\n", (unsigned int) skb); + + skblen = skb->len; + save_and_cli(flags); + len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen; + + if (lan_saa9730_write(lp, skb, skblen)) { + restore_flags(flags); + printk + ("Error when writing packet to controller: skb=%08x\n", + (unsigned int) skb); + netif_stop_queue(dev); + return -1; + } + + lp->stats.tx_bytes += len; + lp->stats.tx_packets++; + + dev->trans_start = jiffies; + netif_start_queue(dev); + dev_kfree_skb(skb); + + restore_flags(flags); + + return 0; +} + +static int lan_saa9730_close(struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + + if (lan_saa9730_debug > 1) + printk("lan_saa9730_close:\n"); + + netif_stop_queue(dev); + + /* Disable the Lan interrupt in the event manager. */ + evm_saa9730_disable_lan_int(lp); + + /* Stop the controller */ + if (lan_saa9730_stop(lp)) + return -1; + + free_irq(dev->irq, (void *) dev); + + return 0; +} + +static struct net_device_stats *lan_saa9730_get_stats(struct net_device + *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + + return &lp->stats; +} + +static void lan_saa9730_set_multicast(struct net_device *dev) +{ + struct lan_saa9730_private *lp = + (struct lan_saa9730_private *) dev->priv; + + /* Stop the controller */ + lan_saa9730_stop(lp); + + if (dev->flags & IFF_PROMISC) { + /* accept all packets */ + OUTL(CAM_CONTROL_COMP_EN | CAM_CONTROL_STATION_ACC | + CAM_CONTROL_GROUP_ACC | CAM_CONTROL_BROAD_ACC, + &lp->lan_saa9730_regs->CamCtl); + } else { + if (dev->flags & IFF_ALLMULTI) { + /* accept all multicast packets */ + OUTL(CAM_CONTROL_COMP_EN | CAM_CONTROL_GROUP_ACC | + CAM_CONTROL_BROAD_ACC, + &lp->lan_saa9730_regs->CamCtl); + } else { + /* + * Will handle the multicast stuff later. -carstenl + */ + } + } + + lan_saa9730_restart(lp); +} + +static int lan_saa9730_init(struct net_device *dev, int ioaddr, int irq) +{ + struct lan_saa9730_private *lp; + unsigned char ethernet_addr[6]; + + dev = init_etherdev(dev, 0); + + dev->open = lan_saa9730_open_fail; + if (get_ethernet_addr(ethernet_addr)) + return -1; + + memcpy(dev->dev_addr, ethernet_addr, 6); + dev->base_addr = ioaddr; + dev->irq = irq; + + /* + * Make certain the data structures used by the controller are aligned + * and DMAble. + */ + lp = (struct lan_saa9730_private *) (((unsigned long) + kmalloc(sizeof(*lp) + 7, + GFP_DMA | GFP_KERNEL) + + 7) & ~7); + + dev->priv = lp; + memset(lp, 0, sizeof(*lp)); + + /* Set SAA9730 LAN base address. */ + lp->lan_saa9730_regs = (t_lan_saa9730_regmap *) (ioaddr + + SAA9730_LAN_REGS_ADDR); + + /* Set SAA9730 EVM base address. */ + lp->evm_saa9730_regs = (t_evm_saa9730_regmap *) (ioaddr + + SAA9730_EVM_REGS_ADDR); +#ifdef CONFIG_REMOTE_DEBUG + if (saa9730_kgdb_active) + saa9730_kgdb_setup((t_uart_saa9730_regmap *) (ioaddr + + + SAA9730_UART_REGS_ADDR)); +#endif + /* Allocate LAN RX/TX frame buffer space. */ + if (lan_saa9730_allocate_buffers(lp)) + return -1; + + /* Stop LAN controller. */ + if (lan_saa9730_stop(lp)) + return -1; + + /* Initialize CAM registers. */ + if (lan_saa9730_cam_init(dev)) + return -1; + + /* Initialize MII registers. */ + if (lan_saa9730_mii_init(lp)) + return -1; + + /* Initialize control registers. */ + if (lan_saa9730_control_init(lp)) + return -1; + + /* Load CAM registers. */ + if (lan_saa9730_cam_load(lp)) + return -1; + + /* Initialize DMA context registers. */ + if (lan_saa9730_dma_init(lp)) + return -1; + + dev->open = lan_saa9730_open; + dev->hard_start_xmit = lan_saa9730_start_xmit; + dev->stop = lan_saa9730_close; + dev->get_stats = lan_saa9730_get_stats; + dev->set_multicast_list = lan_saa9730_set_multicast; + dev->tx_timeout = lan_saa9730_tx_timeout; + dev->watchdog_timeo = (HZ >> 1); + dev->dma = 0; + + return 0; +} + + +static int __init saa9730_probe(void) +{ + struct net_device *dev = NULL; + + if (pci_present()) { + struct pci_dev *pdev = NULL; + if (lan_saa9730_debug > 1) + printk + ("saa9730.c: PCI bios is present, checking for devices...\n"); + + while ((pdev = pci_find_device(PCI_VENDOR_ID_PHILIPS, + PCI_DEVICE_ID_PHILIPS_SAA9730, + pdev))) { + unsigned int pci_ioaddr; + + pci_irq_line = pdev->irq; + /* LAN base address in located at BAR 1. */ + + pci_ioaddr = pci_resource_start(pdev, 1); + pci_set_master(pdev); + + printk("Found SAA9730 (PCI) at %#x, irq %d.\n", + pci_ioaddr, pci_irq_line); + if (!lan_saa9730_init + (dev, pci_ioaddr, pci_irq_line)) return 0; + else + printk("Lan init failed.\n"); + } + } + + return -ENODEV; +} + +module_init(saa9730_probe); diff --git a/drivers/net/saa9730.h b/drivers/net/saa9730.h new file mode 100644 index 000000000..cad254386 --- /dev/null +++ b/drivers/net/saa9730.h @@ -0,0 +1,410 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * SAA9730 ethernet driver description. + * + */ +#ifndef _SAA9730_H +#define _SAA9730_H + + +/* Number of 6-byte entries in the CAM. */ +#define LAN_SAA9730_CAM_ENTRIES 10 +#define LAN_SAA9730_CAM_DWORDS ((LAN_SAA9730_CAM_ENTRIES*6)/4) + +/* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */ +#define LAN_SAA9730_PACKET_SIZE 2048 + +/* + * Number of TX buffers = number of RX buffers = 2, which is fixed according + * to HW requirements. + */ +#define LAN_SAA9730_BUFFERS 2 + +/* Number of RX packets per RX buffer. */ +#define LAN_SAA9730_RCV_Q_SIZE 15 + +/* Number of TX packets per TX buffer. */ +#define LAN_SAA9730_TXM_Q_SIZE 15 + +/* + * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD + * packets received. + * If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD + * packets, the hardware can timeout after a certain time and still tell + * us packets have arrived. + * The timeout value in unit of 32 PCI clocks (33Mhz). + * The value 200 approximates 0.0002 seconds. + */ +#define LAN_SAA9730_RCV_Q_INT_THRESHOLD 1 +#define LAN_SAA9730_DEFAULT_TIME_OUT_CNT 10 + +#define RXSF_NDIS 0 +#define RXSF_READY 2 +#define RXSF_HWDONE 3 + +#define TXSF_EMPTY 0 +#define TXSF_READY 2 +#define TXSF_HWDONE 3 + +#define LANEND_LITTLE 0 +#define LANEND_BIG_2143 1 +#define LANEND_BIG_4321 2 + +#define LANMB_ANY 0 +#define LANMB_8 1 +#define LANMB_32 2 +#define LANMB_64 3 + +#define MACCM_AUTOMATIC 0 +#define MACCM_10MB 1 +#define MACCM_MII 2 + +/* + * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board) + */ +#define PHY_CONTROL 0x0 +#define PHY_STATUS 0x1 +#define PHY_STATUS_LINK_UP 0x4 +#define PHY_CONTROL_RESET 0x8000 +#define PHY_CONTROL_AUTO_NEG 0x1000 +#define PHY_CONTROL_RESTART_AUTO_NEG 0x0200 +#define PHY_ADDRESS 0x0 + +/* PK_COUNT register. */ +#define PK_COUNT_TX_A_SHF 24 +#define PK_COUNT_TX_A_MSK (0xff << PK_COUNT_TX_A_SHF) +#define PK_COUNT_TX_B_SHF 16 +#define PK_COUNT_TX_B_MSK (0xff << PK_COUNT_TX_B_SHF) +#define PK_COUNT_RX_A_SHF 8 +#define PK_COUNT_RX_A_MSK (0xff << PK_COUNT_RX_A_SHF) +#define PK_COUNT_RX_B_SHF 0 +#define PK_COUNT_RX_B_MSK (0xff << PK_COUNT_RX_B_SHF) + +/* OK2USE register. */ +#define OK2USE_TX_A 0x8 +#define OK2USE_TX_B 0x4 +#define OK2USE_RX_A 0x2 +#define OK2USE_RX_B 0x1 + +/* LAN DMA CONTROL register. */ +#define DMA_CTL_BLK_INT 0x80000000 +#define DMA_CTL_MAX_XFER_SHF 18 +#define DMA_CTL_MAX_XFER_MSK (0x3 << LAN_DMA_CTL_MAX_XFER_SHF) +#define DMA_CTL_ENDIAN_SHF 16 +#define DMA_CTL_ENDIAN_MSK (0x3 << LAN_DMA_CTL_ENDIAN_SHF) +#define DMA_CTL_RX_INT_COUNT_SHF 8 +#define DMA_CTL_RX_INT_COUNT_MSK (0xff << LAN_DMA_CTL_RX_INT_COUNT_SHF) +#define DMA_CTL_EN_TX_DMA 0x00000080 +#define DMA_CTL_EN_RX_DMA 0x00000040 +#define DMA_CTL_RX_INT_BUFFUL_EN 0x00000020 +#define DMA_CTL_RX_INT_TO_EN 0x00000010 +#define DMA_CTL_RX_INT_EN 0x00000008 +#define DMA_CTL_TX_INT_EN 0x00000004 +#define DMA_CTL_MAC_TX_INT_EN 0x00000002 +#define DMA_CTL_MAC_RX_INT_EN 0x00000001 + +/* DMA STATUS register. */ +#define DMA_STATUS_BAD_ADDR_SHF 16 +#define DMA_STATUS_BAD_ADDR_MSK (0xf << DMA_STATUS_BAD_ADDR_SHF) +#define DMA_STATUS_RX_PKTS_RECEIVED_SHF 8 +#define DMA_STATUS_RX_PKTS_RECEIVED_MSK (0xff << DMA_STATUS_RX_PKTS_RECEIVED_SHF) +#define DMA_STATUS_TX_EN_SYNC 0x00000080 +#define DMA_STATUS_RX_BUF_A_FUL 0x00000040 +#define DMA_STATUS_RX_BUF_B_FUL 0x00000020 +#define DMA_STATUS_RX_TO_INT 0x00000010 +#define DMA_STATUS_RX_INT 0x00000008 +#define DMA_STATUS_TX_INT 0x00000004 +#define DMA_STATUS_MAC_TX_INT 0x00000002 +#define DMA_STATUS_MAC_RX_INT 0x00000001 + +/* DMA TEST/PANIC SWITHES register. */ +#define DMA_TEST_LOOPBACK 0x01000000 +#define DMA_TEST_SW_RESET 0x00000001 + +/* MAC CONTROL register. */ +#define MAC_CONTROL_EN_MISS_ROLL 0x00002000 +#define MAC_CONTROL_MISS_ROLL 0x00000400 +#define MAC_CONTROL_LOOP10 0x00000080 +#define MAC_CONTROL_CONN_SHF 5 +#define MAC_CONTROL_CONN_MSK (0x3 << MAC_CONTROL_CONN_SHF) +#define MAC_CONTROL_MAC_LOOP 0x00000010 +#define MAC_CONTROL_FULL_DUP 0x00000008 +#define MAC_CONTROL_RESET 0x00000004 +#define MAC_CONTROL_HALT_IMM 0x00000002 +#define MAC_CONTROL_HALT_REQ 0x00000001 + +/* CAM CONTROL register. */ +#define CAM_CONTROL_COMP_EN 0x00000010 +#define CAM_CONTROL_NEG_CAM 0x00000008 +#define CAM_CONTROL_BROAD_ACC 0x00000004 +#define CAM_CONTROL_GROUP_ACC 0x00000002 +#define CAM_CONTROL_STATION_ACC 0x00000001 + +/* TRANSMIT CONTROL register. */ +#define TX_CTL_EN_COMP 0x00004000 +#define TX_CTL_EN_TX_PAR 0x00002000 +#define TX_CTL_EN_LATE_COLL 0x00001000 +#define TX_CTL_EN_EX_COLL 0x00000800 +#define TX_CTL_EN_L_CARR 0x00000400 +#define TX_CTL_EN_EX_DEFER 0x00000200 +#define TX_CTL_EN_UNDER 0x00000100 +#define TX_CTL_MII10 0x00000080 +#define TX_CTL_SD_PAUSE 0x00000040 +#define TX_CTL_NO_EX_DEF0 0x00000020 +#define TX_CTL_F_BACK 0x00000010 +#define TX_CTL_NO_CRC 0x00000008 +#define TX_CTL_NO_PAD 0x00000004 +#define TX_CTL_TX_HALT 0x00000002 +#define TX_CTL_TX_EN 0x00000001 + +/* TRANSMIT STATUS register. */ +#define TX_STATUS_SQ_ERR 0x00010000 +#define TX_STATUS_TX_HALTED 0x00008000 +#define TX_STATUS_COMP 0x00004000 +#define TX_STATUS_TX_PAR 0x00002000 +#define TX_STATUS_LATE_COLL 0x00001000 +#define TX_STATUS_TX10_STAT 0x00000800 +#define TX_STATUS_L_CARR 0x00000400 +#define TX_STATUS_EX_DEFER 0x00000200 +#define TX_STATUS_UNDER 0x00000100 +#define TX_STATUS_IN_TX 0x00000080 +#define TX_STATUS_PAUSED 0x00000040 +#define TX_STATUS_TX_DEFERRED 0x00000020 +#define TX_STATUS_EX_COLL 0x00000010 +#define TX_STATUS_TX_COLL_SHF 0 +#define TX_STATUS_TX_COLL_MSK (0xf << TX_STATUS_TX_COLL_SHF) + +/* RECEIVE CONTROL register. */ +#define RX_CTL_EN_GOOD 0x00004000 +#define RX_CTL_EN_RX_PAR 0x00002000 +#define RX_CTL_EN_LONG_ERR 0x00000800 +#define RX_CTL_EN_OVER 0x00000400 +#define RX_CTL_EN_CRC_ERR 0x00000200 +#define RX_CTL_EN_ALIGN 0x00000100 +#define RX_CTL_IGNORE_CRC 0x00000040 +#define RX_CTL_PASS_CTL 0x00000020 +#define RX_CTL_STRIP_CRC 0x00000010 +#define RX_CTL_SHORT_EN 0x00000008 +#define RX_CTL_LONG_EN 0x00000004 +#define RX_CTL_RX_HALT 0x00000002 +#define RX_CTL_RX_EN 0x00000001 + +/* RECEIVE STATUS register. */ +#define RX_STATUS_RX_HALTED 0x00008000 +#define RX_STATUS_GOOD 0x00004000 +#define RX_STATUS_RX_PAR 0x00002000 +#define RX_STATUS_LONG_ERR 0x00000800 +#define RX_STATUS_OVERFLOW 0x00000400 +#define RX_STATUS_CRC_ERR 0x00000200 +#define RX_STATUS_ALIGN_ERR 0x00000100 +#define RX_STATUS_RX10_STAT 0x00000080 +#define RX_STATUS_INT_RX 0x00000040 +#define RX_STATUS_CTL_RECD 0x00000020 + +/* MD_CA register. */ +#define MD_CA_PRE_SUP 0x00001000 +#define MD_CA_BUSY 0x00000800 +#define MD_CA_WR 0x00000400 +#define MD_CA_PHY_SHF 5 +#define MD_CA_PHY_MSK (0x1f << MD_CA_PHY_SHF) +#define MD_CA_ADDR_SHF 0 +#define MD_CA_ADDR_MSK (0x1f << MD_CA_ADDR_SHF) + +/* Tx Status/Control. */ +#define TX_STAT_CTL_OWNER_SHF 30 +#define TX_STAT_CTL_OWNER_MSK (0x3 << TX_STAT_CTL_OWNER_SHF) +#define TX_STAT_CTL_FRAME_SHF 27 +#define TX_STAT_CTL_FRAME_MSK (0x7 << TX_STAT_CTL_FRAME_SHF) +#define TX_STAT_CTL_STATUS_SHF 11 +#define TX_STAT_CTL_STATUS_MSK (0x1ffff << TX_STAT_CTL_STATUS_SHF) +#define TX_STAT_CTL_LENGTH_SHF 0 +#define TX_STAT_CTL_LENGTH_MSK (0x7ff << TX_STAT_CTL_LENGTH_SHF) + +#define TX_STAT_CTL_ERROR_MSK ((TX_STATUS_SQ_ERR | \ + TX_STATUS_TX_HALTED | \ + TX_STATUS_TX_PAR | \ + TX_STATUS_LATE_COLL | \ + TX_STATUS_L_CARR | \ + TX_STATUS_EX_DEFER | \ + TX_STATUS_UNDER | \ + TX_STATUS_PAUSED | \ + TX_STATUS_TX_DEFERRED | \ + TX_STATUS_EX_COLL | \ + TX_STATUS_TX_COLL_MSK) \ + << TX_STAT_CTL_STATUS_SHF) +#define TX_STAT_CTL_INT_AFTER_TX 0x4 + +/* Rx Status/Control. */ +#define RX_STAT_CTL_OWNER_SHF 30 +#define RX_STAT_CTL_OWNER_MSK (0x3 << RX_STAT_CTL_OWNER_SHF) +#define RX_STAT_CTL_STATUS_SHF 11 +#define RX_STAT_CTL_STATUS_MSK (0xffff << RX_STAT_CTL_STATUS_SHF) +#define RX_STAT_CTL_LENGTH_SHF 0 +#define RX_STAT_CTL_LENGTH_MSK (0x7ff << RX_STAT_CTL_LENGTH_SHF) + + + +/* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */ +#define SAA9730_LAN_REGS_ADDR 0x20400 + +struct lan_saa9730_regmap { + volatile unsigned int TxBuffA; /* 0x20400 */ + volatile unsigned int TxBuffB; /* 0x20404 */ + volatile unsigned int RxBuffA; /* 0x20408 */ + volatile unsigned int RxBuffB; /* 0x2040c */ + volatile unsigned int PacketCount; /* 0x20410 */ + volatile unsigned int Ok2Use; /* 0x20414 */ + volatile unsigned int LanDmaCtl; /* 0x20418 */ + volatile unsigned int Timeout; /* 0x2041c */ + volatile unsigned int DmaStatus; /* 0x20420 */ + volatile unsigned int DmaTest; /* 0x20424 */ + volatile unsigned char filler20428[0x20430 - 0x20428]; + volatile unsigned int PauseCount; /* 0x20430 */ + volatile unsigned int RemotePauseCount; /* 0x20434 */ + volatile unsigned char filler20438[0x20440 - 0x20438]; + volatile unsigned int MacCtl; /* 0x20440 */ + volatile unsigned int CamCtl; /* 0x20444 */ + volatile unsigned int TxCtl; /* 0x20448 */ + volatile unsigned int TxStatus; /* 0x2044c */ + volatile unsigned int RxCtl; /* 0x20450 */ + volatile unsigned int RxStatus; /* 0x20454 */ + volatile unsigned int StationMgmtData; /* 0x20458 */ + volatile unsigned int StationMgmtCtl; /* 0x2045c */ + volatile unsigned int CamAddress; /* 0x20460 */ + volatile unsigned int CamData; /* 0x20464 */ + volatile unsigned int CamEnable; /* 0x20468 */ + volatile unsigned char filler2046c[0x20500 - 0x2046c]; + volatile unsigned int DebugPCIMasterAddr; /* 0x20500 */ + volatile unsigned int DebugLanTxStateMachine; /* 0x20504 */ + volatile unsigned int DebugLanRxStateMachine; /* 0x20508 */ + volatile unsigned int DebugLanTxFifoPointers; /* 0x2050c */ + volatile unsigned int DebugLanRxFifoPointers; /* 0x20510 */ + volatile unsigned int DebugLanCtlStateMachine; /* 0x20514 */ +}; +typedef volatile struct lan_saa9730_regmap t_lan_saa9730_regmap; + + +/* EVM interrupt control registers. */ +#define EVM_LAN_INT 0x00010000 +#define EVM_MASTER_EN 0x00000001 + +/* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */ +#define SAA9730_EVM_REGS_ADDR 0x02000 + +struct evm_saa9730_regmap { + volatile unsigned int InterruptStatus1; /* 0x2000 */ + volatile unsigned int InterruptEnable1; /* 0x2004 */ + volatile unsigned int InterruptMonitor1; /* 0x2008 */ + volatile unsigned int Counter; /* 0x200c */ + volatile unsigned int CounterThreshold; /* 0x2010 */ + volatile unsigned int CounterControl; /* 0x2014 */ + volatile unsigned int GpioControl1; /* 0x2018 */ + volatile unsigned int InterruptStatus2; /* 0x201c */ + volatile unsigned int InterruptEnable2; /* 0x2020 */ + volatile unsigned int InterruptMonitor2; /* 0x2024 */ + volatile unsigned int GpioControl2; /* 0x2028 */ + volatile unsigned int InterruptBlock1; /* 0x202c */ + volatile unsigned int InterruptBlock2; /* 0x2030 */ +}; +typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap; + + +/* The SAA9730 UART register map, as seen via the PCI bus */ + +#define SAA9730_UART_REGS_ADDR 0x21800 + +struct uart_saa9730_regmap { + volatile unsigned char Thr_Rbr; + volatile unsigned char Ier; + volatile unsigned char Iir_Fcr; + volatile unsigned char Lcr; + volatile unsigned char Mcr; + volatile unsigned char Lsr; + volatile unsigned char Msr; + volatile unsigned char Scr; + volatile unsigned char BaudDivLsb; + volatile unsigned char BaudDivMsb; + volatile unsigned char Junk0; + volatile unsigned char Junk1; + volatile unsigned int Config; /* 0x2180c */ + volatile unsigned int TxStart; /* 0x21810 */ + volatile unsigned int TxLength; /* 0x21814 */ + volatile unsigned int TxCounter; /* 0x21818 */ + volatile unsigned int RxStart; /* 0x2181c */ + volatile unsigned int RxLength; /* 0x21820 */ + volatile unsigned int RxCounter; /* 0x21824 */ +}; +typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap; + +/* + * Only a subset of the UART control bits are defined here, + * enough to make the serial debug port work. + */ + +#define SAA9730_LCR_DATA8 0x03 + +#define SAA9730_MCR_DTR 0x01 +#define SAA9730_MCR_RTS 0x02 + +#define SAA9730_LSR_DR 0x01 +#define SAA9730_LSR_THRE 0x20 + +struct lan_saa9730_private { + /* Pointer for the SAA9730 LAN controller register set. */ + t_lan_saa9730_regmap *lan_saa9730_regs; + + /* Pointer to the SAA9730 EVM register. */ + t_evm_saa9730_regmap *evm_saa9730_regs; + + /* TRUE if the next buffer to write is RxBuffA, FALSE if RxBuffB. */ + unsigned char NextRcvToUseIsA; + /* Rcv buffer Index. */ + unsigned char NextRcvPacketIndex; + + /* Index of next packet to use in that buffer. */ + unsigned char NextTxmPacketIndex; + /* Next buffer index. */ + unsigned char NextTxmBufferIndex; + + /* Index of first pending packet ready to send. */ + unsigned char PendingTxmPacketIndex; + /* Pending buffer index. */ + unsigned char PendingTxmBufferIndex; + + unsigned char DmaRcvPackets; + unsigned char DmaTxmPackets; + + unsigned char RcvAIndex; /* index into RcvBufferSpace[] for Blk A */ + unsigned char RcvBIndex; /* index into RcvBufferSpace[] for Blk B */ + + unsigned int + TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE]; + unsigned int + RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE]; + unsigned int TxBufferFree[LAN_SAA9730_BUFFERS]; + + unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6]; + + struct net_device_stats stats; +}; + +#endif /* _SAA9730_H */ |