diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ide/.cvsignore | 2 | ||||
| -rw-r--r-- | drivers/isdn/isdnloop/.cvsignore | 2 | ||||
| -rw-r--r-- | drivers/isdn/sc/.cvsignore | 2 | ||||
| -rw-r--r-- | drivers/scsi/Makefile | 4 | ||||
| -rw-r--r-- | drivers/scsi/hosts.c | 4 | ||||
| -rw-r--r-- | drivers/video/aty128.h | 2 | ||||
| -rw-r--r-- | drivers/video/nv4ref.h | 2445 | ||||
| -rw-r--r-- | drivers/video/nvreg.h | 188 | ||||
| -rw-r--r-- | drivers/video/riva_hw.c | 1429 | ||||
| -rw-r--r-- | drivers/video/riva_hw.h | 343 | ||||
| -rw-r--r-- | drivers/video/riva_tbl.h | 402 | ||||
| -rw-r--r-- | drivers/video/rivafb.c | 1891 | ||||
| -rw-r--r-- | drivers/video/vga_font.c | 1 |
13 files changed, 12 insertions, 6703 deletions
diff --git a/drivers/ide/.cvsignore b/drivers/ide/.cvsignore new file mode 100644 index 000000000..857dd22e9 --- /dev/null +++ b/drivers/ide/.cvsignore @@ -0,0 +1,2 @@ +.depend +.*.flags diff --git a/drivers/isdn/isdnloop/.cvsignore b/drivers/isdn/isdnloop/.cvsignore new file mode 100644 index 000000000..857dd22e9 --- /dev/null +++ b/drivers/isdn/isdnloop/.cvsignore @@ -0,0 +1,2 @@ +.depend +.*.flags diff --git a/drivers/isdn/sc/.cvsignore b/drivers/isdn/sc/.cvsignore new file mode 100644 index 000000000..857dd22e9 --- /dev/null +++ b/drivers/isdn/sc/.cvsignore @@ -0,0 +1,2 @@ +.depend +.*.flags diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index 9081a6d13..74644cccf 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -461,10 +461,10 @@ else endif ifeq ($(CONFIG_SCSI_SUNESP),y) -L_OBJS += esp.o sparc_esp.o +L_OBJS += esp.o else ifeq ($(CONFIG_SCSI_SUNESP),m) - M_OBJS += esp.o sparc_esp.o + M_OBJS += esp.o endif endif diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index 321b783a5..b626d3fdd 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -266,7 +266,7 @@ #endif #ifdef CONFIG_SCSI_SUNESP -#include "sparc_esp.h" +#include "esp.h" #endif #ifdef CONFIG_SCSI_SGIWD93 @@ -650,7 +650,7 @@ static Scsi_Host_Template builtin_scsi_hosts[] = SCSI_DEC_ESP, #endif #ifdef CONFIG_BLK_DEV_3W_XXXX_RAID - TWXXXX, + TWXXXX, #endif /* "Removable host adapters" below this line (Parallel Port/USB/other) */ #ifdef CONFIG_SCSI_PPA diff --git a/drivers/video/aty128.h b/drivers/video/aty128.h index d934d0c2d..7b1452bf6 100644 --- a/drivers/video/aty128.h +++ b/drivers/video/aty128.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $ * linux/drivers/video/aty128.h * Register definitions for ATI Rage128 boards * diff --git a/drivers/video/nv4ref.h b/drivers/video/nv4ref.h deleted file mode 100644 index ffcb4445d..000000000 --- a/drivers/video/nv4ref.h +++ /dev/null @@ -1,2445 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 - */ - - /***************************************************************************\ -|* Modified 1999 by Fredrik Reite (fredrik@reite.com) *| - \***************************************************************************/ - - -#ifndef __NV4REF_H__ -#define __NV4REF_H__ - -/* Magic values to lock/unlock extended regs */ -#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */ -#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */ -#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */ -#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */ - -#define UNLOCK_EXT_MAGIC 0x57 -#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ - -#define LOCK_EXT_INDEX 0x6 - -#define NV_PCRTC_HORIZ_TOTAL 0x00 -#define NV_PCRTC_HORIZ_DISPLAY_END 0x01 -#define NV_PCRTC_HORIZ_BLANK_START 0x02 - -#define NV_PCRTC_HORIZ_BLANK_END 0x03 -#define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7 -#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5 -#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0 - -#define NV_PCRTC_HORIZ_RETRACE_START 0x04 - -#define NV_PCRTC_HORIZ_RETRACE_END 0x05 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0 - -#define NV_PCRTC_VERT_TOTAL 0x06 - -#define NV_PCRTC_OVERFLOW 0x07 -#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7 -#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6 -#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5 -#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4 -#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3 -#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2 -#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1 -#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0 - -#define NV_PCRTC_PRESET_ROW_SCAN 0x08 - -#define NV_PCRTC_MAX_SCAN_LINE 0x09 -#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7 -#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6 -#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5 -#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0 - -#define NV_PCRTC_CURSOR_START 0x0A -#define NV_PCRTC_CURSOR_END 0x0B -#define NV_PCRTC_START_ADDR_HIGH 0x0C -#define NV_PCRTC_START_ADDR_LOW 0x0D -#define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E -#define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F - -#define NV_PCRTC_VERT_RETRACE_START 0x10 -#define NV_PCRTC_VERT_RETRACE_END 0x11 -#define NV_PCRTC_VERT_DISPLAY_END 0x12 -#define NV_PCRTC_OFFSET 0x13 -#define NV_PCRTC_UNDERLINE_LOCATION 0x14 -#define NV_PCRTC_VERT_BLANK_START 0x15 -#define NV_PCRTC_VERT_BLANK_END 0x16 -#define NV_PCRTC_MODE_CONTROL 0x17 -#define NV_PCRTC_LINE_COMPARE 0x18 - -/* Extended offset and start address */ -#define NV_PCRTC_REPAINT0 0x19 -#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 -#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 - -/* Horizonal extended bits */ -#define NV_PCRTC_HORIZ_EXTRA 0x2d -#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 -#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 -#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 -#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 -#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 - -/* Assorted extra bits */ -#define NV_PCRTC_EXTRA 0x25 -#define NV_PCRTC_EXTRA_OFFSET_11 5:5 -#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 -#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 -#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 -#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 -#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 - -/* Controls how much data the refresh fifo requests */ -#define NV_PCRTC_FIFO_CONTROL 0x1b -#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 - -/* When the fifo occupancy falls below *twice* the watermark, - * the refresh fifo will start to be refilled. If this value is - * too low, you will get junk on the screen. Too high, and performance - * will suffer. Watermark in units of 8 bytes - */ -#define NV_PCRTC_FIFO 0x20 -#define NV_PCRTC_FIFO_RESET 7:7 -#define NV_PCRTC_FIFO_WATERMARK 5:0 - -/* Various flags */ -#define NV_PCRTC_REPAINT1 0x1a -#define NV_PCRTC_REPAINT1_HSYNC 7:7 -#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 -#define NV_PCRTC_REPAINT1_VSYNC 6:6 -#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 - -#define NV_PCRTC_GRCURSOR0 0x30 -#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 - -#define NV_PCRTC_GRCURSOR1 0x31 -#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 -#define NV_PCRTC_GRCURSOR1_CURSOR 0:0 -#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 -#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 - -/* Controls what the format of the framebuffer is */ -#define NV_PCRTC_PIXEL 0x28 -#define NV_PCRTC_PIXEL_MODE 7:7 -#define NV_PCRTC_PIXEL_MODE_TV 0x01 -#define NV_PCRTC_PIXEL_MODE_VGA 0x00 -#define NV_PCRTC_PIXEL_TV_MODE 6:6 -#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 -#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 -#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 -#define NV_PCRTC_PIXEL_FORMAT 1:0 -#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 -#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 -#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 -#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 - -/* RAMDAC registers and fields */ -#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ -#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ -#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ -#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ -#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */ -#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */ -#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ -#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ -#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ - -/* Master Control */ -#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ -#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ -#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */ -#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */ -#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */ -#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */ -#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */ -#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */ -#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */ -#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */ -#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */ -#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */ -#define NV_PMC_INTR_0 0x00000100 /* RW-4R */ -#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ -#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ -#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */ -#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ -#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ -#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */ -#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ -#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ -#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ -#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ -#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ -#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ -#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ -#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */ -#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */ -#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */ -#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */ -#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ -#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */ -#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ -#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ -#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */ -#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */ -#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */ -#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */ -#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */ -#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */ -#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */ -#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */ -#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */ - -/* dev_timer.ref */ -#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */ -#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */ -#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */ -#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */ -#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */ -#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */ -#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */ -#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */ -#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */ -#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */ -#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */ -#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */ -#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */ -#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */ -#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */ -#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */ -#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */ -#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */ -#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */ - -/* dev_fifo.ref */ -#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ -#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */ -#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */ -#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ -#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ -#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */ -#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */ -#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */ -#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */ -#define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */ -#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */ -#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */ -#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ -#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ -#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */ -#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ -#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */ -#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */ -#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */ -#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ -#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */ -#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */ -#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ -#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */ -#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */ -#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */ -#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */ -#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ -#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ -#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */ -#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_MODE 0x00002504 /* RW-4R */ -#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA 0x00002508 /* RW-4R */ -#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */ -#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ -#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ -#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */ -#define NV_PFIFO_CACHE0_PUSH1_CHID 3:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */ -#define NV_PFIFO_CACHE1_PUSH1_CHID 3:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */ -#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 19:16 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 28:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_GET_OFFSET 28:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:30 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 28:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 /* RWXUF */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */ -#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ -#define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */ -#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */ -#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */ -#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */ -#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */ -#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ -#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */ -#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */ -#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */ -#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */ -#define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */ -#define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */ -#define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */ -#define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */ -#define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */ -#define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */ -#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */ -#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */ -#define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */ -#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */ -#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */ -#define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */ -#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */ -#define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */ -#define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */ -#define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */ -#define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */ -#define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ -#define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */ -#define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */ -#define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */ -#define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */ -#define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */ -#define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */ -#define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */ -#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */ -#define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */ -#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */ -#define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */ -#define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */ -#define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */ -#define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */ -#define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */ -#define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */ -#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */ -#define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */ -#define NV_PFIFO_DEVICE__SIZE_1 128 /* */ -#define NV_PFIFO_DEVICE_CHID 3:0 /* R--UF */ -#define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */ -#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ -#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */ -#define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */ -#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */ -#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */ -#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ -#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ -#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ -#define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */ -#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */ -#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */ -#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ -#define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */ -/* dev_graphics.ref */ -#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */ -#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ -#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ -#define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ -#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */ -#define NV_PGRAPH_INTR 0x00400100 /* RW-4R */ -#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */ -#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */ -#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A 8:8 /* RWIVF */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B 9:9 /* RWIVF */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */ -#define NV_PGRAPH_NSTATUS_STATE_IN_USE 11:11 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSTATUS_INVALID_STATE 12:12 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 13:13 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 14:14 /* RWIVF */ -#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */ -#define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_ 5:5 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */ -#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */ -#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A 8:8 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B 9:9 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */ -#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1 0x00400160 /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */ -#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25:25 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x00000000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */ -#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */ -#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */ -#define NV_PGRAPH_CTX_SWITCH2 0x00400164 /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH3 0x00400168 /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_SWITCH4 0x0040016C /* RW-4R */ -#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */ -#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */ -#define NV_PGRAPH_CTX_CACHE1(i) (0x00400180+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_SPARE1 20:20 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25:25 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE2(i) (0x004001a0+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE3(i) (0x004001c0+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */ -#define NV_PGRAPH_CTX_CACHE4(i) (0x004001e0+(i)*4) /* RW-4A */ -#define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */ -#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */ -#define NV_PGRAPH_CTX_CONTROL 0x00400170 /* RW-4R */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */ -#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */ -#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */ -#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ -#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ -#define NV_PGRAPH_CTX_USER 0x00400174 /* RW-4R */ -#define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */ -#define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_CTX_USER_CHID 27:24 /* RWIVF */ -#define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */ -#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */ -#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */ -#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x00400730+(i)*4) /* RW-4A */ -#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 4 /* */ -#define NV_PGRAPH_FFINTFC_FIFO_0_TAG 0:0 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x00000000 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 3:1 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 14:4 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */ -#define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x00400740+(i)*4) /* RW-4A */ -#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 4 /* */ -#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400750 /* RW-4R */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 2:0 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 6:4 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2 0x00400754 /* RW-4R */ -#define NV_PGRAPH_FFINTFC_ST2_STATUS 0:0 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_MTHD 11:1 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH 14:12 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID 18:15 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 19:19 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_FFINTFC_ST2_D 0x00400758 /* RW-4R */ -#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT 31:0 /* RWIVF */ -#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */ -#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */ -#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */ -#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_FE 5:5 /* R-IVF */ -#define NV_PGRAPH_STATUS_FE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_FE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_RASTERIZER 6:6 /* R-IVF */ -#define NV_PGRAPH_STATUS_RASTERIZER_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_RASTERIZER_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */ -#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */ -#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */ -#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_D3D 24:24 /* R-IVF */ -#define NV_PGRAPH_STATUS_D3D_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_D3D_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_CACHE 25:25 /* R-IVF */ -#define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_LIGHTING 26:26 /* R-IVF */ -#define NV_PGRAPH_STATUS_LIGHTING_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_LIGHTING_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PREROP 27:27 /* R-IVF */ -#define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_ROP 28:28 /* R-IVF */ -#define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_STATUS_PORT_USER 29:29 /* R-IVF */ -#define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */ -#define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */ -#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */ -#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */ -#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 15:13 /* R-XUF */ -#define NV_PGRAPH_TRAPPED_ADDR_CHID 27:24 /* R-XUF */ -#define NV_PGRAPH_TRAPPED_DATA 0x00400708 /* R--4R */ -#define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */ -#define NV_PGRAPH_SURFACE 0x0040070C /* RW-4R */ -#define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */ -#define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */ -#define NV_PGRAPH_NOTIFY 0x00400714 /* RW-4R */ -#define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ -#define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */ -#define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */ -#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ -#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ -#define NV_PGRAPH_BOFFSET(i) (0x00400640+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */ -#define NV_PGRAPH_BOFFSET_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET0 0x00400640 /* RW-4R */ -#define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */ -#define NV_PGRAPH_BOFFSET0_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET1 0x00400644 /* RW-4R */ -#define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */ -#define NV_PGRAPH_BOFFSET1_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET2 0x00400648 /* RW-4R */ -#define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */ -#define NV_PGRAPH_BOFFSET2_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET3 0x0040064C /* RW-4R */ -#define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */ -#define NV_PGRAPH_BOFFSET3_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET4 0x00400650 /* RW-4R */ -#define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */ -#define NV_PGRAPH_BOFFSET4_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BOFFSET5 0x00400654 /* RW-4R */ -#define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */ -#define NV_PGRAPH_BOFFSET5_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE(i) (0x00400658+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BBASE__SIZE_1 6 /* */ -#define NV_PGRAPH_BBASE_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE0 0x00400658 /* RW-4R */ -#define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */ -#define NV_PGRAPH_BBASE0_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE1 0x0040065c /* RW-4R */ -#define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */ -#define NV_PGRAPH_BBASE1_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE2 0x00400660 /* RW-4R */ -#define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */ -#define NV_PGRAPH_BBASE2_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE3 0x00400664 /* RW-4R */ -#define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */ -#define NV_PGRAPH_BBASE3_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE4 0x00400668 /* RW-4R */ -#define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */ -#define NV_PGRAPH_BBASE4_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BBASE5 0x0040066C /* RW-4R */ -#define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */ -#define NV_PGRAPH_BBASE5_LINADRS 23:0 /* RWIUF */ -#define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH(i) (0x00400670+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BPITCH__SIZE_1 5 /* */ -#define NV_PGRAPH_BPITCH_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH0 0x00400670 /* RW-4R */ -#define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */ -#define NV_PGRAPH_BPITCH0_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH1 0x00400674 /* RW-4R */ -#define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */ -#define NV_PGRAPH_BPITCH1_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH2 0x00400678 /* RW-4R */ -#define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */ -#define NV_PGRAPH_BPITCH2_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH3 0x0040067C /* RW-4R */ -#define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */ -#define NV_PGRAPH_BPITCH3_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPITCH4 0x00400680 /* RW-4R */ -#define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */ -#define NV_PGRAPH_BPITCH4_VALUE 12:0 /* RWIUF */ -#define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BLIMIT(i) (0x00400684+(i)*4) /* RW-4A */ -#define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */ -#define NV_PGRAPH_BLIMIT_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT0 0x00400684 /* RW-4R */ -#define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */ -#define NV_PGRAPH_BLIMIT0_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT1 0x00400688 /* RW-4R */ -#define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */ -#define NV_PGRAPH_BLIMIT1_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT2 0x0040068c /* RW-4R */ -#define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */ -#define NV_PGRAPH_BLIMIT2_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT3 0x00400690 /* RW-4R */ -#define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */ -#define NV_PGRAPH_BLIMIT3_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT4 0x00400694 /* RW-4R */ -#define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */ -#define NV_PGRAPH_BLIMIT4_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BLIMIT5 0x00400698 /* RW-4R */ -#define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */ -#define NV_PGRAPH_BLIMIT5_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */ -#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */ -#define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE2 0x0040069c /* RW-4R */ -#define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE5 0x004006a0 /* RW-4R */ -#define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */ -#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */ -#define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */ -#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 /* RW-4R */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 23:0 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT 29:29 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30:30 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31:31 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_Z 0x00400614 /* RW-4R */ -#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 23:0 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT 30:30 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31:31 /* RWIVF */ -#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE 0x00400710 /* RW-4R */ -#define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */ -#define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */ -#define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */ -#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */ -#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */ -#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */ -#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */ -#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */ -#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX 0x00400728 /* RW-4R */ -#define NV_PGRAPH_CACHE_INDEX_BANK 2:2 /* RWXVF */ -#define NV_PGRAPH_CACHE_INDEX_BANK_10 0x00000000 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_BANK_32 0x00000001 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_ADRS 12:3 /* RWXVF */ -#define NV_PGRAPH_CACHE_INDEX_ADRS_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_ADRS_1024 0x00000400 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_OP 14:13 /* RWXVF */ -#define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x00000000 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x00000001 /* RW--V */ -#define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x00000002 /* RW--V */ -#define NV_PGRAPH_CACHE_RAM 0x0040072c /* RW-4R */ -#define NV_PGRAPH_CACHE_RAM_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DMA_PITCH 0x00400760 /* RW-4R */ -#define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */ -#define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */ -#define NV_PGRAPH_DVD_COLORFMT 0x00400764 /* RW-4R */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 /* RW--V */ -#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */ -#define NV_PGRAPH_SCALED_FORMAT 0x00400768 /* RW-4R */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */ -#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */ -#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */ -#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */ -#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */ -#define NV_PGRAPH_PATT_COLOR0 0x00400800 /* RW-4R */ -#define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PATT_COLOR1 0x00400804 /* RW-4R */ -#define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PATT_COLORRAM(i) (0x00400900+(i)*4) /* R--4A */ -#define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */ -#define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* R--UF */ -#define NV_PGRAPH_PATTERN(i) (0x00400808+(i)*4) /* RW-4A */ -#define NV_PGRAPH_PATTERN__SIZE_1 2 /* */ -#define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */ -#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 /* RW-4R */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */ -#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */ -#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */ -#define NV_PGRAPH_MONO_COLOR0 0x00400600 /* RW-4R */ -#define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_ROP3 0x00400604 /* RW-4R */ -#define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */ -#define NV_PGRAPH_CHROMA 0x00400814 /* RW-4R */ -#define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_BETA_AND 0x00400608 /* RW-4R */ -#define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */ -#define NV_PGRAPH_BETA_PREMULT 0x0040060c /* RW-4R */ -#define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_CONTROL0 0x00400818 /* RW-4R */ -#define NV_PGRAPH_CONTROL1 0x0040081c /* RW-4R */ -#define NV_PGRAPH_CONTROL2 0x00400820 /* RW-4R */ -#define NV_PGRAPH_BLEND 0x00400824 /* RW-4R */ -#define NV_PGRAPH_DPRAM_INDEX 0x00400828 /* RW-4R */ -#define NV_PGRAPH_DPRAM_INDEX_ADRS 6:0 /* RWIVF */ -#define NV_PGRAPH_DPRAM_INDEX_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT 10:8 /* RWIVF */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x00000001 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x00000002 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x00000003 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x00000004 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x00000005 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x00000006 /* RW--V */ -#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x00000007 /* RW--V */ -#define NV_PGRAPH_DPRAM_DATA 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_DATA_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ADRS_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ADRS_0_VALUE 19:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ADRS_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ADRS_1_VALUE 19:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_DATA_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_DATA_0_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_DATA_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_DATA_1_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_WE_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_WE_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_WE_0_VALUE 23:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_WE_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_WE_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_WE_1_VALUE 23:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ALPHA_0 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ALPHA_0_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_DPRAM_ALPHA_1 0x0040082c /* RW-4R */ -#define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ -#define NV_PGRAPH_DPRAM_ALPHA_1_VALUE 31:0 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT 0x00400830 /* RW-4R */ -#define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */ -#define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */ -#define NV_PGRAPH_FORMATS 0x00400618 /* RW-4R */ -#define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */ -#define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_INVALID 0x00000004 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_RGB30 0x00000006 /* -W--V */ -#define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* -W--V */ -#define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */ -#define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* RW--V */ -#define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */ -#define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* RWI-V */ -#define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* RW--V */ -#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* RW--V */ -#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ -#define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */ -#define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */ -#define NV_PGRAPH_X_RAM_BPORT__SIZE_1 32 /* */ -#define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */ -#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ -#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */ -#define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */ -#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 32 /* */ -#define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */ -#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */ -#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */ -#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */ -#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */ -#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */ -#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */ -#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */ -#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */ -#define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */ -#define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */ -#define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ -#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ -#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */ -#define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */ -#define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ -#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ -#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */ -#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */ -#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */ -#define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */ -#define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */ -#define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */ -#define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */ -#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */ -#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */ -#define NV_PGRAPH_VALID2 0x00400578 /* RW-4R */ -#define NV_PGRAPH_VALID2_VLD2 28:0 /* RWNVF */ -#define NV_PGRAPH_VALID2_VLD2_0 0x00000000 /* RWN-V */ -#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */ -#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */ -#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */ -#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ -#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ -#define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */ -#define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */ -#define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */ -#define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */ -#define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */ -#define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */ -#define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */ -#define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_U_RAM(i) (0x00400d00+(i)*4) /* RW-4A */ -#define NV_PGRAPH_U_RAM__SIZE_1 16 /* */ -#define NV_PGRAPH_U_RAM_VALUE 31:6 /* RWXFF */ -#define NV_PGRAPH_V_RAM(i) (0x00400d40+(i)*4) /* RW-4A */ -#define NV_PGRAPH_V_RAM__SIZE_1 16 /* */ -#define NV_PGRAPH_V_RAM_VALUE 31:6 /* RWXFF */ -#define NV_PGRAPH_M_RAM(i) (0x00400d80+(i)*4) /* RW-4A */ -#define NV_PGRAPH_M_RAM__SIZE_1 16 /* */ -#define NV_PGRAPH_M_RAM_VALUE 31:6 /* RWXFF */ -#define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */ -#define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */ -#define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */ -#define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */ -#define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */ -#define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */ -#define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */ -#define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */ -#define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */ -#define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */ -#define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */ -#define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */ -#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */ -#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */ -#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */ -#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */ -#define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */ -#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */ -#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */ -#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */ -#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ -#define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */ -#define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */ -#define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */ -#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */ -#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */ -#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */ -#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */ -#define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */ -#define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */ -#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */ -#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */ -#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ -#define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */ -#define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */ -#define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */ -#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */ -#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ -#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ -#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */ -#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */ -#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */ -#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */ -#define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */ -#define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */ -#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */ -#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */ - -/* Framebuffer registers */ -#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ -#define NV_PFB_BOOT_0 0x00100000 /* RW-4R */ -#define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RW-VF */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_WIDTH_128 2:2 /* RW-VF */ -#define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x00000000 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_WIDTH_128_ON 0x00000001 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE 4:3 /* RW-VF */ -#define NV_PFB_BOOT_0_RAM_TYPE_256K 0x00000000 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x00000001 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x00000002 /* RW--V */ -#define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x00000003 /* RW--V */ -#define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */ -#define NV_PFB_CONFIG_0_TYPE 14:0 /* RWIVF */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x00000120 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x00000220 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x00000320 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x00004120 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x00004220 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x00004320 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_TETRIS 0x00002000 /* RW--V */ -#define NV_PFB_CONFIG_0_TYPE_NOTILING 0x00001114 /* RWI-V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE 17:15 /* RWI-F */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_PASS 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_1 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_2 0x00000002 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_3 0x00000003 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_4 0x00000004 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_5 0x00000005 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_6 0x00000006 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_MODE_7 0x00000007 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT 19:18 /* RWI-F */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT_0 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT_1 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_TETRIS_SHIFT_2 0x00000002 /* RW--V */ -#define NV_PFB_CONFIG_0_BANK_SWAP 22:20 /* RWI-F */ -#define NV_PFB_CONFIG_0_BANK_SWAP_OFF 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_BANK_SWAP_1M 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_BANK_SWAP_2M 0x00000005 /* RW--V */ -#define NV_PFB_CONFIG_0_BANK_SWAP_4M 0x00000007 /* RW--V */ -#define NV_PFB_CONFIG_0_UNUSED 23:23 /* RW-VF */ -#define NV_PFB_CONFIG_0_SCRAMBLE_EN 29:29 /* RWIVF */ -#define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x00000000 /* RW--V */ -#define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR 28:28 /* RWIVF */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_INIT 0x00000000 /* RW--V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK 27:24 /* RWIVF */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0x0000000f /* RWI-V */ -#define NV_PFB_CONFIG_1 0x00100204 /* RW-4R */ -#define NV_PFB_RTL 0x00100300 /* RW-4R */ -#define NV_PFB_RTL_H 0:0 /* RWIUF */ -#define NV_PFB_RTL_H_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_MC 1:1 /* RWIUF */ -#define NV_PFB_RTL_MC_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_V 2:2 /* RWIUF */ -#define NV_PFB_RTL_V_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_G 3:3 /* RWIUF */ -#define NV_PFB_RTL_G_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_RTL_GB 4:4 /* RWIUF */ -#define NV_PFB_RTL_GB_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */ -#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */ -#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */ -#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */ -#define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */ -#define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */ -#define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */ -#define NV_PFB_CONFIG_1_SGRAM100 3:3 /* RWIVF */ -#define NV_PFB_CONFIG_1_SGRAM100_ENABLED 0x00000000 /* RWI-V */ -#define NV_PFB_CONFIG_1_SGRAM100_DISABLED 0x00000001 /* RW--V */ -#define NV_PFB_DEBUG_0_CKE_ALWAYSON 29:29 /* RWIVF */ -#define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x00000000 /* RW--V */ -#define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x00000001 /* RWI-V */ - -#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */ -#define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0:0 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 3:2 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x00000003 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4:4 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5:5 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* R-XVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* R---V */ -#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11:11 /* RWIVF */ -#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */ -#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */ - -/* Extras */ -#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */ -/*#define NV_PRAMIN 0x00FFFFFF:0x00C00000*/ -#define NV_PNVM 0x01FFFFFF:0x01000000 /* RW--M */ -/*#define NV_PNVM 0x00BFFFFF:0x00800000*/ -#define NV_CHAN0 0x0080ffff:0x00800000 - -/* FIFO subchannels */ -#define NV_UROP 0x43 -#define NV_UCHROMA 0x57 -#define NV_UCLIP 0x19 -#define NV_UPATT 0x18 -#define NV_ULIN 0x5C -#define NV_UTRI 0x5D -#define NV_URECT 0x5E -#define NV_UBLIT 0x5F -#define NV_UGLYPH 0x4B - -#endif /*__NV4REF_H__*/ - diff --git a/drivers/video/nvreg.h b/drivers/video/nvreg.h deleted file mode 100644 index abfc167ae..000000000 --- a/drivers/video/nvreg.h +++ /dev/null @@ -1,188 +0,0 @@ -/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ -/* - * Copyright 1996-1997 David J. McKay - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */ - -#ifndef __NVREG_H_ -#define __NVREG_H_ - -/* Little macro to construct bitmask for contiguous ranges of bits */ -#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) -#define MASKEXPAND(mask) BITMASK(1?mask,0?mask) - -/* Macro to set specific bitfields (mask has to be a macro x:y) ! */ -#define SetBF(mask,value) ((value) << (0?mask)) -#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) - -#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ - | SetBF(mask,value))) - -#define DEVICE_BASE(device) (0?NV##_##device) -#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1) - -/* This is where we will have to have conditional compilation */ -#define DEVICE_ACCESS(device,reg) \ - nvCONTROL[(NV_##device##_##reg)/4] - -#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) -#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) -#define DEVICE_PRINT(device,reg) \ - ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) -#define DEVICE_DEF(device,mask,value) \ - SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value) -#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) -#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) - -#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) -#define PDAC_Read(reg) DEVICE_READ(PDAC,reg) -#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) -#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) -#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) -#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) - -#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) -#define PFB_Read(reg) DEVICE_READ(PFB,reg) -#define PFB_Print(reg) DEVICE_PRINT(PFB,reg) -#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) -#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value) -#define PFB_Mask(mask) DEVICE_MASK(PFB,mask) - -#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value) -#define PRM_Read(reg) DEVICE_READ(PRM,reg) -#define PRM_Print(reg) DEVICE_PRINT(PRM,reg) -#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value) -#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value) -#define PRM_Mask(mask) DEVICE_MASK(PRM,mask) - -#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value) -#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg) -#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg) -#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value) -#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value) -#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask) - -#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value) -#define PDMA_Read(reg) DEVICE_READ(PDMA,reg) -#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg) -#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value) -#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value) -#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) - -#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value) -#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg) -#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg) -#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value) -#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value) -#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask) - -#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value) -#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg) -#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg) -#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value) -#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value) -#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask) - -#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value) -#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg) -#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg) -#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value) -#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value) -#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask) - -#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value) -#define PRAM_Read(reg) DEVICE_READ(PRAM,reg) -#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg) -#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value) -#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value) -#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask) - -#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value) -#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg) -#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg) -#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value) -#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value) -#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask) - -#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) -#define PMC_Read(reg) DEVICE_READ(PMC,reg) -#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) -#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) -#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) -#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) - -#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) -#define PMC_Read(reg) DEVICE_READ(PMC,reg) -#define PMC_Print(reg) DEVICE_PRINT(PMC,reg) -#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) -#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) -#define PMC_Mask(mask) DEVICE_MASK(PMC,mask) - - -#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value) -#define PBUS_Read(reg) DEVICE_READ(PBUS,reg) -#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg) -#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value) -#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value) -#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask) - - -#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value) -#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg) -#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg) -#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value) -#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value) -#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask) - - -#define PDAC_ReadExt(reg) \ - ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ - (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ - (PDAC_Read(INDEX_DATA))) - -#define PDAC_WriteExt(reg,value)\ - ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ - (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ - (PDAC_Write(INDEX_DATA,(value)))) - -#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5) -#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5)) - -#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value) -#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index) - -#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) -#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) -#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) - -#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value) -#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5)) - -extern volatile unsigned *nvCONTROL; - -typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType; - -NVChipType GetChipType(void); - -#endif - - diff --git a/drivers/video/riva_hw.c b/drivers/video/riva_hw.c deleted file mode 100644 index 2e0f1b27e..000000000 --- a/drivers/video/riva_hw.c +++ /dev/null @@ -1,1429 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.c,v 1.1.2.3 1998/12/26 00:12:39 dawes Exp $ */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <asm/io.h> -#include "riva_hw.h" -#include "riva_tbl.h" - - -/* - * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT - * operate identically (except TNT has more memory and better 3D quality. - */ - -static int nv3Busy -( - RIVA_HW_INST *chip -) -{ - return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x000006B0/4] & 0x01)); -} -static int nv4Busy -( - RIVA_HW_INST *chip -) -{ - return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x00000700/4] & 0x01)); -} -static int ShowHideCursor -( - RIVA_HW_INST *chip, - int ShowHide -) -{ - int xcurrent; - xcurrent = chip->CurrentState->cursor1; - chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | (ShowHide & 0x01); - outb(0x31, 0x3D4); - outb(chip->CurrentState->cursor1, 0x3D5); - return (xcurrent & 0x01); -} - -/****************************************************************************\ -* * -* The video arbitration routines calculate some "magic" numbers. Fixes * -* the snow seen when accessing the framebuffer without it. * -* It just works (I hope). * -* * -\****************************************************************************/ - -#define DEFAULT_GR_LWM 100 -#define DEFAULT_VID_LWM 100 -#define DEFAULT_GR_BURST_SIZE 256 -#define DEFAULT_VID_BURST_SIZE 128 -#define VIDEO 0 -#define GRAPHICS 1 -#define MPORT 2 -#define ENGINE 3 -#define GFIFO_SIZE 320 -#define GFIFO_SIZE_128 256 -#define MFIFO_SIZE 120 -#define VFIFO_SIZE 256 -#define ABS(a) (a>0?a:-a) -typedef struct { - int gdrain_rate; - int vdrain_rate; - int mdrain_rate; - int gburst_size; - int vburst_size; - char vid_en; - char gr_en; - int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; - int by_gfacc; - char vid_only_once; - char gr_only_once; - char first_vacc; - char first_gacc; - char first_macc; - int vocc; - int gocc; - int mocc; - char cur; - char engine_en; - char converged; - int priority; -} nv3_arb_info; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int graphics_hi_priority; - int media_hi_priority; - int rtl_values; - int valid; -} nv3_fifo_info; -typedef struct { - char pix_bpp; - char enable_video; - char gr_during_vid; - char enable_mp; - int memory_width; - int video_scale; - int pclk_khz; - int mclk_khz; - int mem_page_miss; - int mem_latency; - char mem_aligned; -} nv3_sim_state; -typedef struct { - int graphics_lwm; - int video_lwm; - int graphics_burst_size; - int video_burst_size; - int valid; -} nv4_fifo_info; -typedef struct { - int pclk_khz; - int mclk_khz; - int nvclk_khz; - char mem_page_miss; - char mem_latency; - int memory_width; - char enable_video; - char gr_during_vid; - char pix_bpp; - char mem_aligned; - char enable_mp; -} nv4_sim_state; -static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - int iter = 0; - int tmp, t; - int vfsize, mfsize, gfsize; - int mburst_size = 32; - int mmisses, gmisses, vmisses; - int misses; - int vlwm, glwm, mlwm; - int last, next, cur; - int max_gfsize ; - long ns; - - vlwm = 0; - glwm = 0; - mlwm = 0; - vfsize = 0; - gfsize = 0; - cur = ainfo->cur; - mmisses = 2; - gmisses = 2; - vmisses = 2; - if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; - else max_gfsize = GFIFO_SIZE; - max_gfsize = GFIFO_SIZE; - while (1) - { - if (ainfo->vid_en) - { - if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; - if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; - ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; - vfsize = ns * ainfo->vdrain_rate / 1000000; - vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; - } - if (state->enable_mp) - { - if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; - } - if (ainfo->gr_en) - { - if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; - if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; - ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; - gfsize = ns *ainfo->gdrain_rate/1000000; - gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; - } - mfsize = 0; - if (!state->gr_during_vid && ainfo->vid_en) - if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->mocc < 0) - next = MPORT; - else if (ainfo->gocc< ainfo->by_gfacc) - next = GRAPHICS; - else return (0); - else switch (ainfo->priority) - { - case VIDEO: - if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->mocc<0) - next = MPORT; - else return (0); - break; - case GRAPHICS: - if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else if (ainfo->mocc<0) - next = MPORT; - else return (0); - break; - default: - if (ainfo->mocc<0) - next = MPORT; - else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) - next = GRAPHICS; - else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) - next = VIDEO; - else return (0); - break; - } - last = cur; - cur = next; - iter++; - switch (cur) - { - case VIDEO: - if (last==cur) misses = 0; - else if (ainfo->first_vacc) misses = vmisses; - else misses = 1; - ainfo->first_vacc = 0; - if (last!=cur) - { - ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; - vlwm = ns * ainfo->vdrain_rate/ 1000000; - vlwm = ainfo->vocc - vlwm; - } - ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; - ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; - break; - case GRAPHICS: - if (last==cur) misses = 0; - else if (ainfo->first_gacc) misses = gmisses; - else misses = 1; - ainfo->first_gacc = 0; - if (last!=cur) - { - ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; - glwm = ns * ainfo->gdrain_rate/1000000; - glwm = ainfo->gocc - glwm; - } - ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; - ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; - break; - default: - if (last==cur) misses = 0; - else if (ainfo->first_macc) misses = mmisses; - else misses = 1; - ainfo->first_macc = 0; - ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; - ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; - ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; - break; - } - if (iter>100) - { - ainfo->converged = 0; - return (1); - } - ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; - tmp = ns * ainfo->gdrain_rate/1000000; - if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; - tmp = ns * ainfo->vdrain_rate/1000000; - if (ABS(ainfo->vburst_size) + (ABS(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (ABS(ainfo->gocc) > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - if (ABS(ainfo->vocc) > VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (ABS(ainfo->mocc) > MFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (ABS(vfsize) > VFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - if (ABS(gfsize) > max_gfsize) - { - ainfo->converged = 0; - return (1); - } - if (ABS(mfsize) > MFIFO_SIZE) - { - ainfo->converged = 0; - return (1); - } - } -} -static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - int g, v, not_done; - long ens, vns, mns, gns; - int mmisses, gmisses, vmisses, eburst_size, mburst_size; - int refresh_cycle; - - refresh_cycle = 0; - refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; - mmisses = 2; - if (state->mem_aligned) gmisses = 2; - else gmisses = 3; - vmisses = 2; - eburst_size = state->memory_width * 1; - mburst_size = 32; - gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; - ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; - ainfo->wcmocc = 0; - ainfo->wcgocc = 0; - ainfo->wcvocc = 0; - ainfo->wcvlwm = 0; - ainfo->wcglwm = 0; - ainfo->engine_en = 1; - ainfo->converged = 1; - if (ainfo->engine_en) - { - ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; - ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; - ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; - ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; - ainfo->cur = ENGINE; - ainfo->first_vacc = 1; - ainfo->first_gacc = 1; - ainfo->first_macc = 1; - nv3_iterate(res_info, state,ainfo); - } - if (state->enable_mp) - { - mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; - ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; - ainfo->cur = MPORT; - ainfo->first_vacc = 1; - ainfo->first_gacc = 1; - ainfo->first_macc = 0; - nv3_iterate(res_info, state,ainfo); - } - if (ainfo->gr_en) - { - ainfo->first_vacc = 1; - ainfo->first_gacc = 0; - ainfo->first_macc = 1; - gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; - ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; - ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; - ainfo->cur = GRAPHICS; - nv3_iterate(res_info, state,ainfo); - } - if (ainfo->vid_en) - { - ainfo->first_vacc = 0; - ainfo->first_gacc = 1; - ainfo->first_macc = 1; - vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; - ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; - ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; - ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; - ainfo->cur = VIDEO; - nv3_iterate(res_info, state, ainfo); - } - if (ainfo->converged) - { - res_info->graphics_lwm = (int)ABS(ainfo->wcglwm) + 16; - res_info->video_lwm = (int)ABS(ainfo->wcvlwm) + 32; - res_info->graphics_burst_size = ainfo->gburst_size; - res_info->video_burst_size = ainfo->vburst_size; - res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); - res_info->media_hi_priority = (ainfo->priority == MPORT); - if (res_info->video_lwm > 160) - { - res_info->graphics_lwm = 256; - res_info->video_lwm = 128; - res_info->graphics_burst_size = 64; - res_info->video_burst_size = 64; - res_info->graphics_hi_priority = 0; - res_info->media_hi_priority = 0; - ainfo->converged = 0; - return (0); - } - if (res_info->video_lwm > 128) - { - res_info->video_lwm = 128; - } - return (1); - } - else - { - res_info->graphics_lwm = 256; - res_info->video_lwm = 128; - res_info->graphics_burst_size = 64; - res_info->video_burst_size = 64; - res_info->graphics_hi_priority = 0; - res_info->media_hi_priority = 0; - return (0); - } -} -static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) -{ - int done, g,v, p; - int priority, gburst_size, vburst_size, iter; - - done = 0; - if (state->gr_during_vid && ainfo->vid_en) - ainfo->priority = MPORT; - else - ainfo->priority = ainfo->gdrain_rate < ainfo->vdrain_rate ? VIDEO: GRAPHICS; - for (p=0; p < 2 && done != 1; p++) - { - for (g=128 ; (g > 32) && (done != 1); g= g>> 1) - { - for (v=128; (v >=32) && (done !=1); v = v>> 1) - { - ainfo->priority = p; - ainfo->gburst_size = g; - ainfo->vburst_size = v; - done = nv3_arb(res_info, state,ainfo); - if (g==128) - { - if ((res_info->graphics_lwm + g) > 256) - done = 0; - } - } - } - } - if (!done) - return (0); - else - return (1); -} -static void nv3CalcArbitration -( - nv3_fifo_info * res_info, - nv3_sim_state * state -) -{ - nv3_fifo_info save_info; - nv3_arb_info ainfo; - char res_gr, res_vid; - - ainfo.gr_en = 1; - ainfo.vid_en = state->enable_video; - ainfo.vid_only_once = 0; - ainfo.gr_only_once = 0; - ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8; - ainfo.vdrain_rate = (int) state->pclk_khz * 2; - if (state->video_scale != 0) - ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; - ainfo.mdrain_rate = 33000; - res_info->rtl_values = 0; - if (!state->gr_during_vid && state->enable_video) - { - ainfo.gr_only_once = 1; - ainfo.gr_en = 1; - ainfo.gdrain_rate = 0; - res_vid = nv3_get_param(res_info, state, &ainfo); - res_vid = ainfo.converged; - save_info.video_lwm = res_info->video_lwm; - save_info.video_burst_size = res_info->video_burst_size; - ainfo.vid_en = 1; - ainfo.vid_only_once = 1; - ainfo.gr_en = 1; - ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8; - ainfo.vdrain_rate = 0; - res_gr = nv3_get_param(res_info, state, &ainfo); - res_gr = ainfo.converged; - res_info->video_lwm = save_info.video_lwm; - res_info->video_burst_size = save_info.video_burst_size; - res_info->valid = res_gr & res_vid; - } - else - { - if (!ainfo.gr_en) ainfo.gdrain_rate = 0; - if (!ainfo.vid_en) ainfo.vdrain_rate = 0; - res_gr = nv3_get_param(res_info, state, &ainfo); - res_info->valid = ainfo.converged; - } -} -void nv3UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv3_fifo_info fifo_data; - nv3_sim_state sim_data; - unsigned int M, N, P, pll, MClk; - - pll = chip->PRAMDAC[0x00000504/4]; - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.video_scale = 1; - sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64; - sim_data.memory_width = 128; - sim_data.mem_latency = 11; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = 9; - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - nv3CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } - else - { - *lwm = 0x24; - *burst = 0x02; - } -} -static void nv4CalcArbitration -( - nv4_fifo_info *fifo, - nv4_sim_state *arb -) -{ - int data, m,n,p, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; - int found, mclk_extra, mclk_loop, cbs, m1, p1; - int xtal_freq, mclk_freq, pclk_freq, nvclk_freq, mp_enable; - int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; - int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; - int craw, vraw; - - fifo->valid = 1; - pclk_freq = arb->pclk_khz; - mclk_freq = arb->mclk_khz; - nvclk_freq = arb->nvclk_khz; - pagemiss = arb->mem_page_miss; - cas = arb->mem_latency; - width = arb->memory_width >> 6; - video_enable = arb->enable_video; - color_key_enable = arb->gr_during_vid; - bpp = arb->pix_bpp; - align = arb->mem_aligned; - mp_enable = arb->enable_mp; - clwm = 0; - vlwm = 0; - cbs = 128; - pclks = 2; - nvclks = 2; - nvclks += 2; - nvclks += 1; - mclks = 5; - mclks += 3; - mclks += 1; - mclks += cas; - mclks += 1; - mclks += 1; - mclks += 1; - mclks += 1; - mclk_extra = 3; - nvclks += 2; - nvclks += 1; - nvclks += 1; - nvclks += 1; - if (mp_enable) - mclks+=4; - nvclks += 0; - pclks += 0; - found = 0; - while (found != 1) - { - fifo->valid = 1; - found = 1; - mclk_loop = mclks+mclk_extra; - us_m = mclk_loop *1000*1000 / mclk_freq; - us_n = nvclks*1000*1000 / nvclk_freq; - us_p = nvclks*1000*1000 / pclk_freq; - if (video_enable) - { - video_drain_rate = pclk_freq * 2; - crtc_drain_rate = pclk_freq * bpp/8; - vpagemiss = 2; - vpagemiss += 1; - crtpagemiss = 2; - vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; - else - video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; - us_video = vpm_us + us_m + us_n + us_p + video_fill_us; - vlwm = us_video * video_drain_rate/(1000*1000); - vlwm++; - vbs = 128; - if (vlwm > 128) vbs = 64; - if (vlwm > (256-64)) vbs = 32; - if (nvclk_freq * 2 > mclk_freq * width) - video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; - else - video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = - us_video - +video_fill_us - +cpm_us - +us_m + us_n +us_p - ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; - } - else - { - crtc_drain_rate = pclk_freq * bpp/8; - crtpagemiss = 2; - crtpagemiss += 1; - cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; - us_crt = cpm_us + us_m + us_n + us_p ; - clwm = us_crt * crtc_drain_rate/(1000*1000); - clwm++; - } - m1 = clwm + cbs - 512; - p1 = m1 * pclk_freq / mclk_freq; - p1 = p1 * bpp / 8; - if ((p1 < m1) && (m1 > 0)) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - else if (video_enable) - { - if ((clwm > 511) || (vlwm > 255)) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - } - else - { - if (clwm > 519) - { - fifo->valid = 0; - found = 0; - if (mclk_extra ==0) found = 1; - mclk_extra--; - } - } - craw = clwm; - vraw = vlwm; - if (clwm < 384) clwm = 384; - if (vlwm < 128) vlwm = 128; - data = (int)(clwm); - fifo->graphics_lwm = data; - fifo->graphics_burst_size = 128; - data = (int)((vlwm+15)); - fifo->video_lwm = data; - fifo->video_burst_size = vbs; - } -} -static void nv4UpdateArbitrationSettings -( - unsigned VClk, - unsigned pixelDepth, - unsigned *burst, - unsigned *lwm, - RIVA_HW_INST *chip -) -{ - nv4_fifo_info fifo_data; - nv4_sim_state sim_data; - unsigned int M, N, P, pll, MClk, NVClk, cfg1; - - pll = chip->PRAMDAC[0x00000504/4]; - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - MClk = (N * chip->CrystalFreqKHz / M) >> P; - pll = chip->PRAMDAC[0x00000500/4]; - M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; - NVClk = (N * chip->CrystalFreqKHz / M) >> P; - cfg1 = chip->PFB[0x00000204/4]; - sim_data.pix_bpp = (char)pixelDepth; - sim_data.enable_video = 0; - sim_data.enable_mp = 0; - sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64; - sim_data.mem_latency = (char)cfg1 & 0x0F; - sim_data.mem_aligned = 1; - sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); - sim_data.gr_during_vid = 0; - sim_data.pclk_khz = VClk; - sim_data.mclk_khz = MClk; - sim_data.nvclk_khz = NVClk; - nv4CalcArbitration(&fifo_data, &sim_data); - if (fifo_data.valid) - { - int b = fifo_data.graphics_burst_size >> 4; - *burst = 0; - while (b >>= 1) (*burst)++; - *lwm = fifo_data.graphics_lwm >> 3; - } -} - -/****************************************************************************\ -* * -* RIVA Mode State Routines * -* * -\****************************************************************************/ - -/* - * Calculate the Video Clock parameters for the PLL. - */ -static int CalcVClock -( - int clockIn, - int *clockOut, - int *mOut, - int *nOut, - int *pOut, - RIVA_HW_INST *chip -) -{ - unsigned lowM, highM, highP; - unsigned DeltaNew, DeltaOld; - unsigned VClk, Freq; - unsigned M, N, O, P; - - DeltaOld = 0xFFFFFFFF; - VClk = (unsigned)clockIn; - if (chip->CrystalFreqKHz == 14318) - { - lowM = 8; - highM = 14 - (chip->Architecture == 3); - } - else - { - lowM = 7; - highM = 13 - (chip->Architecture == 3); - } - highP = 4 - (chip->Architecture == 3); - for (P = 0; P <= highP; P ++) - { - Freq = VClk << P; - if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) - { - for (M = lowM; M <= highM; M++) - { - N = (VClk * M / chip->CrystalFreqKHz) << P; - Freq = (chip->CrystalFreqKHz * N / M) >> P; - if (Freq > VClk) - DeltaNew = Freq - VClk; - else - DeltaNew = VClk - Freq; - if (DeltaNew < DeltaOld) - { - *mOut = M; - *nOut = N; - *pOut = P; - *clockOut = Freq; - DeltaOld = DeltaNew; - } - } - } - } - return (DeltaOld != 0xFFFFFFFF); -} -/* - * Calculate extended mode parameters (SVGA) and save in a - * mode state structure. - */ -static void CalcStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state, - int bpp, - int width, - int hDisplaySize, - int hDisplay, - int hStart, - int hEnd, - int hTotal, - int height, - int vDisplay, - int vStart, - int vEnd, - int vTotal, - int dotClock -) -{ - int pixelDepth, VClk, m, n, p; - /* - * Save mode parameters. - */ - state->bpp = bpp; - state->width = width; - state->height = height; - /* - * Extended RIVA registers. - */ - pixelDepth = (bpp + 1)/8; - CalcVClock(dotClock, &VClk, &m, &n, &p, chip); - switch (chip->Architecture) - { - case 3: - nv3UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - state->cursor0 = 0x00; - state->cursor1 = 0x78; - state->cursor2 = 0x00000000; - state->pllsel = 0x10010100; - state->config = ((width + 31)/32) - | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) - | 0x1000; - state->general = 0x00000100; - state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; - break; - case 4: - case 5: - nv4UpdateArbitrationSettings(VClk, - pixelDepth * 8, - &(state->arbitration0), - &(state->arbitration1), - chip); - state->cursor0 = 0x00; - state->cursor1 = 0xFC; - state->cursor2 = 0x00000000; - state->pllsel = 0x10000700; - state->config = 0x00001114; - state->general = bpp == 16 ? 0x00101100 : 0x00100100; - state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; - break; - } - state->vpll = (p << 16) | (n << 8) | m; - state->screen = ((hTotal & 0x040) >> 2) - | ((vDisplay & 0x400) >> 7) - | ((vStart & 0x400) >> 8) - | ((vDisplay & 0x400) >> 9) - | ((vTotal & 0x400) >> 10); - state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; - state->horiz = hTotal < 260 ? 0x00 : 0x01; - state->pixel = (pixelDepth > 2 ? 3 : pixelDepth) | 0x40; - state->offset0 = - state->offset1 = - state->offset2 = - state->offset3 = 0; - state->pitch0 = - state->pitch1 = - state->pitch2 = - state->pitch3 = pixelDepth * width; -} -/* - * Load fixed function state and pre-calculated/stored state. - */ -#define LOAD_FIXED_STATE(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ - chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1] -#define LOAD_FIXED_STATE_8BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1] -#define LOAD_FIXED_STATE_15BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1] -#define LOAD_FIXED_STATE_16BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1] -#define LOAD_FIXED_STATE_32BPP(tbl,dev) \ - for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ - chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1] -static void LoadStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state -) -{ - int i; - /* - * Load HW fixed function state. - */ - LOAD_FIXED_STATE(Riva,PMC); - LOAD_FIXED_STATE(Riva,PTIMER); - /* - * Make sure frame buffer config gets set before loading PRAMIN. - */ - chip->PFB[0x00000200/4] = state->config; - switch (chip->Architecture) - { - case 3: - LOAD_FIXED_STATE(nv3,PFIFO); - LOAD_FIXED_STATE(nv3,PRAMIN); - LOAD_FIXED_STATE(nv3,PGRAPH); - switch (state->bpp) - { - case 15: - case 16: - LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); - chip->Tri03 = 0L; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); - chip->Tri03 = 0L; - break; - } - for (i = 0x00000; i < 0x00800; i++) - chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03; - chip->PGRAPH[0x00000630/4] = state->offset0; - chip->PGRAPH[0x00000634/4] = state->offset1; - chip->PGRAPH[0x00000638/4] = state->offset2; - chip->PGRAPH[0x0000063C/4] = state->offset3; - chip->PGRAPH[0x00000650/4] = state->pitch0; - chip->PGRAPH[0x00000654/4] = state->pitch1; - chip->PGRAPH[0x00000658/4] = state->pitch2; - chip->PGRAPH[0x0000065C/4] = state->pitch3; - break; - case 4: - case 5: - LOAD_FIXED_STATE(nv4,PFIFO); - LOAD_FIXED_STATE(nv4,PRAMIN); - LOAD_FIXED_STATE(nv4,PGRAPH); - switch (state->bpp) - { - case 15: - LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); - break; - case 16: - LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); - break; - case 24: - case 32: - LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); - chip->Tri03 = 0L; - break; - case 8: - default: - LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); - LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); - chip->Tri03 = 0L; - break; - } - chip->PGRAPH[0x00000640/4] = state->offset0; - chip->PGRAPH[0x00000644/4] = state->offset1; - chip->PGRAPH[0x00000648/4] = state->offset2; - chip->PGRAPH[0x0000064C/4] = state->offset3; - chip->PGRAPH[0x00000670/4] = state->pitch0; - chip->PGRAPH[0x00000674/4] = state->pitch1; - chip->PGRAPH[0x00000678/4] = state->pitch2; - chip->PGRAPH[0x0000067C/4] = state->pitch3; - break; - } -//NOTICE("8"); -// LOAD_FIXED_STATE(Riva,FIFO); /* FIX ME*/ -//NOTICE("9"); - /* - * Load HW mode state. - */ - outb(0x19, 0x3D4); outb(state->repaint0, 0x3D5); - outb(0x1A, 0x3D4); outb(state->repaint1, 0x3D5); - outb(0x25, 0x3D4); outb(state->screen, 0x3D5); - outb(0x28, 0x3D4); outb(state->pixel, 0x3D5); - outb(0x2D, 0x3D4); outb(state->horiz, 0x3D5); - outb(0x1B, 0x3D4); outb(state->arbitration0, 0x3D5); - outb(0x20, 0x3D4); outb(state->arbitration1, 0x3D5); - outb(0x30, 0x3D4); outb(state->cursor0, 0x3D5); - outb(0x31, 0x3D4); outb(state->cursor1, 0x3D5); - chip->PRAMDAC[0x00000300/4] = state->cursor2; - chip->PRAMDAC[0x00000508/4] = state->vpll; - chip->PRAMDAC[0x0000050C/4] = state->pllsel; - chip->PRAMDAC[0x00000600/4] = state->general; - /* - * Turn off VBlank enable and reset. - */ -// *(chip->VBLANKENABLE) = 0; /* FIXME*/ -// *(chip->VBLANK) = chip->VBlankBit; /*FIXME*/ - /* - * Set interrupt enable. - */ - chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; - /* - * Set current state pointer. - */ - chip->CurrentState = state; - /* - * Reset FIFO free count. - */ - chip->FifoFreeCount = 0; -} -static void UnloadStateExt -( - RIVA_HW_INST *chip, - RIVA_HW_STATE *state -) -{ - /* - * Save current HW state. - */ - outb(0x19, 0x3D4); state->repaint0 = inb(0x3D5); - outb(0x1A, 0x3D4); state->repaint1 = inb(0x3D5); - outb(0x25, 0x3D4); state->screen = inb(0x3D5); - outb(0x28, 0x3D4); state->pixel = inb(0x3D5); - outb(0x2D, 0x3D4); state->horiz = inb(0x3D5); - outb(0x1B, 0x3D4); state->arbitration0 = inb(0x3D5); - outb(0x20, 0x3D4); state->arbitration1 = inb(0x3D5); - outb(0x30, 0x3D4); state->cursor0 = inb(0x3D5); - outb(0x31, 0x3D4); state->cursor1 = inb(0x3D5); - state->cursor2 = chip->PRAMDAC[0x00000300/4]; - state->vpll = chip->PRAMDAC[0x00000508/4]; - state->pllsel = chip->PRAMDAC[0x0000050C/4]; - state->general = chip->PRAMDAC[0x00000600/4]; - state->config = chip->PFB[0x00000200/4]; - switch (chip->Architecture) - { - case 3: - state->offset0 = chip->PGRAPH[0x00000630/4]; - state->offset1 = chip->PGRAPH[0x00000634/4]; - state->offset2 = chip->PGRAPH[0x00000638/4]; - state->offset3 = chip->PGRAPH[0x0000063C/4]; - state->pitch0 = chip->PGRAPH[0x00000650/4]; - state->pitch1 = chip->PGRAPH[0x00000654/4]; - state->pitch2 = chip->PGRAPH[0x00000658/4]; - state->pitch3 = chip->PGRAPH[0x0000065C/4]; - break; - case 4: - case 5: - state->offset0 = chip->PGRAPH[0x00000640/4]; - state->offset1 = chip->PGRAPH[0x00000644/4]; - state->offset2 = chip->PGRAPH[0x00000648/4]; - state->offset3 = chip->PGRAPH[0x0000064C/4]; - state->pitch0 = chip->PGRAPH[0x00000670/4]; - state->pitch1 = chip->PGRAPH[0x00000674/4]; - state->pitch2 = chip->PGRAPH[0x00000678/4]; - state->pitch3 = chip->PGRAPH[0x0000067C/4]; - break; - } -} -static void SetStartAddress -( - RIVA_HW_INST *chip, - unsigned start -) -{ - int offset = start >> 2; - int pan = (start & 3) << 1; - unsigned char tmp; - - /* - * Unlock extended registers. - */ - outb(chip->LockUnlockIndex, chip->LockUnlockIO); - outb(0x57, chip->LockUnlockIO + 1); - /* - * Set start address. - */ - outb(0x0D, 0x3D4); - outb(offset, 0x3D5); - outb(0x0C, 0x3D4); - outb(offset >> 8, 0x3D5); - outb(0x19, 0x3D4); - tmp = inb(0x3D5); - outb(((offset >> 16) & 0x0F) | (tmp & 0xF0), 0x3D5); - /* - * 4 pixel pan register. - */ - offset = inb(chip->IO + 0x0A); - outb(0x13, 0x3C0); - outb(pan, 0x3C0); -} -static void nv3SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - while (nv3Busy(chip)); - chip->PGRAPH[0x00000630/4] = surf0; - chip->PGRAPH[0x00000634/4] = surf1; -} -static void nv4SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - while (nv4Busy(chip)); - chip->PGRAPH[0x00000640/4] = surf0; - chip->PGRAPH[0x00000644/4] = surf1; -} -static void nv3SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - while (nv3Busy(chip)); - chip->PGRAPH[0x00000638/4] = surf0; - chip->PGRAPH[0x0000063C/4] = surf1; -} -static void nv4SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - while (nv4Busy(chip)); - chip->PGRAPH[0x00000648/4] = surf0; - chip->PGRAPH[0x0000064C/4] = surf1; -} - -/****************************************************************************\ -* * -* Probe RIVA Chip Configuration * -* * -\****************************************************************************/ - -void nv3GetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Fill in chip configuration. - */ - if (chip->PFB[0x00000000/4] & 0x00000020) - { - if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20) - && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02)) - { - /* - * SDRAM 128 ZX. - */ - chip->RamBandwidthKBytesPerSec = 800000; - switch (chip->PFB[0x00000000/4] & 0x03) - { - case 2: - chip->RamAmountKBytes = 1024 * 4 - 32; - break; - case 1: - chip->RamAmountKBytes = 1024 * 2 - 32; - break; - default: - chip->RamAmountKBytes = 1024 * 8 - 32; - break; - } - } - else - { - chip->RamBandwidthKBytesPerSec = 1000000; - chip->RamAmountKBytes = 1024 * 8 - 32; - } - } - else - { - /* - * SGRAM 128. - */ - chip->RamBandwidthKBytesPerSec = 1000000; - switch (chip->PFB[0x00000000/4] & 0x00000003) - { - case 0: - chip->RamAmountKBytes = 1024 * 8 - 32; - break; - case 2: - chip->RamAmountKBytes = 1024 * 4 - 32; - break; - default: - chip->RamAmountKBytes = 1024 * 2 - 32; - break; - } - } - chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000020) ? 14318 : 13500; - chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); - chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); - chip->VBLANKENABLE = &(chip->PGRAPH[0x0140/4]); - chip->VBLANK = &(chip->PGRAPH[0x0100/4]); - chip->VBlankBit = 0x00000100; - chip->MaxVClockFreqKHz = 230000; - chip->LockUnlockIO = 0x3C4; - chip->LockUnlockIndex = 0x06; - /* - * Set chip functions. - */ - chip->Busy = nv3Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->CalcStateExt = CalcStateExt; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv3SetSurfaces2D; - chip->SetSurfaces3D = nv3SetSurfaces3D; -} - -void nv4GetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Fill in chip configuration. - */ - switch (chip->PFB[0x00000000/4] & 0x00000003) - { - case 0: - chip->RamAmountKBytes = 1024 * 32 - 128; - break; - case 1: - chip->RamAmountKBytes = 1024 * 4 - 128; - break; - case 2: - chip->RamAmountKBytes = 1024 * 8 - 128; - break; - case 3: - default: - chip->RamAmountKBytes = 1024 * 16 - 128; - break; - } - switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) - { - case 3: - chip->RamBandwidthKBytesPerSec = 800000; - break; - default: - chip->RamBandwidthKBytesPerSec = 1000000; - break; - } - chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500; - chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); - chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); - chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); - chip->VBLANK = &(chip->PCRTC[0x0100/4]); - chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 250000; - chip->LockUnlockIO = 0x3D4; - chip->LockUnlockIndex = 0x1F; - /* - * Set chip functions. - */ - chip->Busy = nv4Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->CalcStateExt = CalcStateExt; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv4SetSurfaces2D; - chip->SetSurfaces3D = nv4SetSurfaces3D; -} - -void nv5GetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Fill in chip configuration. - */ - switch (chip->PFB[0x00000000/4] & 0x00000003) - { - case 0: - chip->RamAmountKBytes = 1024 * 32 - 128; - break; - case 1: - chip->RamAmountKBytes = 1024 * 4 - 128; - break; - case 2: - chip->RamAmountKBytes = 1024 * 8 - 128; - break; - case 3: - default: - chip->RamAmountKBytes = 1024 * 16 - 128; - break; - } - switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) - { - case 3: - chip->RamBandwidthKBytesPerSec = 800000; - break; - default: - chip->RamBandwidthKBytesPerSec = 1000000; - break; - } - chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500; - chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); - chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); - chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); - chip->VBLANK = &(chip->PCRTC[0x0100/4]); - chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 250000; - chip->LockUnlockIO = 0x3D4; - chip->LockUnlockIndex = 0x1F; - /* - * Set chip functions. - */ - chip->Busy = nv4Busy; - chip->ShowHideCursor = ShowHideCursor; - chip->CalcStateExt = CalcStateExt; - chip->LoadStateExt = LoadStateExt; - chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv4SetSurfaces2D; - chip->SetSurfaces3D = nv4SetSurfaces3D; -} - -int RivaGetConfig -( - RIVA_HW_INST *chip -) -{ - /* - * Save this so future SW know whats it's dealing with. - */ - chip->Version = RIVA_SW_VERSION; - /* - * Chip specific configuration. - */ - switch (chip->Architecture) - { - case 3: - nv3GetConfig(chip); - break; - case 4: - nv4GetConfig(chip); - break; - case 5: - nv5GetConfig(chip); - default: - return (-1); - } - /* - * Fill in FIFO pointers. - */ - chip->Rop = (RivaRop *)&(chip->FIFO[0x00000000/4]); - chip->Clip = (RivaClip *)&(chip->FIFO[0x00002000/4]); - chip->Patt = (RivaPattern *)&(chip->FIFO[0x00004000/4]); - chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]); - chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]); - chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); - return (0); -} - diff --git a/drivers/video/riva_hw.h b/drivers/video/riva_hw.h deleted file mode 100644 index 6ab8395e5..000000000 --- a/drivers/video/riva_hw.h +++ /dev/null @@ -1,343 +0,0 @@ -/***************************************************************************\ -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| -\***************************************************************************/ -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.h,v 1.1.2.2 1998/12/22 16:33:19 hohndel Exp $ */ -#ifndef __RIVA_HW_H__ -#define __RIVA_HW_H__ -#define RIVA_SW_VERSION 0x00010000 - -/***************************************************************************\ -* * -* FIFO registers. * -* * -\***************************************************************************/ - -/* - * Raster OPeration. Windows style ROP3. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned Rop3; -} RivaRop; -/* - * 8X8 Monochrome pattern. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BD]; - unsigned Shape; - unsigned reserved03[0x001]; - unsigned Color0; - unsigned Color1; - unsigned Monochrome[2]; -} RivaPattern; -/* - * Scissor clip rectangle. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned TopLeft; - unsigned WidthHeight; -} RivaClip; -/* - * 2D filled rectangle. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop[1]; - unsigned reserved01[0x0BC]; - unsigned Color; - unsigned reserved03[0x03E]; - unsigned TopLeft; - unsigned WidthHeight; -} RivaRectangle; -/* - * 2D screen-screen BLT. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned TopLeftSrc; - unsigned TopLeftDst; - unsigned WidthHeight; -} RivaScreenBlt; -/* - * 2D pixel BLT. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop[1]; - unsigned reserved01[0x0BC]; - unsigned TopLeft; - unsigned WidthHeight; - unsigned WidthHeightIn; - unsigned reserved02[0x03C]; - unsigned Pixels; -} RivaPixmap; -/* - * Filled rectangle combined with monochrome expand. Useful for glyphs. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned reserved03[(0x040)-1]; - unsigned Color1A; - struct - { - unsigned TopLeft; - unsigned WidthHeight; - } UnclippedRectangle[64]; - unsigned reserved04[(0x080)-3]; - struct - { - unsigned TopLeft; - unsigned BottomRight; - } ClipB; - unsigned Color1B; - struct - { - unsigned TopLeft; - unsigned BottomRight; - } ClippedRectangle[64]; - unsigned reserved05[(0x080)-5]; - struct - { - unsigned TopLeft; - unsigned BottomRight; - } ClipC; - unsigned Color1C; - unsigned WidthHeightC; - unsigned PointC; - unsigned MonochromeData1C; - unsigned reserved06[(0x080)+121]; - struct - { - unsigned TopLeft; - unsigned BottomRight; - } ClipD; - unsigned Color1D; - unsigned WidthHeightInD; - unsigned WidthHeightOutD; - unsigned PointD; - unsigned MonochromeData1D; - unsigned reserved07[(0x080)+120]; - struct - { - unsigned TopLeft; - unsigned BottomRight; - } ClipE; - unsigned Color0E; - unsigned Color1E; - unsigned WidthHeightInE; - unsigned WidthHeightOutE; - unsigned PointE; - unsigned MonochromeData01E; -} RivaBitmap; -/* - * 3D textured, Z buffered triangle. - */ -typedef volatile struct -{ - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BC]; - unsigned TextureOffset; - unsigned TextureFormat; - unsigned TextureFilter; - unsigned FogColor; - unsigned Control; - unsigned AlphaTest; - unsigned reserved02[0x339]; - unsigned FogAndIndex; - unsigned Color; - float ScreenX; - float ScreenY; - float ScreenZ; - float EyeM; - float TextureS; - float TextureT; -} RivaTexturedTriangle03; - -/***************************************************************************\ -* * -* Virtualized RIVA H/W interface. * -* * -\***************************************************************************/ - -struct _riva_hw_inst; -struct _riva_hw_state; -/* - * Virtialized chip interface. Makes RIVA 128 and TNT look alike. - */ -typedef struct _riva_hw_inst -{ - /* - * Chip specific settings. - */ - unsigned Architecture; - unsigned Version; - unsigned CrystalFreqKHz; - unsigned RamAmountKBytes; - unsigned MaxVClockFreqKHz; - unsigned RamBandwidthKBytesPerSec; - unsigned EnableIRQ; - unsigned IO; - unsigned LockUnlockIO; - unsigned LockUnlockIndex; - unsigned VBlankBit; - unsigned FifoFreeCount; - /* - * Non-FIFO registers. - */ - volatile unsigned *PCRTC; - volatile unsigned *PRAMDAC; - volatile unsigned *PFB; - volatile unsigned *PFIFO; - volatile unsigned *PGRAPH; - volatile unsigned *PEXTDEV; - volatile unsigned *PTIMER; - volatile unsigned *PMC; - volatile unsigned *PRAMIN; - volatile unsigned *FIFO; - volatile unsigned *CURSOR; - volatile unsigned *CURSORPOS; - volatile unsigned *VBLANKENABLE; - volatile unsigned *VBLANK; - /* - * Common chip functions. - */ - int (*Busy)(struct _riva_hw_inst *); - void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int); - void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); - void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); - void (*SetStartAddress)(struct _riva_hw_inst *,unsigned); - void (*SetSurfaces2D)(struct _riva_hw_inst *,unsigned,unsigned); - void (*SetSurfaces3D)(struct _riva_hw_inst *,unsigned,unsigned); - int (*ShowHideCursor)(struct _riva_hw_inst *,int); - /* - * Current extended mode settings. - */ - struct _riva_hw_state *CurrentState; - /* - * FIFO registers. - */ - RivaRop *Rop; - RivaPattern *Patt; - RivaClip *Clip; - RivaPixmap *Pixmap; - RivaScreenBlt *Blt; - RivaBitmap *Bitmap; - RivaTexturedTriangle03 *Tri03; -} RIVA_HW_INST; -/* - * Extended mode state information. - */ -typedef struct _riva_hw_state -{ - unsigned bpp; - unsigned width; - unsigned height; - unsigned repaint0; - unsigned repaint1; - unsigned screen; - unsigned pixel; - unsigned horiz; - unsigned arbitration0; - unsigned arbitration1; - unsigned vpll; - unsigned pllsel; - unsigned general; - unsigned config; - unsigned cursor0; - unsigned cursor1; - unsigned cursor2; - unsigned offset0; - unsigned offset1; - unsigned offset2; - unsigned offset3; - unsigned pitch0; - unsigned pitch1; - unsigned pitch2; - unsigned pitch3; -} RIVA_HW_STATE; -/* - * External routines. - */ -int RivaGetConfig(RIVA_HW_INST *); -/* - * FIFO Free Count. Should attempt to yield processor if RIVA is busy. - */ -#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ -{ \ -while ((hwinst).FifoFreeCount < (cnt)) \ -{ \ - (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \ -} \ -(hwinst).FifoFreeCount -= (cnt); \ -} -#endif /* __RIVA_HW_H__ */ - diff --git a/drivers/video/riva_tbl.h b/drivers/video/riva_tbl.h deleted file mode 100644 index 8188c0fd8..000000000 --- a/drivers/video/riva_tbl.h +++ /dev/null @@ -1,402 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_tbl.h,v 1.1.2.2 1998/12/22 16:33:20 hohndel Exp $ */ -/* - * RIVA Fixed Functionality Init Tables. - */ -static unsigned RivaTablePMC[][2] = -{ - {0x00000050, 0x00000000}, - {0x00000080, 0xFFFF00FF}, - {0x00000080, 0xFFFFFFFF} -}; -static unsigned RivaTablePTIMER[][2] = -{ - {0x00000080, 0x00000008}, - {0x00000084, 0x00000003}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF} -}; -static unsigned RivaTableFIFO[][2] = -{ - {0x00000000, 0x80000000}, - {0x00000800, 0x80000001}, - {0x00001000, 0x80000002}, - {0x00001800, 0x80000010}, - {0x00002000, 0x80000011}, - {0x00002800, 0x80000012}, - {0x00003800, 0x80000013} -}; -static unsigned nv3TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000490, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000481, 0x00000000}, - {0x00000084, 0x00000000}, - {0x00000086, 0x00002000}, - {0x00000085, 0x00002200}, - {0x00000484, 0x00000000}, - {0x0000049C, 0x00000000}, - {0x00000104, 0x00000000}, - {0x00000108, 0x00000000}, - {0x00000100, 0x00000000}, - {0x000004A0, 0x00000000}, - {0x000004A4, 0x00000000}, - {0x000004A8, 0x00000000}, - {0x000004AC, 0x00000000}, - {0x000004B0, 0x00000000}, - {0x000004B4, 0x00000000}, - {0x000004B8, 0x00000000}, - {0x000004BC, 0x00000000}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000480, 0x00000001}, - {0x00000490, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv3TablePGRAPH[][2] = -{ - {0x00000020, 0x1230001F}, - {0x00000021, 0x10113000}, - {0x00000022, 0x1131F101}, - {0x00000023, 0x0100F531}, - {0x00000060, 0x00000000}, - {0x00000065, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000069, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x000001A8, 0x00000000}, - {0x00000440, 0xFFFFFFFF}, - {0x00000480, 0x00000001}, - {0x000001A0, 0x00000000}, - {0x000001A2, 0x00000000}, - {0x0000018A, 0xFFFFFFFF}, - {0x00000190, 0x00000000}, - {0x00000142, 0x00000000}, - {0x00000154, 0x00000000}, - {0x00000155, 0xFFFFFFFF}, - {0x00000156, 0x00000000}, - {0x00000157, 0xFFFFFFFF}, - {0x00000064, 0x10010002}, - {0x00000050, 0x00000000}, - {0x00000051, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000041, 0xFFFFFFFF}, - {0x00000440, 0xFFFFFFFF}, - {0x000001A9, 0x00000001} -}; -static unsigned nv3TablePGRAPH_8BPP[][2] = -{ - {0x000001AA, 0x00001111} -}; -static unsigned nv3TablePGRAPH_15BPP[][2] = -{ - {0x000001AA, 0x00002222} -}; -static unsigned nv3TablePGRAPH_32BPP[][2] = -{ - {0x000001AA, 0x00003333} -}; -static unsigned nv3TablePRAMIN[][2] = -{ - {0x00000500, 0x00010000}, - {0x00000501, 0x007FFFFF}, - {0x00000200, 0x80000000}, - {0x00000201, 0x00C20341}, - {0x00000204, 0x80000001}, - {0x00000205, 0x00C50342}, - {0x00000208, 0x80000002}, - {0x00000209, 0x00C60343}, - {0x00000240, 0x80000010}, - {0x00000241, 0x00D10344}, - {0x00000244, 0x80000011}, - {0x00000245, 0x00D00345}, - {0x00000248, 0x80000012}, - {0x00000249, 0x00CC0346}, - {0x0000024C, 0x80000013}, - {0x0000024D, 0x00D70347}, - {0x00000D05, 0x00000000}, - {0x00000D06, 0x00000000}, - {0x00000D07, 0x00000000}, - {0x00000D09, 0x00000000}, - {0x00000D0A, 0x00000000}, - {0x00000D0B, 0x00000000}, - {0x00000D0D, 0x00000000}, - {0x00000D0E, 0x00000000}, - {0x00000D0F, 0x00000000}, - {0x00000D11, 0x00000000}, - {0x00000D12, 0x00000000}, - {0x00000D13, 0x00000000}, - {0x00000D15, 0x00000000}, - {0x00000D16, 0x00000000}, - {0x00000D17, 0x00000000}, - {0x00000D19, 0x00000000}, - {0x00000D1A, 0x00000000}, - {0x00000D1B, 0x00000000}, - {0x00000D1D, 0x00000140}, - {0x00000D1E, 0x00000000}, - {0x00000D1F, 0x00000000} -}; -static unsigned nv3TablePRAMIN_8BPP[][2] = -{ - {0x00000D04, 0x10110203}, - {0x00000D08, 0x10110203}, - {0x00000D0C, 0x10110203}, - {0x00000D10, 0x10118203}, - {0x00000D14, 0x10110203}, - {0x00000D18, 0x10110203}, - {0x00000D1C, 0x10419208} -}; -static unsigned nv3TablePRAMIN_15BPP[][2] = -{ - {0x00000D04, 0x10110200}, - {0x00000D08, 0x10110200}, - {0x00000D0C, 0x10110200}, - {0x00000D10, 0x10118200}, - {0x00000D14, 0x10110200}, - {0x00000D18, 0x10110200}, - {0x00000D1C, 0x10419208} -}; -static unsigned nv3TablePRAMIN_32BPP[][2] = -{ - {0x00000D04, 0x10110201}, - {0x00000D08, 0x10110201}, - {0x00000D0C, 0x10110201}, - {0x00000D10, 0x10118201}, - {0x00000D14, 0x10110201}, - {0x00000D18, 0x10110201}, - {0x00000D1C, 0x10419208} -}; -static unsigned nv4TablePFIFO[][2] = -{ - {0x00000140, 0x00000000}, - {0x00000480, 0x00000000}, - {0x00000494, 0x00000000}, - {0x00000400, 0x00000000}, - {0x00000414, 0x00000000}, - {0x00000084, 0x03000100}, - {0x00000085, 0x00000110}, - {0x00000086, 0x00000112}, - {0x00000143, 0x0000FFFF}, - {0x00000496, 0x0000FFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x00000415, 0x00000001}, - {0x00000480, 0x00000001}, - {0x00000494, 0x00000001}, - {0x00000495, 0x00000001}, - {0x00000140, 0x00000001} -}; -static unsigned nv4TablePGRAPH[][2] = -{ - {0x00000020, 0x1231C001}, - {0x00000021, 0x72111101}, - {0x00000022, 0x11D5F071}, - {0x00000023, 0x10D4FF31}, - {0x00000060, 0x00000000}, - {0x00000068, 0x00000000}, - {0x00000070, 0x00000000}, - {0x00000078, 0x00000000}, - {0x00000061, 0x00000000}, - {0x00000069, 0x00000000}, - {0x00000071, 0x00000000}, - {0x00000079, 0x00000000}, - {0x00000062, 0x00000000}, - {0x0000006A, 0x00000000}, - {0x00000072, 0x00000000}, - {0x0000007A, 0x00000000}, - {0x00000063, 0x00000000}, - {0x0000006B, 0x00000000}, - {0x00000073, 0x00000000}, - {0x0000007B, 0x00000000}, - {0x00000064, 0x00000000}, - {0x0000006C, 0x00000000}, - {0x00000074, 0x00000000}, - {0x0000007C, 0x00000000}, - {0x00000065, 0x00000000}, - {0x0000006D, 0x00000000}, - {0x00000075, 0x00000000}, - {0x0000007D, 0x00000000}, - {0x00000066, 0x00000000}, - {0x0000006E, 0x00000000}, - {0x00000076, 0x00000000}, - {0x0000007E, 0x00000000}, - {0x00000067, 0x00000000}, - {0x0000006F, 0x00000000}, - {0x00000077, 0x00000000}, - {0x0000007F, 0x00000000}, - {0x00000058, 0x00000000}, - {0x00000059, 0x00000000}, - {0x0000005A, 0x00000000}, - {0x0000005B, 0x00000000}, - {0x00000196, 0x00000000}, - {0x000001A1, 0x00FFFFFF}, - {0x00000197, 0x00000000}, - {0x000001A2, 0x00FFFFFF}, - {0x00000198, 0x00000000}, - {0x000001A3, 0x00FFFFFF}, - {0x00000199, 0x00000000}, - {0x000001A4, 0x00FFFFFF}, - {0x00000050, 0x00000000}, - {0x00000040, 0xFFFFFFFF}, - {0x0000005C, 0x10010100}, - {0x000001C8, 0x00000001} -}; -static unsigned nv4TablePGRAPH_8BPP[][2] = -{ - {0x000001C4, 0xFFFFFFFF}, - {0x000001C9, 0x00111111}, - {0x00000186, 0x00001010}, - {0x0000020C, 0x01010101} -}; -static unsigned nv4TablePGRAPH_15BPP[][2] = -{ - {0x000001C4, 0xFFFFFFFF}, - {0x000001C9, 0x00226222}, - {0x00000186, 0x00002071}, - {0x0000020C, 0x09090909} -}; -static unsigned nv4TablePGRAPH_16BPP[][2] = -{ - {0x000001C4, 0xFFFFFFFF}, - {0x000001C9, 0x00556555}, - {0x00000186, 0x000050C2}, - {0x0000020C, 0x0C0C0C0C} -}; -static unsigned nv4TablePGRAPH_32BPP[][2] = -{ - {0x000001C4, 0xFFFFFFFF}, - {0x000001C9, 0x0077D777}, - {0x00000186, 0x000070E5}, - {0x0000020C, 0x07070707} -}; -static unsigned nv4TablePRAMIN[][2] = -{ - {0x00000000, 0x80000010}, - {0x00000001, 0x80011145}, - {0x00000002, 0x80000011}, - {0x00000003, 0x80011146}, - {0x00000004, 0x80000012}, - {0x00000005, 0x80011147}, - {0x00000006, 0x80000013}, - {0x00000007, 0x80011148}, - {0x00000020, 0x80000000}, - {0x00000021, 0x80011142}, - {0x00000022, 0x80000001}, - {0x00000023, 0x80011143}, - {0x00000024, 0x80000002}, - {0x00000025, 0x80011144}, - {0x00000500, 0x00003000}, - {0x00000501, 0x02FFFFFF}, - {0x00000502, 0x00000002}, - {0x00000503, 0x00000002}, - {0x00000508, 0x01008043}, - {0x0000050A, 0x00000000}, - {0x0000050B, 0x00000000}, - {0x0000050C, 0x01008019}, - {0x0000050E, 0x00000000}, - {0x0000050F, 0x00000000}, - {0x00000510, 0x01008018}, - {0x00000512, 0x00000000}, - {0x00000513, 0x00000000}, - {0x00000514, 0x0100A033}, - {0x00000516, 0x00000000}, - {0x00000517, 0x00000000}, - {0x00000518, 0x0100805F}, - {0x0000051A, 0x00000000}, - {0x0000051B, 0x00000000}, - {0x0000051C, 0x0100804B}, - {0x0000051E, 0x00000000}, - {0x0000051F, 0x00000000}, - {0x00000520, 0x0100A048}, - {0x00000521, 0x00000D01}, - {0x00000522, 0x11401140}, - {0x00000523, 0x00000000} -}; -static unsigned nv4TablePRAMIN_8BPP[][2] = -{ - {0x00000509, 0x00000301}, - {0x0000050D, 0x00000301}, - {0x00000511, 0x00000301}, - {0x00000515, 0x00000301}, - {0x00000519, 0x00000301}, - {0x0000051D, 0x00000301} -}; -static unsigned nv4TablePRAMIN_15BPP[][2] = -{ - {0x00000509, 0x00000901}, - {0x0000050D, 0x00000901}, - {0x00000511, 0x00000901}, - {0x00000515, 0x00000901}, - {0x00000519, 0x00000901}, - {0x0000051D, 0x00000901} -}; -static unsigned nv4TablePRAMIN_16BPP[][2] = -{ - {0x00000509, 0x00000C01}, - {0x0000050D, 0x00000C01}, - {0x00000511, 0x00000C01}, - {0x00000515, 0x00000C01}, - {0x00000519, 0x00000C01}, - {0x0000051D, 0x00000C01} -}; -static unsigned nv4TablePRAMIN_32BPP[][2] = -{ - {0x00000509, 0x00000E01}, - {0x0000050D, 0x00000E01}, - {0x00000511, 0x00000E01}, - {0x00000515, 0x00000E01}, - {0x00000519, 0x00000E01}, - {0x0000051D, 0x00000E01} -}; - diff --git a/drivers/video/rivafb.c b/drivers/video/rivafb.c deleted file mode 100644 index c48f7a08a..000000000 --- a/drivers/video/rivafb.c +++ /dev/null @@ -1,1891 +0,0 @@ -/* - * linux/drivers/video/rivafb.c - nVidia RIVA 128/TNT/TNT2 fb driver - * - * Copyright 1999 Jeff Garzik <jgarzik@mandrakesoft.com> - * - * Contributors: - * - * ani joshi: Lots of debugging and cleanup work, really helped - * get the driver going - * - * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven - * Includes riva_hw.c from nVidia, see copyright below. - * KGI code provided the basis for state storage, init, and mode switching. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -/* version number of this driver */ -#define RIVAFB_VERSION "0.6.5" - -#include <linux/config.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/selection.h> -#include <linux/tty.h> -#include <linux/malloc.h> -#include <linux/delay.h> -#include <linux/fb.h> -#include <linux/init.h> -#include <linux/pci.h> - -#include <video/fbcon.h> - -#include "riva_hw.h" -#include "nv4ref.h" -#include "nvreg.h" -#include "vga.h" -#include <video/fbcon-cfb4.h> -#include <video/fbcon-cfb8.h> -#include <video/fbcon-cfb16.h> -#include <video/fbcon-cfb32.h> - -#ifndef CONFIG_PCI /* sanity check */ -#error This driver requires PCI support. -#endif - -/***************************************************************** - * - * various helpful macros and constants - * - */ - -/* #define RIVAFBDEBUG */ -#ifdef RIVAFBDEBUG -#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args) -#else -#define DPRINTK(fmt, args...) -#endif - -#ifndef RIVA_NDEBUG -#define assert(expr) \ - if(!(expr)) { \ - printk( "Assertion failed! %s,%s,%s,line=%d\n",\ - #expr,__FILE__,__FUNCTION__,__LINE__); \ - *(int*)0 = 0; \ - } -#else -#define assert(expr) -#endif - -/* GGI compatibility macros */ -#define io_out8 outb -#define io_in8 inb -#define FatalError panic -#define NUM_SEQ_REGS 0x05 -#define NUM_CRT_REGS 0x41 -#define NUM_GRC_REGS 0x09 -#define NUM_ATC_REGS 0x15 - -/* max number of VGA controllers we scan for */ -#define RIVA_MAX_VGA_CONTROLLERS 8 - -#define PFX "rivafb: " - -#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) - -/* macro that allows you to set overflow bits */ -#define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) -#define SetBit(n) (1<<(n)) -#define Set8Bits(value) ((value)&0xff) - -struct riva_chip_info { - const char *name; - unsigned arch_rev; - unsigned short vendor; - unsigned short device; -}; - - -static const struct riva_chip_info riva_pci_probe_list[] = -{ - {"RIVA-128", 3, PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128}, - {"RIVA-TNT", 4, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT}, - {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2}, - {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2}, - {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2}, - {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2}, - {NULL, 0, 0, 0} -}; - - -/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. - * From KGI originally. */ -struct riva_regs { - u8 attr[0x15]; - u8 crtc[0x41]; - u8 gra[0x09]; - u8 seq[0x05]; - u8 misc_output; - RIVA_HW_STATE ext; -}; - - -/* - * describes the state of a Riva board - */ -struct rivafb_par { - struct riva_regs state; /* state of hw board */ - __u32 visual; /* FB_VISUAL_xxx */ - unsigned depth; /* bpp of current mode */ -}; - -typedef struct { - unsigned char red, green, blue, transp; -} riva_cfb8_cmap_t; - - - -struct rivafb_info; -struct rivafb_info { - struct fb_info info; /* kernel framebuffer info */ - - RIVA_HW_INST riva; /* interface to riva_hw.c */ - - const char *drvr_name; /* Riva hardware board type */ - - unsigned long ctrl_base_phys; /* physical control register base addr */ - unsigned long fb_base_phys; /* physical framebuffer base addr */ - - caddr_t ctrl_base; /* virtual control register base addr */ - caddr_t fb_base; /* virtual framebuffer base addr */ - - unsigned ram_amount; /* amount of RAM on card, in megabytes */ - unsigned dclk_max; /* max DCLK */ - - struct riva_regs initial_state; /* initial startup video mode */ - - struct display disp; - int currcon; - struct display *currcon_display; - - struct rivafb_info *next; - - struct pci_dev *pd; /* pointer to board's pci info */ - unsigned base0_region_size; /* size of control register region */ - unsigned base1_region_size; /* size of framebuffer region */ - -#ifdef FBCON_HAS_CFB8 - riva_cfb8_cmap_t palette[256]; /* VGA DAC palette cache */ -#endif - -#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32) - union { -#ifdef FBCON_HAS_CFB16 - u_int16_t cfb16[16]; -#endif -#ifdef FBCON_HAS_CFB32 - u_int32_t cfb32[16]; -#endif - } con_cmap; -#endif /* FBCON_HAS_CFB16 | FBCON_HAS_CFB32 */ -}; - -/* ------------------- global variables ------------------------ */ - - -static struct rivafb_info *riva_boards = NULL; - -/* command line data, set in rivafb_setup() */ -static char fontname[40] __initdata = { 0 }; -static char noaccel __initdata = 0; /* unused */ -#ifndef MODULE -static const char *mode_option __initdata = NULL; -#endif - - -/* ------------------- prototypes ------------------------------ */ - -int rivafb_open (struct fb_info *info, int user); -int rivafb_release (struct fb_info *info, int user); -int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con, - struct fb_info *info); -int rivafb_get_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -int rivafb_set_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info); -int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info); -int rivafb_pan_display (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg, int con, struct fb_info *info); -int rivafb_switch(int con, struct fb_info *info); -void rivafb_blank (int blank, struct fb_info *info); - -static void riva_load_video_mode (struct rivafb_info *rivainfo, - struct fb_var_screeninfo *video_mode); -static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green, - unsigned *blue, unsigned *transp, - struct fb_info *info); -static int riva_setcolreg (unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info); -static int riva_get_cmap_len(const struct fb_var_screeninfo *var); - -static u32 riva_pci_region_size (struct pci_dev *pd, unsigned baseaddr); - -static void riva_pci_iounmap (struct rivafb_info *rinfo); -static int riva_pci_register (struct pci_dev *pd, const struct riva_chip_info *rci); -static int riva_pci_register_devices (void); -static int riva_set_fbinfo (struct rivafb_info *rinfo); - -static -void riva_save_state(struct rivafb_info *rinfo, struct riva_regs *regs); -static -void riva_load_state(struct rivafb_info *rinfo, struct riva_regs *regs); -static -struct rivafb_info *riva_board_list_add(struct rivafb_info *board_list, - struct rivafb_info *new_node); - -#if 0 -static void riva_pci_region_init (struct pci_dev *pd, struct rivafb_info *rinfo); -#endif - -static void riva_wclut (unsigned char regnum, unsigned char red, - unsigned char green, unsigned char blue); - - - - -/* kernel interface */ -static struct fb_ops riva_fb_ops = -{ - rivafb_open, - rivafb_release, - rivafb_get_fix, - rivafb_get_var, - rivafb_set_var, - rivafb_get_cmap, - rivafb_set_cmap, - rivafb_pan_display, - rivafb_ioctl -}; - - - - -/* from GGI */ -static const struct riva_regs reg_template = -{ - { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, - 0x41, 0x01, 0x0F, 0x13, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ - 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, /* 0x40 */ - }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ - 0xFF }, - { 0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ - 0xEB /* MISC */ -}; - - - -/* ------------------- general utility functions -------------------------- */ - -/** - * riva_set_dispsw - * @rivainfo: pointer to internal driver struct for a given Riva card - * - * DESCRIPTION: - * Sets up console Low level operations depending on the current? color depth - * of the display - */ - -void riva_set_dispsw (struct rivafb_info *rinfo) -{ - struct display *disp = &rinfo->disp; - - DPRINTK ("ENTER\n"); - - assert (rinfo != NULL); - - disp->dispsw_data = NULL; - - switch (disp->var.bits_per_pixel) { -#ifdef FBCON_HAS_MFB - case 1: - disp->dispsw = &fbcon_mfb; - break; -#endif -#ifdef FBCON_HAS_CFB4 - case 4: - disp->dispsw = &fbcon_cfb4; - break; -#endif -#ifdef FBCON_HAS_CFB8 - case 8: - disp->dispsw = &fbcon_cfb8; - break; -#endif -#ifdef FBCON_HAS_CFB16 - case 15: - case 16: - disp->dispsw = &fbcon_cfb16; - disp->dispsw_data = &rinfo->con_cmap.cfb16; - break; -#endif -#ifdef FBCON_HAS_CFB24 - case 24: - disp->dispsw = &fbcon_cfb24; - disp->dispsw_data = rinfo->con_cmap.cfb24; - break; -#endif -#ifdef FBCON_HAS_CFB32 - case 32: - disp->dispsw = &fbcon_cfb32; - disp->dispsw_data = rinfo->con_cmap.cfb32; - break; -#endif - default: - DPRINTK ("Setting fbcon_dummy renderer\n"); - disp->dispsw = &fbcon_dummy; - } - - DPRINTK ("EXIT\n"); -} - - - - -static int riva_init_disp_var (struct rivafb_info *rinfo) -{ - if (mode_option) - fb_find_mode(&rinfo->disp.var, &rinfo->info, mode_option, - NULL, 0, NULL, 8); - else - fb_find_mode(&rinfo->disp.var, &rinfo->info, - "640x480-8@60", NULL, 0, NULL, 8); - return 0; -} - - - - -static int __init riva_init_disp (struct rivafb_info *rinfo) -{ - struct fb_info *info; - struct display *disp; - - DPRINTK("ENTER\n"); - - assert (rinfo != NULL); - - info = &rinfo->info; - disp = &rinfo->disp; - - info->disp = disp; - -#warning FIXME: assure that disp->cmap is completely filled out - - disp->screen_base = rinfo->fb_base; - disp->visual = FB_VISUAL_PSEUDOCOLOR; - disp->type = FB_TYPE_PACKED_PIXELS; - disp->type_aux = 0; - disp->ypanstep = 1; - disp->ywrapstep = 0; - disp->next_line = disp->line_length = - (disp->var.xres_virtual * disp->var.bits_per_pixel) >> 3; - disp->can_soft_blank = 1; - disp->inverse = 0; - - riva_set_dispsw(rinfo); - - rinfo->currcon_display = disp; - - if ((riva_init_disp_var (rinfo)) < 0) { /* must be done last */ - DPRINTK("EXIT, returning -1\n"); - return -1; - } - - DPRINTK("EXIT, returning 0\n"); - return 0; - -} - - - -static int __init riva_set_fbinfo (struct rivafb_info *rinfo) -{ - struct fb_info *info; - - assert (rinfo != NULL); - - info = &rinfo->info; - - strcpy (info->modename, rinfo->drvr_name); - info->node = -1; - info->flags = FBINFO_FLAG_DEFAULT; - info->fbops = &riva_fb_ops; - -#warning FIXME: set monspecs to what??? - - info->display_fg = NULL; /* FIXME: correct? */ - strncpy (info->fontname, fontname, sizeof (info->fontname)); - info->fontname[sizeof (info->fontname) - 1] = 0; - - info->changevar = NULL; /* FIXME: needed? */ - info->switch_con = rivafb_switch; - info->updatevar = NULL; /* FIXME? */ - info->blank = rivafb_blank; - - if (riva_init_disp (rinfo) < 0) /* must be done last */ - return -1; - - return 0; -} - - - - -/* ----------------------------- PCI bus ----------------------------- */ - - - - -/** - * riva_pci_region_size - * @pd: pointer to PCI device to be configured - * - * DESCRIPTION: - * Obtains from the PCI bus the size of the address space allocated to - * the given card's base address zero region. - */ - -static -u32 riva_pci_region_size (struct pci_dev *pd, unsigned baseaddr) -{ - return pd->resource[baseaddr].end - pd->resource[baseaddr].start + 1; -} - - - - -#if 0 - -/** - * riva_pci_iomap - * @nv: - * - * DESCRIPTION: - */ - -static -void riva_pci_region_init (struct pci_dev *pd, struct rivafb_info *rinfo) -{ - unsigned long addr; - - assert (rinfo != NULL); - assert (pd != NULL); - - rinfo->pd = pd; - rinfo->base0_region_size = riva_pci_region_size (pd, PCI_BASE_ADDRESS_0); - assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */ - rinfo->base1_region_size = riva_pci_region_size (pd, PCI_BASE_ADDRESS_1); - assert(rinfo->base0_region_size >= 0x01000000); /* from GGI */ - - /* Get the base addresses */ - pcibios_read_config_dword(0, rinfo->pd->devfn, PCI_BASE_ADDRESS_0, - (unsigned int*)&addr); -#ifdef SHOULDUSETHAT - /* This function should return an int. */ - if (!addr) - return -ENXIO; -#endif - - rinfo->ctrl_base_phys = addr & PCI_BASE_ADDRESS_MEM_MASK; - - pcibios_read_config_dword(0, rinfo->pd->devfn, PCI_BASE_ADDRESS_1, - (unsigned int*)&addr); - - rinfo->fb_base_phys = addr & PCI_BASE_ADDRESS_MEM_MASK; - - rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys, rinfo->base0_region_size); - assert (rinfo->ctrl_base != NULL); - rinfo->fb_base = ioremap (rinfo->fb_base_phys, rinfo->base1_region_size); - assert (rinfo->fb_base != NULL); - - rinfo->riva.EnableIRQ = 0; - rinfo->riva.IO = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; - rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base+0x00680000); - rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base+0x00100000); - rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base+0x00002000); - rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base+0x00400000); - rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base+0x00101000); - rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base+0x00009000); - rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base+0x00000000); - rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base+0x00800000); - - switch (rinfo->riva.Architecture) - { - case 3: - rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00C00000); - break; - case 4: - case 5: - rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base+0x00600000); - rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00710000); - break; - } -} - -#endif /* 0 */ - - - -/** - * riva_pci_iounmap - * @rinfo: - * - * DESCRIPTION: - */ - -static -void riva_pci_iounmap (struct rivafb_info *rinfo) -{ - assert (rinfo != NULL); - assert (rinfo->ctrl_base_phys != 0x00000000); - assert (rinfo->ctrl_base != NULL); - assert (rinfo->fb_base_phys != 0x00000000); - assert (rinfo->fb_base != NULL); - - iounmap (rinfo->ctrl_base); - iounmap (rinfo->fb_base); -} - - - - - -static void __init riva_init_clut (struct rivafb_info *fb_info) -{ - int j, k; - - for (j = 0; j < 256; j++) { - if (j < 16) { - k = color_table[j]; - fb_info->palette[j].red = default_red[k]; - fb_info->palette[j].green = default_grn[k]; - fb_info->palette[j].blue = default_blu[k]; - } else { - fb_info->palette[j].red = - fb_info->palette[j].green = - fb_info->palette[j].blue = j; - } - - riva_wclut (j, - fb_info->palette[j].red, - fb_info->palette[j].green, - fb_info->palette[j].blue); - } -} - - - -static int __init riva_pci_register (struct pci_dev *pd, - const struct riva_chip_info *rci) -{ - struct rivafb_info *rinfo; - - assert (pd != NULL); - assert (rci != NULL); - - rinfo = kmalloc (sizeof (struct rivafb_info), GFP_KERNEL); - assert (rinfo != NULL); - memset (rinfo, 0, sizeof (struct rivafb_info)); - - rinfo->drvr_name = rci->name; - rinfo->riva.Architecture = rci->arch_rev; - - rinfo->pd = pd; - rinfo->base0_region_size = riva_pci_region_size (pd, 0); - rinfo->base1_region_size = riva_pci_region_size (pd, 1); - - assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */ - assert(rinfo->base0_region_size >= 0x01000000); /* from GGI */ - - rinfo->ctrl_base_phys = rinfo->pd->resource[0].start; - rinfo->fb_base_phys = rinfo->pd->resource[1].start; - - request_region(0x3C0, 32, "rivafb"); - - if (!request_mem_region(rinfo->ctrl_base_phys, - rinfo->base0_region_size, "rivafb") || - !request_mem_region(rinfo->fb_base_phys, rinfo->base1_region_size, - "rivafb")) { - printk (KERN_ERR PFX "cannot reserve MMIO region\n"); - return -ENXIO; - } - - rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys, - rinfo->base0_region_size); - assert (rinfo->ctrl_base != NULL); - - rinfo->fb_base = ioremap (rinfo->fb_base_phys, - rinfo->base1_region_size); - assert (rinfo->fb_base != NULL); - - rinfo->riva.EnableIRQ = 0; - rinfo->riva.IO = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0; - rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base+0x00680000); - rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base+0x00100000); - rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base+0x00002000); - rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base+0x00400000); - rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base+0x00101000); - rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base+0x00009000); - rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base+0x00000000); - rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base+0x00800000); - - switch (rinfo->riva.Architecture) - { - case 3: - rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00C00000); - break; - case 4: - case 5: - rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base+0x00600000); - rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00710000); - break; - } - - RivaGetConfig(&rinfo->riva); - - /* back to normal */ - - assert (rinfo->pd != NULL); - - /* unlock io */ - vga_io_wcrt (0x11, 0xFF); /* vgaHWunlock() + riva unlock (0x7F) */ - outb(rinfo->riva.LockUnlockIO, rinfo->riva.LockUnlockIndex); - outb(rinfo->riva.LockUnlockIO + 1, 0x57); - - memcpy (&rinfo->initial_state, ®_template, sizeof (reg_template)); - riva_save_state (rinfo, &rinfo->initial_state); - - rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024; - rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000; - - riva_set_fbinfo (rinfo); - - riva_init_clut (rinfo); - - riva_load_video_mode (rinfo, &rinfo->disp.var); - - if (register_framebuffer ((struct fb_info *) rinfo) < 0) { - printk(KERN_ERR PFX "error registering riva framebuffer\n"); - kfree (rinfo); - return -1; - } - - riva_boards = riva_board_list_add (riva_boards, rinfo); - - printk("PCI Riva NV%d framebuffer ver %s (%s, %dMB @ 0x%lX)\n", - rinfo->riva.Architecture, - RIVAFB_VERSION, - rinfo->drvr_name, - rinfo->ram_amount / (1024 * 1024), - rinfo->fb_base_phys); - - return 0; -} - - - - -static int __init riva_pci_register_devices (void) -{ - struct pci_dev *pd; - const struct riva_chip_info *nci = &riva_pci_probe_list[0]; - - assert (nci != NULL); - while (nci->name != NULL) { - pd = pci_find_device (nci->vendor, nci->device, NULL); - while (pd != NULL) { - if (riva_pci_register (pd, nci) < 0) - return -1; - - pd = pci_find_device (nci->vendor, nci->device, pd); - } - - nci++; - } - - return 0; -} - - - -/*** riva_wclut - set CLUT entry ***/ -static void riva_wclut (unsigned char regnum, unsigned char red, - unsigned char green, unsigned char blue) -{ - unsigned int data = VGA_PEL_D; - - /* address write mode register is not translated.. */ - vga_io_w (VGA_PEL_IW, regnum); - - vga_io_w (data, red); - vga_io_w (data, green); - vga_io_w (data, blue); -} - - - -/* ------------ Hardware Independent Functions ------------ */ - -int __init rivafb_setup(char *options) -{ - char *this_opt; - - if (!options || !*options) - return 0; - - for (this_opt = strtok(options, ","); this_opt; - this_opt = strtok(NULL, ",")) { - if (!strncmp(this_opt, "font:", 5)) { - char *p; - int i; - - p = this_opt + 5; - for (i = 0; i < sizeof(fontname) - 1; i++) - if (!*p || *p == ' ' || *p == ',') - break; - memcpy(fontname, this_opt + 5, i); - fontname[i] = 0; - } - - else if (!strncmp(this_opt, "noaccel", 7)) { - noaccel = 1; - } - - else - mode_option = this_opt; - } - return 0; -} - - /* - * Initialization - */ - -int __init rivafb_init (void) -{ - if (riva_pci_register_devices () < 0) - return -ENXIO; - - if (riva_boards == NULL) - return -ENODEV; - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - /* - * Cleanup - */ - -void __exit rivafb_cleanup (struct fb_info *info) -{ -#warning FIXME: is this all we need to do? - - struct rivafb_info *tmp, *board = riva_boards; - - while (board != NULL) { - riva_load_state (board, &board->initial_state); - riva_pci_iounmap (board); - - unregister_framebuffer ((struct fb_info *) board); - - tmp = board; - board = board->next; - - kfree_s (tmp, sizeof (struct rivafb_info)); - } - - (void) info; /* unused function arg */ -} - - - - - /* - * Frame buffer operations - */ - -int rivafb_open(struct fb_info *info, int user) -{ - /* Nothing, only a usage count for the moment */ - MOD_INC_USE_COUNT; - return 0; -} - -int rivafb_release(struct fb_info *info, int user) -{ - MOD_DEC_USE_COUNT; - return 0; -} - - -/** - * rivafb_get_fix - * @fix: - * @con: - * @info: - * - * DESCRIPTION: - */ - -int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - struct display *p; - - DPRINTK ("ENTER\n"); - - assert (fix != NULL); - assert (info != NULL); - assert (rivainfo->drvr_name && rivainfo->drvr_name[0]); - assert (rivainfo->fb_base_phys > 0); - assert (rivainfo->ram_amount > 0); - - p = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - - memset (fix, 0, sizeof (struct fb_fix_screeninfo)); - sprintf (fix->id, "Riva %s", rivainfo->drvr_name); - - fix->smem_start = rivainfo->fb_base_phys; - fix->smem_len = rivainfo->ram_amount; - - fix->type = p->type; - fix->type_aux = p->type_aux; - fix->visual = p->visual; - - fix->xpanstep = 1; - fix->ypanstep = 1; - fix->ywrapstep = 0; /* FIXME: no ywrap for now */ - - fix->line_length = p->line_length; - -#warning FIXME: set up MMIO region - fix->mmio_start = 0; - fix->mmio_len = 0; - -#warning FIXME: reference riva acceleration fb.h constant here - fix->accel = FB_ACCEL_NONE; - - DPRINTK ("EXIT, returning 0\n"); - - return 0; -} - - - -/** - * rivafb_get_var - * @var: - * @con: - * @info: - * - * DESCRIPTION: - */ - -int rivafb_get_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - - DPRINTK ("ENTER\n"); - - assert (info != NULL); - assert (var != NULL); - - *var = (con < 0) ? rivainfo->disp.var : fb_display[con].var; - - DPRINTK ("EXIT, returning 0\n"); - - return 0; -} - - - -/** - * rivafb_set_var - * @var: - * @con: - * @info: - * - * DESCRIPTION: - */ - -int rivafb_set_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - struct display *dsp; - struct fb_var_screeninfo v; - int nom, den; /* translating from pixels->bytes */ - int i; - unsigned chgvar = 0; - static struct { - int xres, yres; - } modes[] = { - { 1600, 1280 }, - { 1280, 1024 }, - { 1024, 768 }, - { 800, 600 }, - { 640, 480 }, - { -1, -1 } - }; - - DPRINTK ("ENTER\n"); - - assert (info != NULL); - assert (var != NULL); - - DPRINTK ("Requested: %dx%dx%d\n", var->xres, var->yres, var->bits_per_pixel); - DPRINTK (" virtual: %dx%d\n", var->xres_virtual, var->yres_virtual); - DPRINTK (" offset: (%d,%d)\n", var->xoffset, var->yoffset); - DPRINTK ("grayscale: %d\n", var->grayscale); - - dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - assert (dsp != NULL); - - /* if var has changed, we should call changevar() later */ - if (con >= 0) { - chgvar = ((dsp->var.xres != var->xres) || - (dsp->var.yres != var->yres) || - (dsp->var.xres_virtual != var->xres_virtual) || - (dsp->var.yres_virtual != var->yres_virtual) || - (dsp->var.bits_per_pixel != var->bits_per_pixel) || - memcmp(&dsp->var.red, &var->red, sizeof(var->red)) || - memcmp(&dsp->var.green, &var->green, sizeof(var->green)) || - memcmp(&dsp->var.blue, &var->blue, sizeof(var->blue))); - } - - memcpy (&v, var, sizeof (v)); - - switch (v.bits_per_pixel) { -#ifdef FBCON_HAS_MFB - case 1: - dsp->dispsw = &fbcon_mfb; - dsp->line_length = v.xres_virtual / 8; - dsp->visual = FB_VISUAL_MONO10; - nom = 4; - den = 8; - break; -#endif - -#ifdef FBCON_HAS_CFB8 - case 2 ... 8: - v.bits_per_pixel = 8; - dsp->dispsw = &fbcon_cfb8; - nom = 1; - den = 1; - dsp->line_length = v.xres_virtual; - dsp->visual = FB_VISUAL_PSEUDOCOLOR; - v.red.offset = 0; - v.red.length = 6; - v.green.offset = 0; - v.green.length = 6; - v.blue.offset = 0; - v.blue.length = 6; - break; -#endif - -#ifdef FBCON_HAS_CFB16 - case 9 ... 16: - v.bits_per_pixel = 16; - dsp->dispsw = &fbcon_cfb16; - dsp->dispsw_data = &rivainfo->con_cmap.cfb16; - nom = 2; - den = 1; - dsp->line_length = v.xres_virtual * 2; - dsp->visual = FB_VISUAL_DIRECTCOLOR; -#ifdef CONFIG_PREP - v.red.offset = 2; - v.green.offset = -3; - v.blue.offset = 8; -#else - v.red.offset = 10; - v.green.offset = 5; - v.blue.offset = 0; -#endif - v.red.length = 5; - v.green.length = 5; - v.blue.length = 5; - break; -#endif - -#ifdef FBCON_HAS_CFB32 - case 17 ... 32: - v.bits_per_pixel = 32; - dsp->dispsw = &fbcon_cfb32; - dsp->dispsw_data = rivainfo->con_cmap.cfb32; - nom = 4; - den = 1; - dsp->line_length = v.xres_virtual * 4; - dsp->visual = FB_VISUAL_DIRECTCOLOR; -#ifdef CONFIG_PREP - v.red.offset = 8; - v.green.offset = 16; - v.blue.offset = 24; -#else - v.red.offset = 16; - v.green.offset = 8; - v.blue.offset = 0; -#endif - v.red.length = 8; - v.green.length = 8; - v.blue.length = 8; - break; -#endif - - default: - printk (KERN_ERR PFX "mode %dx%dx%d rejected...color depth not supported.\n", - var->xres, var->yres, var->bits_per_pixel); - DPRINTK ("EXIT, returning -EINVAL\n"); - return -EINVAL; - } - - if (v.xres * nom / den * v.yres > rivainfo->ram_amount) { - printk (KERN_ERR PFX "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", - var->xres, var->yres, var->bits_per_pixel); - DPRINTK ("EXIT - EINVAL error\n"); - return -EINVAL; - } - - /* use highest possible virtual resolution */ - if (v.xres_virtual == -1 && - v.yres_virtual == -1) { - printk (KERN_WARNING PFX "using maximum available virtual resolution\n"); - for (i = 0; modes[i].xres != -1; i++) { - if (modes[i].xres * nom / den * modes[i].yres < rivainfo->ram_amount / 2) - break; - } - if (modes[i].xres == -1) { - printk (KERN_ERR PFX "could not find a virtual resolution that fits into video memory!!\n"); - DPRINTK ("EXIT - EINVAL error\n"); - return -EINVAL; - } - v.xres_virtual = modes[i].xres; - v.yres_virtual = modes[i].yres; - - printk (KERN_INFO PFX "virtual resolution set to maximum of %dx%d\n", - v.xres_virtual, v.yres_virtual); - } else if (v.xres_virtual == -1) { - /* FIXME: maximize X virtual resolution only */ - } else if (v.yres_virtual == -1) { - /* FIXME: maximize Y virtual resolution only */ - } - - if (v.xoffset < 0) - v.xoffset = 0; - if (v.yoffset < 0) - v.yoffset = 0; - - /* truncate xoffset and yoffset to maximum if too high */ - if (v.xoffset > v.xres_virtual - v.xres) - v.xoffset = v.xres_virtual - v.xres - 1; - - if (v.yoffset > v.yres_virtual - v.yres) - v.yoffset = v.yres_virtual - v.yres - 1; - - v.red.msb_right = - v.green.msb_right = - v.blue.msb_right = - v.transp.offset = - v.transp.length = - v.transp.msb_right = 0; - - switch (v.activate & FB_ACTIVATE_MASK) { - case FB_ACTIVATE_TEST: - DPRINTK ("EXIT - FB_ACTIVATE_TEST\n"); - return 0; - case FB_ACTIVATE_NXTOPEN: /* ?? */ - case FB_ACTIVATE_NOW: - break; /* continue */ - default: - DPRINTK ("EXIT - unknown activation type\n"); - return -EINVAL; /* unknown */ - } - - dsp->type = FB_TYPE_PACKED_PIXELS; - -#warning FIXME: verify that the above code sets dsp->* fields correctly - - memcpy (&dsp->var, &v, sizeof (v)); - - riva_load_video_mode (rivainfo, &v); - - if (chgvar && info && info->changevar) - info->changevar (con); - - DPRINTK ("EXIT, returning 0\n"); - return 0; -} - - - -/** - * rivafb_get_cmap - * @cmap: - * @kspc: - * @con: - * @info: - * - * DESCRIPTION: - * - * NOTES: - * Copied from matroxfb::matroxfb_get_cmap() - */ - -int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - struct display *dsp; - - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); - assert (cmap != NULL); - - dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - - if (con == rivainfo->currcon) { /* current console? */ - int rc = fb_get_cmap (cmap, kspc, riva_getcolreg, info); - DPRINTK ("EXIT - returning %d\n", rc); - return rc; - } else if (dsp->cmap.len) /* non default colormap? */ - fb_copy_cmap (&dsp->cmap, cmap, kspc ? 0 : 2); - else - fb_copy_cmap (fb_default_cmap (riva_get_cmap_len (&dsp->var)), - cmap, kspc ? 0 : 2); - - DPRINTK ("EXIT, returning 0\n"); - - return 0; -} - - -/** - * rivafb_set_cmap - * @cmap: - * @kspc: - * @con: - * @info: - * - * DESCRIPTION: - * - * NOTES: - * Copied from matroxfb::matroxfb_set_cmap() - */ - -int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - struct display *dsp; - unsigned int cmap_len; - - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); - assert (cmap != NULL); - - dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - - cmap_len = riva_get_cmap_len (&dsp->var); - if (dsp->cmap.len != cmap_len) { - int err = fb_alloc_cmap (&dsp->cmap, cmap_len, 0); - if (err) { - DPRINTK ("EXIT - returning %d\n", err); - return err; - } - } - if (con == rivainfo->currcon) { /* current console? */ - int rc = fb_set_cmap (cmap, kspc, riva_setcolreg, info); - DPRINTK ("EXIT - returning %d\n", rc); - return rc; - } else - fb_copy_cmap (cmap, &dsp->cmap, kspc ? 0 : 1); - - DPRINTK ("EXIT, returning 0\n"); - - return 0; -} - - - -/** - * rivafb_pan_display - * @var: standard kernel fb changeable data - * @par: riva-specific hardware info about current video mode - * @info: pointer to rivafb_info object containing info for current riva board - * - * DESCRIPTION: - * Pan (or wrap, depending on the `vmode' field) the display using the - * `xoffset' and `yoffset' fields of the `var' structure. - * If the values don't fit, return -EINVAL. - * - * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag - */ - -int rivafb_pan_display (struct fb_var_screeninfo *var, int con, - struct fb_info *info) -{ - unsigned int base; - struct display *dsp; - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); - - if (var->xoffset > (var->xres_virtual - var->xres)) - return -EINVAL; - if (var->yoffset > (var->yres_virtual - var->yres)) - return -EINVAL; - - dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - - if (var->vmode & FB_VMODE_YWRAP) { - if (var->yoffset < 0 || var->yoffset >= dsp->var.yres_virtual || var->xoffset) - return -EINVAL; - } else { - if (var->xoffset+dsp->var.xres > dsp->var.xres_virtual || - var->yoffset+dsp->var.yres > dsp->var.yres_virtual) - return -EINVAL; - } - - base = var->yoffset * dsp->line_length + var->xoffset; - - if (con == rivainfo->currcon) { - /* FIXME: do the dirty deed */ - } - - dsp->var.xoffset = var->xoffset; - dsp->var.yoffset = var->yoffset; - - if (var->vmode & FB_VMODE_YWRAP) - dsp->var.vmode |= FB_VMODE_YWRAP; - else - dsp->var.vmode &= ~FB_VMODE_YWRAP; - - DPRINTK ("EXIT, returning 0\n"); - - return 0; -} - - - -/** - * rivafb_ioctl - * @inode: - * @file: - * @cmd: - * @arg: - * @con: - * @info: - * - * DESCRIPTION: - */ - -int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg, int con, struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); - - /* no rivafb-specific ioctls */ - - DPRINTK ("EXIT, returning -EINVAL\n"); - - return -EINVAL; -} - - - - -/** - * rivafb_switch - * @con: - * @info: - * - * DESCRIPTION: - */ - -int rivafb_switch(int con, struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - struct fb_cmap* cmap; - struct display *dsp; - - DPRINTK("ENTER\n"); - - assert (rivainfo != NULL); - - dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - - if (rivainfo->currcon >= 0) { - /* Do we have to save the colormap? */ - cmap = &(rivainfo->currcon_display->cmap); - DPRINTK("switch1: con = %d, cmap.len = %d\n", rivainfo->currcon, cmap->len); - - if (cmap->len) { - DPRINTK("switch1a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp); - fb_get_cmap(cmap, 1, riva_getcolreg, info); -#ifdef DEBUG - if (cmap->red) { - DPRINTK("switch1r: %X\n", cmap->red[0]); - } -#endif - } - } - rivainfo->currcon = con; - rivainfo->currcon_display = dsp; - dsp->var.activate = FB_ACTIVATE_NOW; - -#ifdef riva_DEBUG - cmap = &dsp->cmap; - DPRINTK("switch2: con = %d, cmap.len = %d\n", con, cmap->len); - DPRINTK("switch2a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp); - if (dsp->cmap.red) { - DPRINTK("switch2r: %X\n", cmap->red[0]); - } -#endif - - rivafb_set_var(&dsp->var, con, info); - -#ifdef riva_DEBUG - DPRINTK("switch3: con = %d, cmap.len = %d\n", con, cmap->len); - DPRINTK("switch3a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp); - if (dsp->cmap.red) { - DPRINTK("switch3r: %X\n", cmap->red[0]); - } -#endif - - DPRINTK("EXIT, returning 0\n"); - - return 0; -} - - - -void rivafb_blank (int blank, struct fb_info *info) -{ - unsigned char tmp; - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); - - tmp = vga_io_rseq (VGA_SEQ_CLOCK_MODE) & ~VGA_SR01_SCREEN_OFF; - - if (blank) - tmp |= VGA_SR01_SCREEN_OFF; - - vga_io_wseq (VGA_SEQ_CLOCK_MODE, tmp); - - DPRINTK("EXIT\n"); -} - - -/* ------------------------------------------------------------------------- - * - * internal fb_ops helper functions - * - * ------------------------------------------------------------------------- - */ - - -/** - * riva_get_cmap_len - * @var: - * - * DESCRIPTION: - */ - -static int riva_get_cmap_len(const struct fb_var_screeninfo *var) -{ - int rc = 16; /* reasonable default */ - - assert (var != NULL); - - switch (var->bits_per_pixel) { -#ifdef FBCON_HAS_CFB4 - case 4: - rc = 16; /* pseudocolor... 16 entries HW palette */ - break; -#endif -#ifdef FBCON_HAS_CFB8 - case 8: - rc = 256; /* pseudocolor... 256 entries HW palette */ - break; -#endif -#ifdef FBCON_HAS_CFB16 - case 16: - rc = 16; /* directcolor... 16 entries SW palette */ - break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ -#endif -#ifdef FBCON_HAS_CFB32 - case 32: - rc = 16; /* directcolor... 16 entries SW palette */ - break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ -#endif - default: - assert (0); - /* should not occur */ - break; - } - - return rc; -} - - -/** - * riva_getcolreg - * @regno: - * @red: - * @green: - * @blue: - * @transp: - * @info: pointer to rivafb_info object containing info for current riva board - * - * DESCRIPTION: - * Read a single color register and split it into colors/transparent. - * The return values must have a 16 bit magnitude. - * Return != 0 for invalid regno. - * - * CALLED FROM: - * fbcmap.c:fb_get_cmap() - * fbgen.c:fbgen_get_cmap() - * fbgen.c:fbgen_switch() - */ - -static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green, - unsigned *blue, unsigned *transp, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - - if (regno > 255) - return 1; - *red = rivainfo->palette[regno].red; - *green = rivainfo->palette[regno].green; - *blue = rivainfo->palette[regno].blue; - *transp = 0; - return 0; -} - - -/** - * riva_setcolreg - * @regno: - * @red: - * @green: - * @blue: - * @transp: - * @info: pointer to rivafb_info object containing info for current riva board - * - * DESCRIPTION: - * Set a single color register. The values supplied have a 16 bit - * magnitude. - * Return != 0 for invalid regno. - * - * CALLED FROM: - * fbcmap.c:fb_set_cmap() - * fbgen.c:fbgen_get_cmap() - * fbgen.c:fbgen_install_cmap() - * fbgen.c:fbgen_set_var() - * fbgen.c:fbgen_switch() - * fbgen.c:fbgen_blank() - * fbgen.c:fbgen_blank() - */ - -static int riva_setcolreg (unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - struct display *p; - - DPRINTK("ENTER\n"); - - assert (rivainfo != NULL); - assert (rivainfo->currcon_display != NULL); - - if (regno > 255) - return -EINVAL; - - p = rivainfo->currcon_display; - if (p->var.grayscale) { - /* gray = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; - } - -#ifdef FBCON_HAS_CFB8 - switch (p->var.bits_per_pixel) { - case 8: - /* "transparent" stuff is completely ignored. */ - riva_wclut (regno, red >> 10, green >> 10, blue >> 10); - break; - default: - /* do nothing */ - break; - } -#endif /* FBCON_HAS_CFB8 */ - - rivainfo->palette[regno].red = red; - rivainfo->palette[regno].green = green; - rivainfo->palette[regno].blue = blue; - - if (regno >= 16) - return 0; - - switch (p->var.bits_per_pixel) { - -#ifdef FBCON_HAS_CFB16 - case 16: - assert (regno < 16); -#ifdef CONFIG_PREP - rivainfo->con_cmap.cfb16[regno] = - ((red & 0xf800) >> 9) | - ((green & 0xf800) >> 14) | - ((green & 0xf800) << 2) | - ((blue & 0xf800) >> 3); -#else - rivainfo->con_cmap.cfb16[regno] = - ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | - ((blue & 0xf800) >> 11); -#endif - break; -#endif /* FBCON_HAS_CFB16 */ - -#ifdef FBCON_HAS_CFB32 - case 32: - assert (regno < 16); -#ifdef CONFIG_PREP - rivainfo->con_cmap.cfb32[regno] = - ((red & 0xff00)) | - ((green & 0xff00) << 8) | - ((blue & 0xff00) << 16); -#else - rivainfo->con_cmap.cfb32[regno] = - ((red & 0xff00) << 8) | - ((green & 0xff00)) | - ((blue & 0xff00) >> 8); -#endif - break; -#endif /* FBCON_HAS_CFB32 */ - - default: - /* do nothing */ - break; - } - - return 0; -} - - - -/* - * riva_load_video_mode() - * - * calculate some timings and then send em off to riva_load_state() - */ - -static void riva_load_video_mode (struct rivafb_info *rinfo, - struct fb_var_screeninfo *video_mode) -{ - struct riva_regs newmode; - int bpp, width, hDisplaySize, hDisplay, hStart, - hEnd, hTotal, height, vDisplay, vStart, - vEnd, vTotal, dotClock; - - /* time to calculate */ - - bpp = video_mode->bits_per_pixel; - width = hDisplaySize = video_mode->xres; - hDisplay = (hDisplaySize/8) - 1; - hStart = (hDisplaySize + video_mode->right_margin)/8 + 2; - hEnd = (hDisplaySize + video_mode->right_margin + - video_mode->hsync_len)/8 - 1; - hTotal = (hDisplaySize + video_mode->right_margin + - video_mode->hsync_len + video_mode->left_margin)/8 - 1; - height = video_mode->yres; - vDisplay = video_mode->yres - 1; - vStart = video_mode->yres + video_mode->lower_margin - 1; - vEnd = video_mode->yres + video_mode->lower_margin + - video_mode->vsync_len - 1; - vTotal = video_mode->yres + video_mode->lower_margin + - video_mode->vsync_len + video_mode->upper_margin + 2; - dotClock = 1000000000 / video_mode->pixclock; - - memcpy(&newmode, ®_template, sizeof(struct riva_regs)); - - newmode.crtc[0x0] = Set8Bits(hTotal - 4); - newmode.crtc[0x1] = Set8Bits(hDisplay); - newmode.crtc[0x2] = Set8Bits(hDisplay); - newmode.crtc[0x3] = SetBitField(hTotal,4:0,4:0) | SetBit(7); - newmode.crtc[0x4] = Set8Bits(hStart); - newmode.crtc[0x5] = SetBitField(hTotal,5:5,7:7) - | SetBitField(hEnd,4:0,4:0); - newmode.crtc[0x6] = SetBitField(vTotal,7:0,7:0); - newmode.crtc[0x7] = SetBitField(vTotal,8:8,0:0) - | SetBitField(vDisplay,8:8,1:1) - | SetBitField(vStart,8:8,2:2) - | SetBitField(vDisplay,8:8,3:3) - | SetBit(4) - | SetBitField(vTotal,9:9,5:5) - | SetBitField(vDisplay,9:9,6:6) - | SetBitField(vStart,9:9,7:7); - newmode.crtc[0x9] = SetBitField(vDisplay,9:9,5:5) - | SetBit(6); - newmode.crtc[0x10] = Set8Bits(vStart); - newmode.crtc[0x11] = SetBitField(vEnd,3:0,3:0) - | SetBit(5); - newmode.crtc[0x12] = Set8Bits(vDisplay); - newmode.crtc[0x13] = ((width/8)*(bpp/8)) & 0xFF; - newmode.crtc[0x15] = Set8Bits(vDisplay); - newmode.crtc[0x16] = Set8Bits(vTotal + 1); - - newmode.ext.bpp = bpp; - newmode.ext.width = width; - newmode.ext.height = height; - - rinfo->riva.CalcStateExt(&rinfo->riva,&newmode.ext,bpp,width, - hDisplaySize,hDisplay,hStart,hEnd,hTotal, - height,vDisplay,vStart,vEnd,vTotal,dotClock); - - rinfo->initial_state = newmode; - riva_load_state(rinfo,&newmode); -} - - - - - -/* ------------------------------------------------------------------------- */ - - - /* - * Modularization - */ - -#ifdef MODULE -int __init init_module(void) -{ - return rivafb_init(); -} - -void __exit cleanup_module(void) -{ - struct rivafb_info *tmp, *board = riva_boards; - - while (board != NULL) { - riva_load_state (board, &board->initial_state); - - unregister_framebuffer ((struct fb_info *) board); - - tmp = board; - iounmap (tmp->ctrl_base); - iounmap (tmp->fb_base); - board = board->next; - - kfree (tmp); - } -} -#endif /* MODULE */ - - - - - -/* from GGI */ -static -void riva_save_state(struct rivafb_info *rinfo, struct riva_regs *regs) -{ - int i; - - io_out8(NV_CIO_SR_LOCK_INDEX, 0x3D4); - io_out8(NV_CIO_SR_UNLOCK_RW_VALUE, 0x3D5); - - rinfo->riva.UnloadStateExt(&rinfo->riva, ®s->ext); - - regs->misc_output = io_in8(0x3CC); - - for (i = 0; i < NUM_CRT_REGS; i++) - { - io_out8(i, 0x3D4); - regs->crtc[i] = io_in8(0x3D5); - } - - for (i = 0; i < NUM_ATC_REGS; i++) - { - io_out8(i, 0x3C0); - regs->attr[i] = io_in8(0x3C1); - } - - for (i = 0; i < NUM_GRC_REGS; i++) - { - io_out8(i, 0x3CE); - regs->gra[i] = io_in8(0x3CF); - } - - - for (i = 0; i < NUM_SEQ_REGS; i++) - { - io_out8(i, 0x3C4); - regs->seq[i] = io_in8(0x3C5); - } -} - - -/* from GGI */ -static -void riva_load_state(struct rivafb_info *rinfo, struct riva_regs *regs) -{ - int i; - RIVA_HW_STATE *state = ®s->ext; - - io_out8(0x11, 0x3D4); - io_out8(0x00, 0x3D5); - - io_out8(NV_CIO_SR_LOCK_INDEX, 0x3D4); - io_out8(NV_CIO_SR_UNLOCK_RW_VALUE, 0x3D5); - - rinfo->riva.LoadStateExt(&rinfo->riva,state); - - io_out8(regs->misc_output, 0x3C2); - - for (i = 0; i < NUM_CRT_REGS; i++) - { - if (i < 0x19) - { - io_out8(i, 0x3D4); - io_out8(regs->crtc[i], 0x3D5); - } - else - { - switch (i) - { - case 0x19: - case 0x20: - case 0x21: - case 0x22: - case 0x23: - case 0x24: - case 0x25: - case 0x26: - case 0x27: -#if 0 - case 0x28: -#endif - case 0x29: - case 0x2a: - case 0x2b: - case 0x2c: - case 0x2d: - case 0x2e: - case 0x2f: - case 0x30: - case 0x31: - case 0x32: - case 0x33: - case 0x34: - case 0x35: - case 0x36: - case 0x37: - case 0x38: - case 0x39: - case 0x3a: - case 0x3b: - case 0x3c: - case 0x3d: - case 0x3e: - case 0x3f: -#if 0 - case 0x40: -#endif - break; - default: - io_out8(i, 0x3D4); - io_out8(regs->crtc[i], 0x3D5); - } - } - } - - for (i = 0; i < NUM_ATC_REGS; i++) - { - io_out8(i, 0x3C0); - io_out8(regs->attr[i], 0x3C1); - } - - for (i = 0; i < NUM_GRC_REGS; i++) - { - io_out8(i, 0x3CE); - io_out8(regs->gra[i], 0x3CF); - } - - for (i = 0; i < NUM_SEQ_REGS; i++) - { - io_out8(i, 0x3C4); - io_out8(regs->seq[i], 0x3C5); - } -} - - - - -/** - * riva_board_list_add - * @board_list: Root node of list of boards - * @new_node: New node to be added - * - * DESCRIPTION: - * Adds @new_node to the list referenced by @board_list - * - * RETURNS: - * New root node - */ -static -struct rivafb_info *riva_board_list_add(struct rivafb_info *board_list, - struct rivafb_info *new_node) -{ - struct rivafb_info *i_p = board_list; - - new_node->next = NULL; - - if (board_list == NULL) - return new_node; - - while (i_p->next != NULL) - i_p = i_p->next; - i_p->next = new_node; - - return board_list; -} - diff --git a/drivers/video/vga_font.c b/drivers/video/vga_font.c index bed9a5e95..d6683ee4b 100644 --- a/drivers/video/vga_font.c +++ b/drivers/video/vga_font.c @@ -1,5 +1,6 @@ #include <linux/kernel.h> #include <linux/module.h> +#include <linux/modversions.h> #define cmapsz 8192 |