diff options
Diffstat (limited to 'include/asm-alpha')
| -rw-r--r-- | include/asm-alpha/a.out.h | 3 | ||||
| -rw-r--r-- | include/asm-alpha/apecs.h | 18 | ||||
| -rw-r--r-- | include/asm-alpha/cache.h | 8 | ||||
| -rw-r--r-- | include/asm-alpha/dma.h | 2 | ||||
| -rw-r--r-- | include/asm-alpha/elf.h | 40 | ||||
| -rw-r--r-- | include/asm-alpha/fpu.h | 34 | ||||
| -rw-r--r-- | include/asm-alpha/hardirq.h | 1 | ||||
| -rw-r--r-- | include/asm-alpha/hwrpb.h | 21 | ||||
| -rw-r--r-- | include/asm-alpha/io.h | 4 | ||||
| -rw-r--r-- | include/asm-alpha/ioctls.h | 2 | ||||
| -rw-r--r-- | include/asm-alpha/irq.h | 13 | ||||
| -rw-r--r-- | include/asm-alpha/lca.h | 31 | ||||
| -rw-r--r-- | include/asm-alpha/mman.h | 6 | ||||
| -rw-r--r-- | include/asm-alpha/pal.h | 3 | ||||
| -rw-r--r-- | include/asm-alpha/processor.h | 5 | ||||
| -rw-r--r-- | include/asm-alpha/pyxis.h | 436 | ||||
| -rw-r--r-- | include/asm-alpha/signal.h | 9 | ||||
| -rw-r--r-- | include/asm-alpha/smp.h | 2 | ||||
| -rw-r--r-- | include/asm-alpha/socket.h | 6 | ||||
| -rw-r--r-- | include/asm-alpha/softirq.h | 54 | ||||
| -rw-r--r-- | include/asm-alpha/t2.h | 508 | ||||
| -rw-r--r-- | include/asm-alpha/types.h | 2 | ||||
| -rw-r--r-- | include/asm-alpha/unistd.h | 51 |
23 files changed, 1178 insertions, 81 deletions
diff --git a/include/asm-alpha/a.out.h b/include/asm-alpha/a.out.h index f1965d5ca..073b90a99 100644 --- a/include/asm-alpha/a.out.h +++ b/include/asm-alpha/a.out.h @@ -90,7 +90,8 @@ struct exec #ifdef __KERNEL__ -#define STACK_TOP (0x00120000000UL) +#define STACK_TOP \ + ((current->personality==PER_LINUX_32BIT) ? (0x80000000) : (0x00120000000UL)) #endif diff --git a/include/asm-alpha/apecs.h b/include/asm-alpha/apecs.h index 0f38c8aac..161813515 100644 --- a/include/asm-alpha/apecs.h +++ b/include/asm-alpha/apecs.h @@ -31,7 +31,7 @@ BIOS ROMs. So we must put the windows high enough to avoid these areas. We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1, - and window 2 at BUS 512Mb for 512Mb, mapping physical 0 to 512Mb-1. + and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1. Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually be used for that range (via virt_to_bus()). @@ -53,12 +53,14 @@ DMAable memory; they count on being able to DMA to any memory they get from kmalloc()/get_free_pages(). They will also use window 1 for any physical memory accesses below 64Mb; the rest will be handled by - window 2, maxing out at 512Mb of memory. I trust this is enough... :-) + window 2, maxing out at 1Gb of memory. I trust this is enough... :-) - Finally, the reason we make window 2 start at 512Mb for 512Mb, is so that - we can allocate PCI bus devices' memory starting at 1Gb and up, to ensure - that no conflicts occur and bookkeeping is simplified (ie we don't - try to fill the gap between the two windows, we just go above the top). + We hope that the area before the first window is large enough so that + there will be no overlap at the top end (64Mb). We *must* locate the + PCI cards' memory just below window 1, so that there's still the + possibility of being able to access it via SPARSE space. This is + important for cards such as the Matrox Millennium, whose Xserver + wants to access memory-mapped registers in byte and short lengths. Note that the XL is treated differently from the AVANTI, even though for most other things they are identical. It didn't seem reasonable to @@ -69,8 +71,8 @@ #define APECS_XL_DMA_WIN1_BASE (64*1024*1024) #define APECS_XL_DMA_WIN1_SIZE (64*1024*1024) #define APECS_XL_DMA_WIN1_SIZE_PARANOID (48*1024*1024) -#define APECS_XL_DMA_WIN2_BASE (512*1024*1024) -#define APECS_XL_DMA_WIN2_SIZE (512*1024*1024) +#define APECS_XL_DMA_WIN2_BASE (1024*1024*1024) +#define APECS_XL_DMA_WIN2_SIZE (1024*1024*1024) #else /* CONFIG_ALPHA_XL */ diff --git a/include/asm-alpha/cache.h b/include/asm-alpha/cache.h index c1276cb1e..c9b94b76b 100644 --- a/include/asm-alpha/cache.h +++ b/include/asm-alpha/cache.h @@ -4,9 +4,9 @@ #ifndef __ARCH_ALPHA_CACHE_H #define __ARCH_ALPHA_CACHE_H -/* bytes per L1 cache line */ -#define L1_CACHE_BYTES 32 /* a guess */ - -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) +/* Bytes per L1 (data) cache line. Both EV4 and EV5 are write-through, + read-allocate, direct-mapped, physical. */ +#define L1_CACHE_BYTES 32 +#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #endif diff --git a/include/asm-alpha/dma.h b/include/asm-alpha/dma.h index b5c3c1c7c..d8077298d 100644 --- a/include/asm-alpha/dma.h +++ b/include/asm-alpha/dma.h @@ -313,5 +313,7 @@ static __inline__ int get_dma_residue(unsigned int dmanr) /* These are in kernel/dma.c: */ extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ +#define KERNEL_HAVE_CHECK_DMA +extern int check_dma(unsigned int dmanr); #endif /* _ASM_DMA_H */ diff --git a/include/asm-alpha/elf.h b/include/asm-alpha/elf.h index eb5df17f6..89657ba78 100644 --- a/include/asm-alpha/elf.h +++ b/include/asm-alpha/elf.h @@ -1,5 +1,5 @@ -#ifndef __ASMaxp_ELF_H -#define __ASMaxp_ELF_H +#ifndef __ASM_ALPHA_ELF_H +#define __ASM_ALPHA_ELF_H /* * ELF register definitions.. @@ -39,7 +39,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) +#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x1000000) /* $0 is set by ld.so to a pointer to a function which might be registered using atexit. This provides a mean for the dynamic @@ -98,4 +98,38 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; _dest[32] = _dump.regs[EF_PS]; \ } +/* This yields a mask that user programs can use to figure out what + instruction set this cpu supports. This is trivial on Alpha, + but not so on other machines. */ + +#define ELF_HWCAP \ +({ \ + /* Sadly, most folks don't yet have assemblers that know about \ + amask. This is "amask v0, v0" */ \ + register long _v0 __asm("$0") = -1; \ + __asm(".long 0x47e00c20" : "=r"(_v0) : "0"(_v0)); \ + ~_v0; \ +}) + +/* This yields a string that ld.so will use to load implementation + specific libraries for optimization. This is more specific in + intent than poking at uname or /proc/cpuinfo. + + This might do with checking bwx simultaneously... */ + +#define ELF_PLATFORM \ +({ \ + /* Or "implver v0" ... */ \ + register long _v0 __asm("$0"); \ + __asm(".long 0x47e03d80" : "=r"(_v0)); \ + _v0 == 0 ? "ev4" : "ev5"; \ +}) + +#ifdef __KERNEL__ +#define SET_PERSONALITY(EX, IBCS2) \ + current->personality = \ + ((EX).e_flags & EF_ALPHA_32BIT \ + ? PER_LINUX_32BIT : (IBCS2) ? PER_SVR4 : PER_LINUX) +#endif + #endif diff --git a/include/asm-alpha/fpu.h b/include/asm-alpha/fpu.h index 25148b14b..ab9b28f6e 100644 --- a/include/asm-alpha/fpu.h +++ b/include/asm-alpha/fpu.h @@ -81,4 +81,38 @@ ieee_swcr_to_fpcr(unsigned long sw) return fp; } +#ifdef __KERNEL__ + +/* The following two functions don't need trapb/excb instructions + around the mf_fpcr/mt_fpcr instructions because (a) the kernel + never generates arithmetic faults and (b) call_pal instructions + are implied trap barriers. */ + +static inline unsigned long rdfpcr(void) +{ + unsigned long tmp, ret; + __asm__ ("stt $f0,%0\n\t" + "mf_fpcr $f0\n\t" + "stt $f0,%1\n\t" + "ldt $f0,%0" + : "=m"(tmp), "=m"(ret)); + return ret; +} + +static inline void wrfpcr(unsigned long val) +{ + unsigned long tmp; + __asm__ __volatile__ ( + "stt $f0,%0\n\t" + "ldt $f0,%1\n\t" + "mt_fpcr $f0\n\t" + "ldt $f0,%0" + : "=m"(tmp) : "m"(val)); +} + +extern unsigned long alpha_read_fp_reg (unsigned long reg); +extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); + +#endif /* __KERNEL__ */ + #endif /* __ASM_ALPHA_FPU_H */ diff --git a/include/asm-alpha/hardirq.h b/include/asm-alpha/hardirq.h index 79bf079ed..733216be9 100644 --- a/include/asm-alpha/hardirq.h +++ b/include/asm-alpha/hardirq.h @@ -4,7 +4,6 @@ #include <linux/tasks.h> extern unsigned int local_irq_count[NR_CPUS]; -#define in_interrupt() (local_irq_count[smp_processor_id()] != 0) #ifndef __SMP__ diff --git a/include/asm-alpha/hwrpb.h b/include/asm-alpha/hwrpb.h index 662aa35f6..4f6c5d01e 100644 --- a/include/asm-alpha/hwrpb.h +++ b/include/asm-alpha/hwrpb.h @@ -15,6 +15,8 @@ #define EV45_CPU 6 /* EV4.5 (21064/xxx) */ #define EV56_CPU 7 /* EV5.6 (21164) */ #define EV6_CPU 8 /* EV6 (21164) */ +#define PCA56_CPU 9 /* PCA56 (21164PC) */ +#define PCA57_CPU 10 /* PCA57 (??) */ /* * DEC system types for Alpha systems. Found in HWRPB. @@ -39,7 +41,26 @@ #define ST_DEC_EB64P 20 /* EB64+ systype */ #define ST_DEC_EB66P -19 /* EB66 systype */ #define ST_DEC_EBPC64 -20 /* Cabriolet (AlphaPC64) systype */ +#define ST_DEC_BURNS 21 /* Laptop systype */ +#define ST_DEC_RAWHIDE 22 /* Rawhide systype */ +#define ST_DEC_K2 23 /* K2 systype */ +#define ST_DEC_LYNX 24 /* Lynx systype */ +#define ST_DEC_XL 25 /* Alpha XL systype */ #define ST_DEC_EB164 26 /* EB164 systype */ +#define ST_DEC_NORITAKE 27 /* Noritake systype */ +#define ST_DEC_CORTEX 28 /* Cortex systype */ +#define ST_DEC_MIATA 30 /* MIATA systype */ +#define ST_DEC_XXM 31 /* XXM systype */ +#define ST_DEC_TAKARA 32 /* Takara systype */ +#define ST_DEC_YUKON 33 /* Yukon systype */ +#define ST_DEC_TSUNAMI 34 /* Tsunami systype */ +#define ST_DEC_WILDFIRE 35 /* Wildfire systype */ +#define ST_DEC_CUSCO 36 /* CUSCO systype */ + +/* UNOFFICIAL!!! */ +#define ST_UNOFFICIAL_BIAS 100 +#define ST_DTI_RUFFIAN 101 /* RUFFIAN systype */ + struct pcb_struct { unsigned long ksp; diff --git a/include/asm-alpha/io.h b/include/asm-alpha/io.h index a81f5289e..da03e68db 100644 --- a/include/asm-alpha/io.h +++ b/include/asm-alpha/io.h @@ -80,6 +80,10 @@ extern void _sethae (unsigned long addr); /* cached version */ # include <asm/apecs.h> /* get chip-specific definitions */ #elif defined(CONFIG_ALPHA_CIA) # include <asm/cia.h> /* get chip-specific definitions */ +#elif defined(CONFIG_ALPHA_T2) +# include <asm/t2.h> /* get chip-specific definitions */ +#elif defined(CONFIG_ALPHA_PYXIS) +# include <asm/pyxis.h> /* get chip-specific definitions */ #else # include <asm/jensen.h> #endif diff --git a/include/asm-alpha/ioctls.h b/include/asm-alpha/ioctls.h index 203bde501..2a065c5b6 100644 --- a/include/asm-alpha/ioctls.h +++ b/include/asm-alpha/ioctls.h @@ -86,6 +86,8 @@ #define TIOCSBRK 0x5427 /* BSD compatibility */ #define TIOCCBRK 0x5428 /* BSD compatibility */ #define TIOCGSID 0x5429 /* Return the session ID of FD */ +#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ #define TIOCSERCONFIG 0x5453 #define TIOCSERGWILD 0x5454 diff --git a/include/asm-alpha/irq.h b/include/asm-alpha/irq.h index c1f6939c0..5c81ff6a3 100644 --- a/include/asm-alpha/irq.h +++ b/include/asm-alpha/irq.h @@ -10,12 +10,19 @@ #include <linux/linkage.h> #include <linux/config.h> -#if defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB66P) || defined(CONFIG_ALPHA_EB164) || defined(CONFIG_ALPHA_PC164) +#if defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB66P) || \ + defined(CONFIG_ALPHA_EB164) || defined(CONFIG_ALPHA_PC164) || \ + defined(CONFIG_ALPHA_LX164) # define NR_IRQS 33 -#elif defined(CONFIG_ALPHA_EB66) || defined(CONFIG_ALPHA_EB64P) || defined(CONFIG_ALPHA_MIKASA) +#elif defined(CONFIG_ALPHA_EB66) || defined(CONFIG_ALPHA_EB64P) || \ + defined(CONFIG_ALPHA_MIKASA) # define NR_IRQS 32 -#elif defined(CONFIG_ALPHA_ALCOR) || defined(CONFIG_ALPHA_XLT) +#elif defined(CONFIG_ALPHA_ALCOR) || defined(CONFIG_ALPHA_XLT) || \ + defined(CONFIG_ALPHA_MIATA) || defined(CONFIG_ALPHA_NORITAKE) || \ + defined(CONFIG_ALPHA_RUFFIAN) # define NR_IRQS 48 +#elif defined(CONFIG_ALPHA_SABLE) || defined(CONFIG_ALPHA_SX164) +# define NR_IRQS 40 #else # define NR_IRQS 16 #endif diff --git a/include/asm-alpha/lca.h b/include/asm-alpha/lca.h index 43c6e9eca..1eb35a2e4 100644 --- a/include/asm-alpha/lca.h +++ b/include/asm-alpha/lca.h @@ -130,6 +130,37 @@ #define HAE_ADDRESS LCA_IOC_HAE +/* LCA PMR Power Management register defines */ +#define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL) +#define LCA_PMR_PDIV 0x7 /* Primary clock divisor */ +#define LCA_PMR_ODIV 0x38 /* Override clock divisor */ +#define LCA_PMR_INTO 0x40 /* Interrupt override */ +#define LCA_PMR_DMAO 0x80 /* DMA override */ +#define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even + bits */ +#define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even + bits */ +#define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8 +/* LCA PMR Macros */ + +#define READ_PMR (*(volatile unsigned long *)LCA_PMR_ADDR) +#define WRITE_PMR(d) (*((volatile unsigned long *)LCA_PMR_ADDR) = (d)) + +#define GET_PRIMARY(r) ((r) & LCA_PMR_PDIV) +#define GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV) +#define SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK) | (c))) + +/* LCA PMR Divisor values */ +#define DIV_1 0x0 +#define DIV_1_5 0x1 +#define DIV_2 0x2 +#define DIV_4 0x3 +#define DIV_8 0x4 +#define DIV_16 0x5 +#define DIV_MIN DIV_1 +#define DIV_MAX DIV_16 + + #ifdef __KERNEL__ /* diff --git a/include/asm-alpha/mman.h b/include/asm-alpha/mman.h index a08ec81df..ddfe6bda4 100644 --- a/include/asm-alpha/mman.h +++ b/include/asm-alpha/mman.h @@ -13,9 +13,9 @@ #define MAP_ANONYMOUS 0x10 /* don't use a file */ /* not used by linux, but here to make sure we don't clash with OSF/1 defines */ -#define MAP_HASSEMAPHORE 0x0200 -#define MAP_INHERIT 0x0400 -#define MAP_UNALIGNED 0x0800 +#define _MAP_HASSEMAPHORE 0x0200 +#define _MAP_INHERIT 0x0400 +#define _MAP_UNALIGNED 0x0800 /* These are linux-specific */ #define MAP_GROWSDOWN 0x1000 /* stack-like segment */ diff --git a/include/asm-alpha/pal.h b/include/asm-alpha/pal.h index a4ef2e38a..510d13326 100644 --- a/include/asm-alpha/pal.h +++ b/include/asm-alpha/pal.h @@ -7,7 +7,6 @@ #define PAL_halt 0 #define PAL_cflush 1 #define PAL_draina 2 -#define PAL_cobratt 9 #define PAL_bpt 128 #define PAL_bugchk 129 #define PAL_chmk 131 @@ -27,6 +26,8 @@ /* * OSF specific PAL-code */ +#define PAL_cserve 9 +#define PAL_wripir 13 #define PAL_rdmces 16 #define PAL_wrmces 17 #define PAL_wrfen 43 diff --git a/include/asm-alpha/processor.h b/include/asm-alpha/processor.h index 47f1bf4f6..2b805db93 100644 --- a/include/asm-alpha/processor.h +++ b/include/asm-alpha/processor.h @@ -15,7 +15,8 @@ /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) +#define TASK_UNMAPPED_BASE \ + ((current->personality & ADDR_LIMIT_32BIT) ? 0x40000000 : TASK_SIZE / 2) /* * Bus types @@ -93,7 +94,7 @@ extern void release_thread(struct task_struct *); /* NOTE: The task struct and the stack go together! */ #define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1,0)) + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) #define free_task_struct(p) free_pages((unsigned long)(p),1) #define init_task (init_task_union.task) diff --git a/include/asm-alpha/pyxis.h b/include/asm-alpha/pyxis.h new file mode 100644 index 000000000..9d3d49595 --- /dev/null +++ b/include/asm-alpha/pyxis.h @@ -0,0 +1,436 @@ +#ifndef __ALPHA_PYXIS__H__ +#define __ALPHA_PYXIS__H__ + +#include <linux/config.h> /* CONFIG_ALPHA_RUFFIAN. */ +#include <linux/types.h> + +/* + * PYXIS is the internal name for a cor logic chipset which provides + * memory controller and PCI access for the 21164A chip based systems. + * + * This file is based on: + * + * Pyxis Chipset Spec + * 14-Jun-96 + * Rev. X2.0 + * + */ + +/*------------------------------------------------------------------------** +** ** +** I/O procedures ** +** ** +** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers ** +** inportbxt: 8 bits only ** +** inport: alias of inportw ** +** outport: alias of outportw ** +** ** +** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers ** +** inmembxt: 8 bits only ** +** inmem: alias of inmemw ** +** outmem: alias of outmemw ** +** ** +**------------------------------------------------------------------------*/ + + +/* CIA ADDRESS BIT DEFINITIONS + * + * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | \_/ \_/ + * | | | + * +-- IO space, not cached. Byte Enable --+ | + * Transfer Length --+ + * + * + * + * Byte Transfer + * Enable Length Transfer Byte Address + * adr<6:5> adr<4:3> Length Enable Adder + * --------------------------------------------- + * 00 00 Byte 1110 0x000 + * 01 00 Byte 1101 0x020 + * 10 00 Byte 1011 0x040 + * 11 00 Byte 0111 0x060 + * + * 00 01 Word 1100 0x008 + * 01 01 Word 1001 0x028 <= Not supported in this code. + * 10 01 Word 0011 0x048 + * + * 00 10 Tribyte 1000 0x010 + * 01 10 Tribyte 0001 0x030 + * + * 10 11 Longword 0000 0x058 + * + * Note that byte enables are asserted low. + * + */ + +#define BYTE_ENABLE_SHIFT 5 +#define TRANSFER_LENGTH_SHIFT 3 +#define MEM_SP1_MASK 0x1fffffff /* Mem sparse space 1 mask is 29 bits */ + + +#define PYXIS_DMA_WIN_BASE (1024UL*1024UL*1024UL) +#define PYXIS_DMA_WIN_SIZE (1024*1024*1024) + +/* + * General Registers + */ +#define PYXIS_REV (IDENT_ADDR + 0x8740000080UL) +#define PYXIS_PCI_LAT (IDENT_ADDR + 0x87400000C0UL) +#define PYXIS_CTRL (IDENT_ADDR + 0x8740000100UL) +#define PYXIS_CTRL1 (IDENT_ADDR + 0x8740000140UL) +#define PYXIS_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL) + +#define PYXIS_HAE_MEM (IDENT_ADDR + 0x8740000400UL) +#define PYXIS_HAE_IO (IDENT_ADDR + 0x8740000440UL) +#define PYXIS_CFG (IDENT_ADDR + 0x8740000480UL) + +/* + * Diagnostic Registers + */ +#define PYXIS_DIAG (IDENT_ADDR + 0x8740002000UL) +#define PYXIS_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL) + +/* + * Performance Monitor registers (p4-3) + */ +#define PYXIS_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL) +#define PYXIS_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL) + +/* + * 21171-CA Error registers (p4-3) + */ +#define PYXIS_ERR (IDENT_ADDR + 0x8740008200UL) +#define PYXIS_STAT (IDENT_ADDR + 0x8740008240UL) +#define PYXIS_ERR_MASK (IDENT_ADDR + 0x8740008280UL) +#define PYXIS_SYN (IDENT_ADDR + 0x8740008300UL) +#define PYXIS_ERR_DATA (IDENT_ADDR + 0x8740008308UL) + +#define PYXIS_MEAR (IDENT_ADDR + 0x8740008400UL) +#define PYXIS_MESR (IDENT_ADDR + 0x8740008440UL) +#define PYXIS_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL) +#define PYXIS_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL) +#define PYXIS_PCI_ERR2 (IDENT_ADDR + 0x8740008880UL) + +/* + * PCI Address Translation Registers. I've only defined + * the first window fully as that's the only one that we're currently using. + * The other window bases are needed to disable the windows. + */ +#define PYXIS_TBIA (IDENT_ADDR + 0x8760000100UL) +#define PYXIS_W0_BASE (IDENT_ADDR + 0x8760000400UL) +#define PYXIS_W0_MASK (IDENT_ADDR + 0x8760000440UL) +#define PYXIS_T0_BASE (IDENT_ADDR + 0x8760000480UL) + +#define PYXIS_W1_BASE (IDENT_ADDR + 0x8760000500UL) +#define PYXIS_W2_BASE (IDENT_ADDR + 0x8760000600UL) +#define PYXIS_W3_BASE (IDENT_ADDR + 0x8760000700UL) + +/* + * Memory Control registers + */ +#define PYXIS_MCR (IDENT_ADDR + 0x8750000000UL) + +/* + * Memory spaces: + */ +#define PYXIS_IACK_SC (IDENT_ADDR + 0x8720000000UL) +#define PYXIS_CONF (IDENT_ADDR + 0x8700000000UL) +#define PYXIS_IO (IDENT_ADDR + 0x8580000000UL) +#define PYXIS_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL) +#define PYXIS_DENSE_MEM (IDENT_ADDR + 0x8600000000UL) + +/* + * Interrupt Control registers + */ +#define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL) +#define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL) +#define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL) +#define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL) +#define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL) +#define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL) +#define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL) +#define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL) +#define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL) + +/* + * Bit definitions for I/O Controller status register 0: + */ +#define PYXIS_STAT0_CMD 0xf +#define PYXIS_STAT0_ERR (1<<4) +#define PYXIS_STAT0_LOST (1<<5) +#define PYXIS_STAT0_THIT (1<<6) +#define PYXIS_STAT0_TREF (1<<7) +#define PYXIS_STAT0_CODE_SHIFT 8 +#define PYXIS_STAT0_CODE_MASK 0x7 +#define PYXIS_STAT0_P_NBR_SHIFT 13 +#define PYXIS_STAT0_P_NBR_MASK 0x7ffff + +#define HAE_ADDRESS PYXIS_HAE_MEM + +#ifdef __KERNEL__ + +/* + * Translate physical memory address as seen on (PCI) bus into + * a kernel virtual address and vv. + */ + +#if defined(CONFIG_ALPHA_RUFFIAN) +/* Ruffian doesn't do 1G PCI window. */ + +extern inline unsigned long virt_to_bus(void * address) +{ + return virt_to_phys(address); +} + +extern inline void * bus_to_virt(unsigned long address) +{ + return phys_to_virt(address); +} +#else +extern inline unsigned long virt_to_bus(void * address) +{ + return virt_to_phys(address) + PYXIS_DMA_WIN_BASE; +} + +extern inline void * bus_to_virt(unsigned long address) +{ + return phys_to_virt(address - PYXIS_DMA_WIN_BASE); +} +#endif /* RUFFIAN */ + +/* + * I/O functions: + * + * PYXIS (the 2117x PCI/memory support chipset for the EV5 (21164) + * series of processors uses a sparse address mapping scheme to + * get at PCI memory and I/O. + */ + +#define vuip volatile unsigned int * + +extern inline unsigned int __inb(unsigned long addr) +{ + long result = *(vuip) ((addr << 5) + PYXIS_IO + 0x00); + result >>= (addr & 3) * 8; + return 0xffUL & result; +} + +extern inline void __outb(unsigned char b, unsigned long addr) +{ + unsigned int w; + + asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); + *(vuip) ((addr << 5) + PYXIS_IO + 0x00) = w; + mb(); +} + +extern inline unsigned int __inw(unsigned long addr) +{ + long result = *(vuip) ((addr << 5) + PYXIS_IO + 0x08); + result >>= (addr & 3) * 8; + return 0xffffUL & result; +} + +extern inline void __outw(unsigned short b, unsigned long addr) +{ + unsigned int w; + + asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); + *(vuip) ((addr << 5) + PYXIS_IO + 0x08) = w; + mb(); +} + +extern inline unsigned int __inl(unsigned long addr) +{ + return *(vuip) ((addr << 5) + PYXIS_IO + 0x18); +} + +extern inline void __outl(unsigned int b, unsigned long addr) +{ + *(vuip) ((addr << 5) + PYXIS_IO + 0x18) = b; + mb(); +} + + +/* + * Memory functions. 64-bit and 32-bit accesses are done through + * dense memory space, everything else through sparse space. + * + * For reading and writing 8 and 16 bit quantities we need to + * go through one of the three sparse address mapping regions + * and use the HAE_MEM CSR to provide some bits of the address. + * The following few routines use only sparse address region 1 + * which gives 1Gbyte of accessible space which relates exactly + * to the amount of PCI memory mapping *into* system address space. + * See p 6-17 of the specification but it looks something like this: + * + * 21164 Address: + * + * 3 2 1 + * 9876543210987654321098765432109876543210 + * 1ZZZZ0.PCI.QW.Address............BBLL + * + * ZZ = SBZ + * BB = Byte offset + * LL = Transfer length + * + * PCI Address: + * + * 3 2 1 + * 10987654321098765432109876543210 + * HHH....PCI.QW.Address........ 00 + * + * HHH = 31:29 HAE_MEM CSR + * + */ + +extern inline void pyxis_set_hae(unsigned long new_hae) +{ + unsigned long ipl = swpipl(7); + hae.cache = new_hae; + *hae.reg = new_hae; + mb(); + new_hae = *hae.reg; /* read it to be sure it got out */ + setipl(ipl); +} + +extern inline unsigned long __readb(unsigned long addr) +{ + unsigned long result, shift, msb, work, temp; + + shift = (addr & 0x3) << 3; + msb = addr & 0xE0000000UL; + temp = addr & MEM_SP1_MASK ; + if (msb != hae.cache) { + pyxis_set_hae(msb); + } + work = ((temp << 5) + PYXIS_SPARSE_MEM + 0x00); + result = *(vuip) work; + result >>= shift; + return 0x0ffUL & result; +} + +extern inline unsigned long __readw(unsigned long addr) +{ + unsigned long result, shift, msb, work, temp; + + shift = (addr & 0x3) << 3; + msb = addr & 0xE0000000UL; + temp = addr & MEM_SP1_MASK ; + if (msb != hae.cache) { + pyxis_set_hae(msb); + } + work = ((temp << 5) + PYXIS_SPARSE_MEM + 0x08); + result = *(vuip) work; + result >>= shift; + return 0x0ffffUL & result; +} + +extern inline unsigned long __readl(unsigned long addr) +{ + return *(vuip) (addr + PYXIS_DENSE_MEM); +} + +extern inline void __writeb(unsigned char b, unsigned long addr) +{ + unsigned long msb ; + + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + pyxis_set_hae(msb); + } + *(vuip) ((addr << 5) + PYXIS_SPARSE_MEM + 0x00) = b * 0x01010101; +} + +extern inline void __writew(unsigned short b, unsigned long addr) +{ + unsigned long msb ; + + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + pyxis_set_hae(msb); + } + *(vuip) ((addr << 5) + PYXIS_SPARSE_MEM + 0x08) = b * 0x00010001; +} + +extern inline void __writel(unsigned int b, unsigned long addr) +{ + *(vuip) (addr + PYXIS_DENSE_MEM) = b; +} + +#define inb(port) \ +(__builtin_constant_p((port))?__inb(port):_inb(port)) + +#define outb(x, port) \ +(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) + +#define readl(a) __readl((unsigned long)(a)) +#define writel(v,a) __writel((v),(unsigned long)(a)) + +#undef vuip + +extern unsigned long pyxis_init (unsigned long mem_start, + unsigned long mem_end); + +#endif /* __KERNEL__ */ + +/* + * Data structure for handling PYXIS machine checks: + */ +struct el_PYXIS_sysdata_mcheck { + u_long coma_gcr; + u_long coma_edsr; + u_long coma_ter; + u_long coma_elar; + u_long coma_ehar; + u_long coma_ldlr; + u_long coma_ldhr; + u_long coma_base0; + u_long coma_base1; + u_long coma_base2; + u_long coma_cnfg0; + u_long coma_cnfg1; + u_long coma_cnfg2; + u_long epic_dcsr; + u_long epic_pear; + u_long epic_sear; + u_long epic_tbr1; + u_long epic_tbr2; + u_long epic_pbr1; + u_long epic_pbr2; + u_long epic_pmr1; + u_long epic_pmr2; + u_long epic_harx1; + u_long epic_harx2; + u_long epic_pmlt; + u_long epic_tag0; + u_long epic_tag1; + u_long epic_tag2; + u_long epic_tag3; + u_long epic_tag4; + u_long epic_tag5; + u_long epic_tag6; + u_long epic_tag7; + u_long epic_data0; + u_long epic_data1; + u_long epic_data2; + u_long epic_data3; + u_long epic_data4; + u_long epic_data5; + u_long epic_data6; + u_long epic_data7; +}; + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_ADDR(x) (0x80 | (x)) +#define RTC_ALWAYS_BCD 0 + +#endif /* __ALPHA_PYXIS__H__ */ diff --git a/include/asm-alpha/signal.h b/include/asm-alpha/signal.h index 06c3bb7e3..80e27df1a 100644 --- a/include/asm-alpha/signal.h +++ b/include/asm-alpha/signal.h @@ -145,10 +145,17 @@ struct k_sigaction { /* Here we must cater to libcs that poke about in kernel headers. */ struct sigaction { - __sighandler_t sa_handler; + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; sigset_t sa_mask; int sa_flags; }; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + #endif /* __KERNEL__ */ typedef struct sigaltstack { diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h index d206bcc3b..f7596af91 100644 --- a/include/asm-alpha/smp.h +++ b/include/asm-alpha/smp.h @@ -1,6 +1,8 @@ #ifndef __ASM_SMP_H #define __ASM_SMP_H +#define cpu_logical_map(cpu) (cpu) + /* We'll get here eventually.. */ #endif diff --git a/include/asm-alpha/socket.h b/include/asm-alpha/socket.h index bbaf9b6c4..a40786fad 100644 --- a/include/asm-alpha/socket.h +++ b/include/asm-alpha/socket.h @@ -39,15 +39,15 @@ #define SO_PEERCRED 18 #define SO_BINDTODEVICE 25 -#define SO_BINDTODEVICE 25 +/* Socket filtering */ +#define SO_ATTACH_FILTER 26 +#define SO_DETACH_FILTER 27 /* Security levels - as per NRL IPv6 - don't actually do anything */ #define SO_SECURITY_AUTHENTICATION 19 #define SO_SECURITY_ENCRYPTION_TRANSPORT 20 #define SO_SECURITY_ENCRYPTION_NETWORK 21 -#define SO_BINDTODEVICE 22 - /* Socket types. */ #define SOCK_STREAM 1 /* stream (connection) socket */ #define SOCK_DGRAM 2 /* datagram (conn.less) socket */ diff --git a/include/asm-alpha/softirq.h b/include/asm-alpha/softirq.h index 456103536..96be9ed43 100644 --- a/include/asm-alpha/softirq.h +++ b/include/asm-alpha/softirq.h @@ -5,7 +5,7 @@ * is entirely private to an implementation, it should not be * referenced at all outside of this file. */ -extern atomic_t __alpha_bh_counter; +extern unsigned int local_bh_count[NR_CPUS]; #define get_active_bhs() (bh_mask & bh_active) @@ -43,51 +43,49 @@ extern inline void mark_bh(int nr) } /* - * These use a mask count to correctly handle - * nested disable/enable calls - */ -extern inline void disable_bh(int nr) -{ - bh_mask &= ~(1 << nr); - bh_mask_count[nr]++; -} - -extern inline void enable_bh(int nr) -{ - if (!--bh_mask_count[nr]) - bh_mask |= 1 << nr; -} - -/* * start_bh_atomic/end_bh_atomic also nest * naturally by using a counter */ extern inline void start_bh_atomic(void) { -#ifdef __SMP__ - atomic_inc(&__alpha_bh_counter); - synchronize_irq(); -#else - atomic_inc(&__alpha_bh_counter); -#endif + local_bh_count[smp_processor_id()]++; + barrier(); } extern inline void end_bh_atomic(void) { - atomic_dec(&__alpha_bh_counter); + barrier(); + local_bh_count[smp_processor_id()]--; } #ifndef __SMP__ /* These are for the irq's testing the lock */ -#define softirq_trylock() (atomic_read(&__alpha_bh_counter) ? \ - 0 : \ - ((atomic_set(&__alpha_bh_counter,1)),1)) -#define softirq_endlock() (atomic_set(&__alpha_bh_counter, 0)) +#define softirq_trylock(cpu) \ + (local_bh_count[cpu] ? 0 : (local_bh_count[cpu] = 1)) +#define softirq_endlock(cpu) \ + (local_bh_count[cpu] = 0) #else #error FIXME #endif /* __SMP__ */ + +/* + * These use a mask count to correctly handle + * nested disable/enable calls + */ +extern inline void disable_bh(int nr) +{ + bh_mask &= ~(1 << nr); + bh_mask_count[nr]++; +} + +extern inline void enable_bh(int nr) +{ + if (!--bh_mask_count[nr]) + bh_mask |= 1 << nr; +} + #endif /* _ALPHA_SOFTIRQ_H */ diff --git a/include/asm-alpha/t2.h b/include/asm-alpha/t2.h new file mode 100644 index 000000000..1f4f8c741 --- /dev/null +++ b/include/asm-alpha/t2.h @@ -0,0 +1,508 @@ +#ifndef __ALPHA_T2__H__ +#define __ALPHA_T2__H__ + +#include <linux/types.h> + +/* + * T2 is the internal name for the core logic chipset which provides + * memory controller and PCI access for the SABLE-based systems. + * + * This file is based on: + * + * SABLE I/O Specification + * Revision/Update Information: 1.3 + * + * jestabro@amt.tay1.dec.com Initial Version. + * + */ + +#define BYTE_ENABLE_SHIFT 5 +#define TRANSFER_LENGTH_SHIFT 3 +#define MEM_SP1_MASK 0x1fffffff /* Mem sparse space 1 mask is 29 bits */ + + +#define T2_DMA_WIN_BASE (1024UL*1024UL*1024UL) +#define T2_DMA_WIN_SIZE (1024*1024*1024) + +/* + * Memory spaces: + */ +#define T2_CONF (IDENT_ADDR + 0x390000000UL) +#define T2_IO (IDENT_ADDR + 0x3a0000000UL) +#define T2_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) +#define T2_DENSE_MEM (IDENT_ADDR + 0x3c0000000UL) + +#define T2_IOCSR (IDENT_ADDR + 0x38e000000UL) +#define T2_CERR1 (IDENT_ADDR + 0x38e000020UL) +#define T2_CERR2 (IDENT_ADDR + 0x38e000040UL) +#define T2_CERR3 (IDENT_ADDR + 0x38e000060UL) +#define T2_PERR1 (IDENT_ADDR + 0x38e000080UL) +#define T2_PERR2 (IDENT_ADDR + 0x38e0000a0UL) +#define T2_PSCR (IDENT_ADDR + 0x38e0000c0UL) +#define T2_HAE_1 (IDENT_ADDR + 0x38e0000e0UL) +#define T2_HAE_2 (IDENT_ADDR + 0x38e000100UL) +#define T2_HBASE (IDENT_ADDR + 0x38e000120UL) +#define T2_WBASE1 (IDENT_ADDR + 0x38e000140UL) +#define T2_WMASK1 (IDENT_ADDR + 0x38e000160UL) +#define T2_TBASE1 (IDENT_ADDR + 0x38e000180UL) +#define T2_WBASE2 (IDENT_ADDR + 0x38e0001a0UL) +#define T2_WMASK2 (IDENT_ADDR + 0x38e0001c0UL) +#define T2_TBASE2 (IDENT_ADDR + 0x38e0001e0UL) +#define T2_TLBBR (IDENT_ADDR + 0x38e000200UL) + +#define T2_HAE_3 (IDENT_ADDR + 0x38e000240UL) +#define T2_HAE_4 (IDENT_ADDR + 0x38e000260UL) + +#define HAE_ADDRESS T2_HAE_1 + +/* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to + 3.8fff.ffff + * + * +--------------+ 3 8000 0000 + * | CPU 0 CSRs | + * +--------------+ 3 8100 0000 + * | CPU 1 CSRs | + * +--------------+ 3 8200 0000 + * | CPU 2 CSRs | + * +--------------+ 3 8300 0000 + * | CPU 3 CSRs | + * +--------------+ 3 8400 0000 + * | CPU Reserved | + * +--------------+ 3 8700 0000 + * | Mem Reserved | + * +--------------+ 3 8800 0000 + * | Mem 0 CSRs | + * +--------------+ 3 8900 0000 + * | Mem 1 CSRs | + * +--------------+ 3 8a00 0000 + * | Mem 2 CSRs | + * +--------------+ 3 8b00 0000 + * | Mem 3 CSRs | + * +--------------+ 3 8c00 0000 + * | Mem Reserved | + * +--------------+ 3 8e00 0000 + * | PCI Bridge | + * +--------------+ 3 8f00 0000 + * | Expansion IO | + * +--------------+ 3 9000 0000 + * + * + */ +#define CPU0_BASE (IDENT_ADDR + 0x380000000L) +#define CPU1_BASE (IDENT_ADDR + 0x381000000L) +#define CPU2_BASE (IDENT_ADDR + 0x382000000L) +#define CPU3_BASE (IDENT_ADDR + 0x383000000L) +#define MEM0_BASE (IDENT_ADDR + 0x388000000L) +#define MEM1_BASE (IDENT_ADDR + 0x389000000L) +#define MEM2_BASE (IDENT_ADDR + 0x38a000000L) +#define MEM3_BASE (IDENT_ADDR + 0x38b000000L) + +#ifdef __KERNEL__ + +/* + * Translate physical memory address as seen on (PCI) bus into + * a kernel virtual address and vv. + */ +extern inline unsigned long virt_to_bus(void * address) +{ + return virt_to_phys(address) + T2_DMA_WIN_BASE; +} + +extern inline void * bus_to_virt(unsigned long address) +{ + return phys_to_virt(address - T2_DMA_WIN_BASE); +} + +/* + * I/O functions: + * + * T2 (the core logic PCI/memory support chipset for the SABLE + * series of processors uses a sparse address mapping scheme to + * get at PCI memory and I/O. + */ + +#define vuip volatile unsigned int * + +extern inline unsigned int __inb(unsigned long addr) +{ + long result = *(vuip) ((addr << 5) + T2_IO + 0x00); + result >>= (addr & 3) * 8; + return 0xffUL & result; +} + +extern inline void __outb(unsigned char b, unsigned long addr) +{ + unsigned int w; + + asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); + *(vuip) ((addr << 5) + T2_IO + 0x00) = w; + mb(); +} + +extern inline unsigned int __inw(unsigned long addr) +{ + long result = *(vuip) ((addr << 5) + T2_IO + 0x08); + result >>= (addr & 3) * 8; + return 0xffffUL & result; +} + +extern inline void __outw(unsigned short b, unsigned long addr) +{ + unsigned int w; + + asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); + *(vuip) ((addr << 5) + T2_IO + 0x08) = w; + mb(); +} + +extern inline unsigned int __inl(unsigned long addr) +{ + return *(vuip) ((addr << 5) + T2_IO + 0x18); +} + +extern inline void __outl(unsigned int b, unsigned long addr) +{ + *(vuip) ((addr << 5) + T2_IO + 0x18) = b; + mb(); +} + + +/* + * Memory functions. 64-bit and 32-bit accesses are done through + * dense memory space, everything else through sparse space. + * + * For reading and writing 8 and 16 bit quantities we need to + * go through one of the three sparse address mapping regions + * and use the HAE_MEM CSR to provide some bits of the address. + * The following few routines use only sparse address region 1 + * which gives 1Gbyte of accessible space which relates exactly + * to the amount of PCI memory mapping *into* system address space. + * See p 6-17 of the specification but it looks something like this: + * + * 21164 Address: + * + * 3 2 1 + * 9876543210987654321098765432109876543210 + * 1ZZZZ0.PCI.QW.Address............BBLL + * + * ZZ = SBZ + * BB = Byte offset + * LL = Transfer length + * + * PCI Address: + * + * 3 2 1 + * 10987654321098765432109876543210 + * HHH....PCI.QW.Address........ 00 + * + * HHH = 31:29 HAE_MEM CSR + * + */ + +extern inline unsigned long __readb(unsigned long addr) +{ + unsigned long result, shift, msb; + + shift = (addr & 0x3) * 8 ; + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + set_hae(msb); + } + result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) ; + result >>= shift; + return 0xffUL & result; +} + +extern inline unsigned long __readw(unsigned long addr) +{ + unsigned long result, shift, msb; + + shift = (addr & 0x3) * 8; + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + set_hae(msb); + } + result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); + result >>= shift; + return 0xffffUL & result; +} + +/* on SABLE with T2, we must use SPARSE memory even for 32-bit access */ +extern inline unsigned long __readl(unsigned long addr) +{ + unsigned long result, msb; + + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + set_hae(msb); + } + result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); + return 0xffffffffUL & result; +} + +extern inline void __writeb(unsigned char b, unsigned long addr) +{ + unsigned long msb ; + + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + set_hae(msb); + } + *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = b * 0x01010101; +} + +extern inline void __writew(unsigned short b, unsigned long addr) +{ + unsigned long msb ; + + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + set_hae(msb); + } + *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = b * 0x00010001; +} + +/* on SABLE with T2, we must use SPARSE memory even for 32-bit access */ +extern inline void __writel(unsigned int b, unsigned long addr) +{ + unsigned long msb ; + + msb = addr & 0xE0000000 ; + addr &= MEM_SP1_MASK ; + if (msb != hae.cache) { + set_hae(msb); + } + *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b; +} + +#define inb(port) \ +(__builtin_constant_p((port))?__inb(port):_inb(port)) + +#define outb(x, port) \ +(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) + +#define readl(a) __readl((unsigned long)(a)) +#define writel(v,a) __writel((v),(unsigned long)(a)) + +#undef vuip + +extern unsigned long t2_init (unsigned long mem_start, + unsigned long mem_end); + +#endif /* __KERNEL__ */ + +/* + * Sable CPU Module CSRS + * + * These are CSRs for hardware other than the CPU chip on the CPU module. + * The CPU module has Backup Cache control logic, Cbus control logic, and + * interrupt control logic on it. There is a duplicate tag store to speed + * up maintaining cache coherency. + */ + +struct sable_cpu_csr { +unsigned long bcc; long fill_00[3]; /* Backup Cache Control */ +unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */ +unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */ +unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */ +unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */ +unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */ +unsigned long cbctl; long fill_06[3]; /* CBus Control */ +unsigned long cbe; long fill_07[3]; /* CBus Error */ +unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */ +unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */ +unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */ +unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */ +unsigned long sic; long fill_12[3]; /* System Interrupt Clear */ +unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */ +unsigned long madrl; long fill_14[3]; /* CBus Miss Address */ +unsigned long rev; long fill_15[3]; /* CMIC Revision */ +}; + +/* + * Data structure for handling T2 machine checks: + */ +struct el_t2_frame_header { + unsigned int elcf_fid; /* Frame ID (from above) */ + unsigned int elcf_size; /* Size of frame in bytes */ +}; + +struct el_t2_procdata_mcheck { + unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */ + /* EV4-specific fields */ + unsigned long elfmc_exc_addr; /* Addr of excepting insn. */ + unsigned long elfmc_exc_sum; /* Summary of arith traps. */ + unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */ + unsigned long elfmc_iccsr; /* IBox hardware enables. */ + unsigned long elfmc_pal_base; /* Base address for PALcode. */ + unsigned long elfmc_hier; /* Hardware Interrupt Enable. */ + unsigned long elfmc_hirr; /* Hardware Interrupt Request. */ + unsigned long elfmc_mm_csr; /* D-stream fault info. */ + unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */ + unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ + unsigned long elfmc_abox_ctl; /* ABox Control Register. */ + unsigned long elfmc_biu_stat; /* BIU Status. */ + unsigned long elfmc_biu_addr; /* BUI Address. */ + unsigned long elfmc_biu_ctl; /* BIU Control. */ + unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */ + unsigned long elfmc_fill_addr;/* Cache block which was being read. */ + unsigned long elfmc_va; /* Effective VA of fault or miss. */ + unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */ +}; + +/* + * Sable processor specific Machine Check Data segment. + */ + +struct el_t2_logout_header { + unsigned int elfl_size; /* size in bytes of logout area. */ + int elfl_sbz1:31; /* Should be zero. */ + char elfl_retry:1; /* Retry flag. */ + unsigned int elfl_procoffset; /* Processor-specific offset. */ + unsigned int elfl_sysoffset; /* Offset of system-specific. */ + unsigned int elfl_error_type; /* PAL error type code. */ + unsigned int elfl_frame_rev; /* PAL Frame revision. */ +}; +struct el_t2_sysdata_mcheck { + unsigned long elcmc_bcc; /* CSR 0 */ + unsigned long elcmc_bcce; /* CSR 1 */ + unsigned long elcmc_bccea; /* CSR 2 */ + unsigned long elcmc_bcue; /* CSR 3 */ + unsigned long elcmc_bcuea; /* CSR 4 */ + unsigned long elcmc_dter; /* CSR 5 */ + unsigned long elcmc_cbctl; /* CSR 6 */ + unsigned long elcmc_cbe; /* CSR 7 */ + unsigned long elcmc_cbeal; /* CSR 8 */ + unsigned long elcmc_cbeah; /* CSR 9 */ + unsigned long elcmc_pmbx; /* CSR 10 */ + unsigned long elcmc_ipir; /* CSR 11 */ + unsigned long elcmc_sic; /* CSR 12 */ + unsigned long elcmc_adlk; /* CSR 13 */ + unsigned long elcmc_madrl; /* CSR 14 */ + unsigned long elcmc_crrev4; /* CSR 15 */ +}; + +/* + * Sable memory error frame - sable pfms section 3.42 + */ +struct el_t2_data_memory { + struct el_t2_frame_header elcm_hdr; /* ID$MEM-FERR = 0x08 */ + unsigned int elcm_module; /* Module id. */ + unsigned int elcm_res04; /* Reserved. */ + unsigned long elcm_merr; /* CSR0: Error Reg 1. */ + unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */ + unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */ + unsigned long elcm_mconf; /* CSR3: Configuration. */ + unsigned long elcm_medc1; /* CSR4: EDC Status 1. */ + unsigned long elcm_medc2; /* CSR5: EDC Status 2. */ + unsigned long elcm_medcc; /* CSR6: EDC Control. */ + unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */ + unsigned long elcm_mref; /* CSR8: Refresh Control. */ + unsigned long elcm_filter; /* CSR9: CRD Filter Control. */ +}; + + +/* + * Sable other cpu error frame - sable pfms section 3.43 + */ +struct el_t2_data_other_cpu { + short elco_cpuid; /* CPU ID */ + short elco_res02[3]; + unsigned long elco_bcc; /* CSR 0 */ + unsigned long elco_bcce; /* CSR 1 */ + unsigned long elco_bccea; /* CSR 2 */ + unsigned long elco_bcue; /* CSR 3 */ + unsigned long elco_bcuea; /* CSR 4 */ + unsigned long elco_dter; /* CSR 5 */ + unsigned long elco_cbctl; /* CSR 6 */ + unsigned long elco_cbe; /* CSR 7 */ + unsigned long elco_cbeal; /* CSR 8 */ + unsigned long elco_cbeah; /* CSR 9 */ + unsigned long elco_pmbx; /* CSR 10 */ + unsigned long elco_ipir; /* CSR 11 */ + unsigned long elco_sic; /* CSR 12 */ + unsigned long elco_adlk; /* CSR 13 */ + unsigned long elco_madrl; /* CSR 14 */ + unsigned long elco_crrev4; /* CSR 15 */ +}; + +/* + * Sable other cpu error frame - sable pfms section 3.44 + */ +struct el_t2_data_t2{ + struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */ + unsigned long elct_iocsr; /* IO Control and Status Register */ + unsigned long elct_cerr1; /* Cbus Error Register 1 */ + unsigned long elct_cerr2; /* Cbus Error Register 2 */ + unsigned long elct_cerr3; /* Cbus Error Register 3 */ + unsigned long elct_perr1; /* PCI Error Register 1 */ + unsigned long elct_perr2; /* PCI Error Register 2 */ + unsigned long elct_hae0_1; /* High Address Extension Register 1 */ + unsigned long elct_hae0_2; /* High Address Extension Register 2 */ + unsigned long elct_hbase; /* High Base Register */ + unsigned long elct_wbase1; /* Window Base Register 1 */ + unsigned long elct_wmask1; /* Window Mask Register 1 */ + unsigned long elct_tbase1; /* Translated Base Register 1 */ + unsigned long elct_wbase2; /* Window Base Register 2 */ + unsigned long elct_wmask2; /* Window Mask Register 2 */ + unsigned long elct_tbase2; /* Translated Base Register 2 */ + unsigned long elct_tdr0; /* TLB Data Register 0 */ + unsigned long elct_tdr1; /* TLB Data Register 1 */ + unsigned long elct_tdr2; /* TLB Data Register 2 */ + unsigned long elct_tdr3; /* TLB Data Register 3 */ + unsigned long elct_tdr4; /* TLB Data Register 4 */ + unsigned long elct_tdr5; /* TLB Data Register 5 */ + unsigned long elct_tdr6; /* TLB Data Register 6 */ + unsigned long elct_tdr7; /* TLB Data Register 7 */ +}; + +/* + * Sable error log data structure - sable pfms section 3.40 + */ +struct el_t2_data_corrected { + unsigned long elcpb_biu_stat; + unsigned long elcpb_biu_addr; + unsigned long elcpb_biu_ctl; + unsigned long elcpb_fill_syndrome; + unsigned long elcpb_fill_addr; + unsigned long elcpb_bc_tag; +}; + +/* + * Sable error log data structure + * Note there are 4 memory slots on sable (see t2.h) + */ +struct el_t2_frame_mcheck { + struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */ + struct el_t2_logout_header elfmc_hdr; + struct el_t2_procdata_mcheck elfmc_procdata; + struct el_t2_sysdata_mcheck elfmc_sysdata; + struct el_t2_data_t2 elfmc_t2data; + struct el_t2_data_memory elfmc_memdata[4]; + struct el_t2_frame_header elfmc_footer; /* empty */ +}; + + +/* + * Sable error log data structures on memory errors + */ +struct el_t2_frame_corrected { + struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */ + struct el_t2_logout_header elfcc_hdr; + struct el_t2_data_corrected elfcc_procdata; +/* struct el_t2_data_t2 elfcc_t2data; */ +/* struct el_t2_data_memory elfcc_memdata[4]; */ + struct el_t2_frame_header elfcc_footer; /* empty */ +}; + + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_ADDR(x) (0x80 | (x)) +#define RTC_ALWAYS_BCD 0 + +#endif /* __ALPHA_T2__H__ */ diff --git a/include/asm-alpha/types.h b/include/asm-alpha/types.h index 28e5d487d..381d5f044 100644 --- a/include/asm-alpha/types.h +++ b/include/asm-alpha/types.h @@ -63,11 +63,13 @@ typedef unsigned int u32; typedef signed long long s64; typedef unsigned long long u64; +#define BITS_PER_LONG 32 #else typedef signed long s64; typedef unsigned long u64; +#define BITS_PER_LONG 64 #endif diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h index 44855135e..cef856f24 100644 --- a/include/asm-alpha/unistd.h +++ b/include/asm-alpha/unistd.h @@ -8,7 +8,7 @@ #define __NR_write 4 #define __NR_osf_old_open 5 /* not implemented */ #define __NR_close 6 -#define __NR_wait4 7 +#define __NR_osf_wait4 7 #define __NR_osf_old_creat 8 /* not implemented */ #define __NR_link 9 #define __NR_unlink 10 @@ -84,17 +84,17 @@ #define __NR_setgroups 80 #define __NR_osf_old_getpgrp 81 /* not implemented */ #define __NR_setpgrp 82 /* BSD alias for setpgid */ -#define __NR_setitimer 83 +#define __NR_osf_setitimer 83 #define __NR_osf_old_wait 84 /* not implemented */ #define __NR_osf_table 85 /* not implemented */ -#define __NR_getitimer 86 +#define __NR_osf_getitimer 86 #define __NR_gethostname 87 #define __NR_sethostname 88 #define __NR_getdtablesize 89 #define __NR_dup2 90 #define __NR_fstat 91 #define __NR_fcntl 92 -#define __NR_select 93 +#define __NR_osf_select 93 #define __NR_poll 94 #define __NR_fsync 95 #define __NR_setpriority 96 @@ -117,13 +117,13 @@ #define __NR_recvmsg 113 #define __NR_sendmsg 114 #define __NR_osf_old_vtrace 115 /* not implemented */ -#define __NR_gettimeofday 116 -#define __NR_getrusage 117 +#define __NR_osf_gettimeofday 116 +#define __NR_osf_getrusage 117 #define __NR_getsockopt 118 #define __NR_readv 120 #define __NR_writev 121 -#define __NR_settimeofday 122 +#define __NR_osf_settimeofday 122 #define __NR_fchown 123 #define __NR_fchmod 124 #define __NR_recvfrom 125 @@ -139,7 +139,7 @@ #define __NR_socketpair 135 #define __NR_mkdir 136 #define __NR_rmdir 137 -#define __NR_utimes 138 +#define __NR_osf_utimes 138 #define __NR_osf_old_sigreturn 139 /* not implemented */ #define __NR_osf_adjtime 140 /* not implemented */ #define __NR_getpeername 141 @@ -156,7 +156,7 @@ #define __NR_osf_pid_block 153 /* not implemented */ #define __NR_osf_pid_unblock 154 /* not implemented */ -#define __NR_osf_sigaction 156 +#define __NR_sigaction 156 #define __NR_osf_sigwaitprim 157 /* not implemented */ #define __NR_osf_nfssvc 158 /* not implemented */ #define __NR_osf_getdirentries 159 @@ -186,7 +186,7 @@ #define __NR_semget 205 #define __NR_semop 206 #define __NR_osf_utsname 207 -#define __NR_osf_lchown 208 /* not implemented */ +#define __NR_lchown 208 #define __NR_osf_shmat 209 #define __NR_shmctl 210 #define __NR_shmdt 211 @@ -240,7 +240,7 @@ #define __NR_bdflush 300 #define __NR_sethae 301 #define __NR_mount 302 -#define __NR_adjtimex 303 +#define __NR_old_adjtimex 303 #define __NR_swapoff 304 #define __NR_getdents 305 #define __NR_create_module 306 @@ -295,6 +295,15 @@ #define __NR_rt_sigtimedwait 355 #define __NR_rt_sigqueueinfo 356 #define __NR_rt_sigsuspend 357 +#define __NR_select 358 +#define __NR_gettimeofday 359 +#define __NR_settimeofday 360 +#define __NR_getitimer 361 +#define __NR_setitimer 362 +#define __NR_utimes 363 +#define __NR_getrusage 364 +#define __NR_wait4 365 +#define __NR_adjtimex 366 #if defined(__LIBRARY__) && defined(__GNUC__) @@ -386,6 +395,12 @@ static inline int close(int fd) return sys_close(fd); } +extern off_t sys_lseek(int, off_t, int); +static inline off_t lseek(int fd, off_t off, int whense) +{ + return sys_lseek(fd, off, whense); +} + extern int sys_exit(int); static inline int _exit(int value) { @@ -406,22 +421,12 @@ static inline int read(int fd, char * buf, int nr) return sys_read(fd, buf, nr); } -extern int do_execve(char *, char **, char **, struct pt_regs *); -extern void ret_from_sys_call(void); +extern int __kernel_execve(char *, char **, char **, struct pt_regs *); static inline int execve(char * file, char ** argvp, char ** envp) { - int i; struct pt_regs regs; - memset(®s, 0, sizeof(regs)); - i = do_execve(file, argvp, envp, ®s); - if (!i) { - __asm__ __volatile__("bis %0,%0,$30\n\t" - "bis %1,%1,$26\n\t" - "ret $31,($26),1\n\t" - : :"r" (®s), "r" (ret_from_sys_call)); - } - return -1; + return __kernel_execve(file, argvp, envp, ®s); } extern int sys_setsid(void); |