19 files changed, 669 insertions, 133 deletions

diff --git a/include/asm-sparc64/asi.h b/include/asm-sparc64/asi.h
index 06a3b848b..37dd93cd1 100644
--- a/include/asm-sparc64/asi.h
+++ b/include/asm-sparc64/asi.h
@@ -1,4 +1,4 @@
-/* $Id: asi.h,v 1.1 1996/11/20 12:59:45 davem Exp $ */
+/* $Id: asi.h,v 1.4 2001/03/15 02:08:46 davem Exp $ */
 #ifndef _SPARC64_ASI_H
 #define _SPARC64_ASI_H
 
@@ -23,19 +23,35 @@
 #define ASI_PNFL		0x8a /* Primary, no fault, little endian	*/
 #define ASI_SNFL		0x8b /* Secondary, no fault, little endian	*/
 
-/* SpitFire extended ASIs. */
+/* SpitFire and later extended ASIs.  The "(III)" marker designates
+ * UltraSparc-III specific ASIs.
+ */
 #define ASI_PHYS_USE_EC		0x14 /* PADDR, E-cachable			*/
-#define ASI_PHYS_BYPASS_EC_E	0x15 /* PADDR, E-cachable, E-bit		*/
+#define ASI_PHYS_BYPASS_EC_E	0x15 /* PADDR, E-bit				*/
 #define ASI_PHYS_USE_EC_L	0x1c /* PADDR, E-cachable, little endian	*/
-#define ASI_PHYS_BYPASS_EC_E_L	0x1d /* PADDR, E-cachable, E-bit, little endian	*/
+#define ASI_PHYS_BYPASS_EC_E_L	0x1d /* PADDR, E-bit, little endian		*/
 #define ASI_NUCLEUS_QUAD_LDD	0x24 /* Cachable, qword load			*/
 #define ASI_NUCLEUS_QUAD_LDD_L	0x2c /* Cachable, qword load, little endian 	*/
+#define ASI_PCACHE_DATA_STATUS	0x30 /* (III) PCache data status RAM diag	*/
+#define ASI_PCACHE_DATA		0x31 /* (III) PCache data RAM diag		*/
+#define ASI_PCACHE_TAG		0x32 /* (III) PCache tag RAM diag		*/
+#define ASI_PCACHE_SNOOP_TAG	0x33 /* (III) PCache snoop tag RAM diag		*/
+#define ASI_WCACHE_VALID_BITS	0x38 /* (III) WCache Valid Bits diag		*/
+#define ASI_WCACHE_DATA		0x39 /* (III) WCache data RAM diag		*/
+#define ASI_WCACHE_TAG		0x3a /* (III) WCache tag RAM diag		*/
+#define ASI_WCACHE_SNOOP_TAG	0x3b /* (III) WCache snoop tag RAM diag		*/
+#define ASI_DCACHE_INVALIDATE	0x42 /* (III) DCache Invalidate diag		*/
+#define ASI_DCACHE_UTAG		0x43 /* (III) DCache uTag diag			*/
+#define ASI_DCACHE_SNOOP_TAG	0x44 /* (III) DCache snoop tag RAM diag		*/
 #define ASI_LSU_CONTROL		0x45 /* Load-store control unit			*/
+#define ASI_DCU_CONTROL_REG	0x45 /* (III) DCache Unit Control Register	*/
 #define ASI_DCACHE_DATA		0x46 /* Data cache data-ram diag access		*/
 #define ASI_DCACHE_TAG		0x47 /* Data cache tag/valid ram diag access	*/
 #define ASI_INTR_DISPATCH_STAT	0x48 /* IRQ vector dispatch status		*/
 #define ASI_INTR_RECEIVE	0x49 /* IRQ vector receive status		*/
 #define ASI_UPA_CONFIG		0x4a /* UPA config space			*/
+#define ASI_SAFARI_CONFIG	0x4a /* (III) Safari Config Register		*/
+#define ASI_SAFARI_ADDRESS	0x4a /* (III) Safari Address Register		*/
 #define ASI_ESTATE_ERROR_EN	0x4b /* E-cache error enable space		*/
 #define ASI_AFSR		0x4c /* Async fault status register		*/
 #define ASI_AFAR		0x4d /* Async fault address register		*/
@@ -55,16 +71,23 @@
 #define ASI_DTLB_DATA_ACCESS	0x5d /* Data-MMU TLB data access register	*/
 #define ASI_DTLB_TAG_READ	0x5e /* Data-MMU TLB tag read register		*/
 #define ASI_DMMU_DEMAP		0x5f /* Data-MMU TLB demap			*/
+#define ASI_IIU_INST_TRAP	0x60 /* (III) Instruction Breakpoint register	*/
 #define ASI_IC_INSTR		0x66 /* Insn cache instrucion ram diag access	*/
 #define ASI_IC_TAG		0x67 /* Insn cache tag/valid ram diag access	*/
+#define ASI_IC_STAG		0x68 /* (III) Insn cache snoop tag ram diag	*/
 #define ASI_IC_PRE_DECODE	0x6e /* Insn cache pre-decode ram diag access	*/
 #define ASI_IC_NEXT_FIELD	0x6f /* Insn cache next-field ram diag access	*/
+#define ASI_BRPRED_ARRAY	0x6f /* (III) Branch Prediction RAM diag	*/
 #define ASI_BLK_AIUP		0x70 /* Primary, user, block load/store		*/
 #define ASI_BLK_AIUS		0x71 /* Secondary, user, block load/store	*/
+#define ASI_EC_DATA		0x74 /* (III) E-cache data staging register	*/
+#define ASI_EC_CTRL		0x75 /* (III) E-cache control register		*/
 #define ASI_EC_W		0x76 /* E-cache diag write access		*/
 #define ASI_UDB_ERROR_W		0x77 /* External UDB error registers write	*/
 #define ASI_UDB_CONTROL_W	0x77 /* External UDB control registers write	*/
-#define ASI_UDB_INTR_W		0x77 /* External UDB IRQ vector dispatch write	*/
+#define ASI_INTR_W		0x77 /* IRQ vector dispatch write		*/
+#define ASI_INTR_DATAN_W	0x77 /* (III) Outgoing irq vector data reg N	*/
+#define ASI_INTR_DISPATCH_W	0x77 /* (III) Interrupt vector dispatch		*/
 #define ASI_BLK_AIUPL		0x78 /* Primary, user, little, blk ld/st	*/
 #define ASI_BLK_AIUSL		0x79 /* Secondary, user, little, blk ld/st	*/
 #define ASI_EC_R		0x7e /* E-cache diag read access		*/
@@ -72,7 +95,8 @@
 #define ASI_UDBL_ERROR_R	0x7f /* External UDB error registers read low	*/
 #define ASI_UDBH_CONTROL_R	0x7f /* External UDB control registers read hi	*/
 #define ASI_UDBL_CONTROL_R	0x7f /* External UDB control registers read low	*/
-#define ASI_UDB_INTR_R		0x7f /* External UDB IRQ vector dispatch read	*/
+#define ASI_INTR_R		0x7f /* IRQ vector dispatch read		*/
+#define ASI_INTR_DATAN_R	0x7f /* (III) Incoming irq vector data reg N	*/
 #define ASI_PST8_P		0xc0 /* Primary, 8 8-bit, partial		*/
 #define ASI_PST8_S		0xc1 /* Secondary, 8 8-bit, partial		*/
 #define ASI_PST16_P		0xc2 /* Primary, 4 16-bit, partial		*/
diff --git a/include/asm-sparc64/bbc.h b/include/asm-sparc64/bbc.h
new file mode 100644
index 000000000..765396288
--- /dev/null
+++ b/include/asm-sparc64/bbc.h
@@ -0,0 +1,225 @@
+/* $Id: bbc.h,v 1.1 2001/03/24 06:03:03 davem Exp $
+ * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
+ *        systems.
+ *
+ * Copyright (C) 2000 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _SPARC64_BBC_H
+#define _SPARC64_BBC_H
+
+/* Register sizes are indicated by "B" (Byte, 1-byte),
+ * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
+ * "Q" (Quad, 8 bytes) inside brackets.
+ */
+
+#define BBC_AID		0x00	/* [B] Agent ID			*/
+#define BBC_DEVP	0x01	/* [B] Device Present		*/
+#define BBC_ARB		0x02	/* [B] Arbitration		*/
+#define BBC_QUIESCE	0x03	/* [B] Quiesce			*/
+#define BBC_WDACTION	0x04	/* [B] Watchdog Action		*/
+#define BBC_SPG		0x06	/* [B] Soft POR Gen		*/
+#define BBC_SXG		0x07	/* [B] Soft XIR Gen		*/
+#define BBC_PSRC	0x08	/* [W] POR Source		*/
+#define BBC_XSRC	0x0c	/* [B] XIR Source		*/
+#define BBC_CSC		0x0d	/* [B] Clock Synthesizers Control*/
+#define BBC_ES_CTRL	0x0e	/* [H] Energy Star Control	*/
+#define BBC_ES_ACT	0x10	/* [W] E* Assert Change Time	*/
+#define BBC_ES_DACT	0x14	/* [B] E* De-Assert Change Time	*/
+#define BBC_ES_DABT	0x15	/* [B] E* De-Assert Bypass Time	*/
+#define BBC_ES_ABT	0x16	/* [H] E* Assert Bypass Time	*/
+#define BBC_ES_PST	0x18	/* [W] E* PLL Settle Time	*/
+#define BBC_ES_FSL	0x1c	/* [W] E* Frequency Switch Latency*/
+#define BBC_EBUST	0x20	/* [Q] EBUS Timing		*/
+#define BBC_JTAG_CMD	0x28	/* [W] JTAG+ Command		*/
+#define BBC_JTAG_CTRL	0x2c	/* [B] JTAG+ Control		*/
+#define BBC_I2C_SEL	0x2d	/* [B] I2C Selection		*/
+#define BBC_I2C_0_S1	0x2e	/* [B] I2C ctrlr-0 reg S1	*/
+#define BBC_I2C_0_S0	0x2f	/* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
+#define BBC_I2C_1_S1	0x30	/* [B] I2C ctrlr-1 reg S1	*/
+#define BBC_I2C_1_S0	0x31	/* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
+#define BBC_KBD_BEEP	0x32	/* [B] Keyboard Beep		*/
+#define BBC_KBD_BCNT	0x34	/* [W] Keyboard Beep Counter	*/
+
+#define BBC_REGS_SIZE	0x40
+
+/* There is a 2K scratch ram area at offset 0x80000 but I doubt
+ * we will use it for anything.
+ */
+
+/* Agent ID register.  This register shows the Safari Agent ID
+ * for the processors.  The value returned depends upon which
+ * cpu is reading the register.
+ */
+#define BBC_AID_ID	0x07	/* Safari ID		*/
+#define BBC_AID_RESV	0xf8	/* Reserved		*/
+
+/* Device Present register.  One can determine which cpus are actually
+ * present in the machine by interrogating this register.
+ */
+#define BBC_DEVP_CPU0	0x01	/* Processor 0 present	*/
+#define BBC_DEVP_CPU1	0x02	/* Processor 1 present	*/
+#define BBC_DEVP_CPU2	0x04	/* Processor 2 present	*/
+#define BBC_DEVP_CPU3	0x08	/* Processor 3 present	*/
+#define BBC_DEVP_RESV	0xf0	/* Reserved		*/
+
+/* Arbitration register.  This register is used to block access to
+ * the BBC from a particular cpu.
+ */
+#define BBC_ARB_CPU0	0x01	/* Enable cpu 0 BBC arbitratrion */
+#define BBC_ARB_CPU1	0x02	/* Enable cpu 1 BBC arbitratrion */
+#define BBC_ARB_CPU2	0x04	/* Enable cpu 2 BBC arbitratrion */
+#define BBC_ARB_CPU3	0x08	/* Enable cpu 3 BBC arbitratrion */
+#define BBC_ARB_RESV	0xf0	/* Reserved			 */
+
+/* Quiesce register.  Bus and BBC segments for cpus can be disabled
+ * with this register, ie. for hot plugging.
+ */
+#define BBC_QUIESCE_S02	0x01	/* Quiesce Safari segment for cpu 0 and 2 */
+#define BBC_QUIESCE_S13	0x02	/* Quiesce Safari segment for cpu 1 and 3 */
+#define BBC_QUIESCE_B02	0x04	/* Quiesce BBC segment for cpu 0 and 2    */
+#define BBC_QUIESCE_B13	0x08	/* Quiesce BBC segment for cpu 1 and 3    */
+#define BBC_QUIESCE_FD0 0x10	/* Disable Fatal_Error[0] reporting	  */
+#define BBC_QUIESCE_FD1 0x20	/* Disable Fatal_Error[1] reporting	  */
+#define BBC_QUIESCE_FD2 0x40	/* Disable Fatal_Error[2] reporting	  */
+#define BBC_QUIESCE_FD3 0x80	/* Disable Fatal_Error[3] reporting	  */
+
+/* Watchdog Action register.  When the watchdog device timer expires
+ * a line is enabled to the BBC.  The action BBC takes when this line
+ * is asserted can be controlled by this regiser.
+ */
+#define BBC_WDACTION_RST  0x01	/* When set, watchdog causes system reset.
+				 * When clear, all cpus receive XIR reset.
+				 */
+#define BBC_WDACTION_RESV 0xfe	/* Reserved */
+
+/* Soft_POR_GEN register.  The POR (Power On Reset) signal may be asserted
+ * for specific processors or all processors via this register.
+ */
+#define BBC_SPG_CPU0	0x01 /* Assert POR for processor 0	*/
+#define BBC_SPG_CPU1	0x02 /* Assert POR for processor 1	*/
+#define BBC_SPG_CPU2	0x04 /* Assert POR for processor 2	*/
+#define BBC_SPG_CPU3	0x08 /* Assert POR for processor 3	*/
+#define BBC_SPG_CPUALL	0x10 /* Reset all processors and reset
+			      * the entire system.
+			      */
+#define BBC_SPG_RESV	0xe0 /* Reserved			*/
+
+/* Soft_XIR_GEN register.  The XIR (eXternally Initiated Reset) signal
+ * may be asserted to specific processors via this register.
+ */
+#define BBC_SXG_CPU0	0x01 /* Assert XIR for processor 0	*/
+#define BBC_SXG_CPU1	0x02 /* Assert XIR for processor 1	*/
+#define BBC_SXG_CPU2	0x04 /* Assert XIR for processor 2	*/
+#define BBC_SXG_CPU3	0x08 /* Assert XIR for processor 3	*/
+#define BBC_SXG_RESV	0xf0 /* Reserved			*/
+
+/* POR Source register.  One may identify the cause of the most recent
+ * reset by reading this register.
+ */
+#define BBC_PSRC_SPG0	0x0001 /* CPU 0 reset via BBC_SPG register	*/
+#define BBC_PSRC_SPG1	0x0002 /* CPU 1 reset via BBC_SPG register	*/
+#define BBC_PSRC_SPG2	0x0004 /* CPU 2 reset via BBC_SPG register	*/
+#define BBC_PSRC_SPG3	0x0008 /* CPU 3 reset via BBC_SPG register	*/
+#define BBC_PSRC_SPGSYS	0x0010 /* System reset via BBC_SPG register	*/
+#define BBC_PSRC_JTAG	0x0020 /* System reset via JTAG+		*/
+#define BBC_PSRC_BUTTON	0x0040 /* System reset via push-button dongle	*/
+#define BBC_PSRC_PWRUP	0x0080 /* System reset via power-up		*/
+#define BBC_PSRC_FE0	0x0100 /* CPU 0 reported Fatal_Error		*/
+#define BBC_PSRC_FE1	0x0200 /* CPU 1 reported Fatal_Error		*/
+#define BBC_PSRC_FE2	0x0400 /* CPU 2 reported Fatal_Error		*/
+#define BBC_PSRC_FE3	0x0800 /* CPU 3 reported Fatal_Error		*/
+#define BBC_PSRC_FE4	0x1000 /* Schizo reported Fatal_Error		*/
+#define BBC_PSRC_FE5	0x2000 /* Safari device 5 reported Fatal_Error	*/
+#define BBC_PSRC_FE6	0x4000 /* CPMS reported Fatal_Error		*/
+#define BBC_PSRC_SYNTH	0x8000 /* System reset when on-board clock synthesizers
+				* were updated.
+				*/
+#define BBC_PSRC_WDT   0x10000 /* System reset via Super I/O watchdog	*/
+#define BBC_PSRC_RSC   0x20000 /* System reset via RSC remote monitoring
+				* device
+				*/
+
+/* XIR Source register.  The source of an XIR event sent to a processor may
+ * be determined via this register.
+ */
+#define BBC_XSRC_SXG0	0x01	/* CPU 0 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG1	0x02	/* CPU 1 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG2	0x04	/* CPU 2 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_SXG3	0x08	/* CPU 3 received XIR via Soft_XIR_GEN reg */
+#define BBC_XSRC_JTAG	0x10	/* All CPUs received XIR via JTAG+         */
+#define BBC_XSRC_W_OR_B	0x20	/* All CPUs received XIR either because:
+				 * a) Super I/O watchdog fired, or
+				 * b) XIR push button was activated
+				 */
+#define BBC_XSRC_RESV	0xc0	/* Reserved				   */
+
+/* Clock Synthesizers Control register.  This register provides the big-bang
+ * programming interface to the two clock synthesizers of the machine.
+ */
+#define BBC_CSC_SLOAD	0x01	/* Directly connected to S_LOAD pins	*/
+#define BBC_CSC_SDATA	0x02	/* Directly connected to S_DATA pins	*/
+#define BBC_CSC_SCLOCK	0x04	/* Directly connected to S_CLOCK pins	*/
+#define BBC_CSC_RESV	0x78	/* Reserved				*/
+#define BBC_CSC_RST	0x80	/* Generate system reset when S_LOAD==1	*/
+
+/* Energy Star Control register.  This register is used to generate the
+ * clock frequency change trigger to the main system devices (Schizo and
+ * the processors).  The transition occurs when bits in this register
+ * go from 0 to 1, only one bit must be set at once else no action
+ * occurs.  Basically the sequence of events is:
+ * a) Choose new frequency: full, 1/2 or 1/32
+ * b) Program this desired frequency into the cpus and Schizo.
+ * c) Set the same value in this register.
+ * d) 16 system clocks later, clear this register.
+ */
+#define BBC_ES_CTRL_1_1		0x01	/* Full frequency	*/
+#define BBC_ES_CTRL_1_2		0x02	/* 1/2 frequency	*/
+#define BBC_ES_CTRL_1_32	0x20	/* 1/32 frequency	*/
+#define BBC_ES_RESV		0xdc	/* Reserved		*/
+
+/* Energy Star Assert Change Time register.  This determines the number
+ * of BBC clock cycles (which is half the system frequency) between
+ * the detection of FREEZE_ACK being asserted and the assertion of
+ * the CLK_CHANGE_L[2:0] signals.
+ */
+#define BBC_ES_ACT_VAL	0xff
+
+/* Energy Star Assert Bypass Time register.  This determines the number
+ * of BBC clock cycles (which is half the system frequency) between
+ * the assertion of the CLK_CHANGE_L[2:0] signals and the assertion of
+ * the ESTAR_PLL_BYPASS signal.
+ */
+#define BBC_ES_ABT_VAL	0xffff
+
+/* Energy Star PLL Settle Time register.  This determines the number of
+ * BBC clock cycles (which is half the system frequency) between the
+ * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
+ * signal.
+ */
+#define BBC_ES_PST_VAL	0xffffffff
+
+/* Energy Star Frequency Switch Latency register.  This is the number of
+ * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
+ * edge of the Safari clock at the new frequency.
+ */
+#define BBC_ES_FSL_VAL	0xffffffff
+
+/* Keyboard Beep control register.  This is a simple enabler for the audio
+ * beep sound.
+ */
+#define BBC_KBD_BEEP_ENABLE	0x01 /* Enable beep	*/
+#define BBC_KBD_BEEP_RESV	0xfe /* Reserved	*/
+
+/* Keyboard Beep Counter register.  There is a free-running counter inside
+ * the BBC which runs at half the system clock.  The bit set in this register
+ * determines when the audio sound is generated.  So for example if bit
+ * 10 is set, the audio beep will oscillate at 1/(2**12).  The keyboard beep
+ * generator automatically selects a different bit to use if the system clock
+ * is changed via Energy Star.
+ */
+#define BBC_KBD_BCNT_BITS	0x0007fc00
+#define BBC_KBC_BCNT_RESV	0xfff803ff
+
+#endif /* _SPARC64_BBC_H */
+
diff --git a/include/asm-sparc64/dcr.h b/include/asm-sparc64/dcr.h
new file mode 100644
index 000000000..0938a1c6e
--- /dev/null
+++ b/include/asm-sparc64/dcr.h
@@ -0,0 +1,13 @@
+/* $Id: dcr.h,v 1.4 2001/03/09 17:56:37 davem Exp $ */
+#ifndef _SPARC64_DCR_H
+#define _SPARC64_DCR_H
+
+/* UltraSparc-III Dispatch Control Register, ASR 0x12 */
+#define DCR_OBS		0x0000000000000fc0 /* Observability Bus Controls	*/
+#define DCR_BPE		0x0000000000000020 /* Branch Predict Enable		*/
+#define DCR_RPE		0x0000000000000010 /* Return Address Prediction Enable	*/
+#define DCR_SI		0x0000000000000008 /* Single Instruction Disable	*/
+#define DCR_IFPOE	0x0000000000000002 /* IRQ FP Operation Enable		*/
+#define DCR_MS		0x0000000000000001 /* Multi-Scalar dispatch		*/
+
+#endif /* _SPARC64_DCR_H */
diff --git a/include/asm-sparc64/dcu.h b/include/asm-sparc64/dcu.h
new file mode 100644
index 000000000..ecbed2ae5
--- /dev/null
+++ b/include/asm-sparc64/dcu.h
@@ -0,0 +1,26 @@
+/* $Id: dcu.h,v 1.2 2001/03/01 23:23:33 davem Exp $ */
+#ifndef _SPARC64_DCU_H
+#define _SPARC64_DCU_H
+
+/* UltraSparc-III Data Cache Unit Control Register */
+#define DCU_CP		0x0002000000000000 /* Physical Cache Enable w/o mmu*/
+#define DCU_CV		0x0001000000000000 /* Virtual Cache Enable	w/o mmu	*/
+#define DCU_ME		0x0000800000000000 /* NC-store Merging Enable	*/
+#define DCU_RE		0x0000400000000000 /* RAW bypass Enable		*/
+#define DCU_PE		0x0000200000000000 /* PCache Enable		*/
+#define DCU_HPE		0x0000100000000000 /* HW prefetch Enable		*/
+#define DCU_SPE		0x0000080000000000 /* SW prefetch Enable		*/
+#define DCU_SL		0x0000040000000000 /* Secondary load steering Enab	*/
+#define DCU_WE		0x0000020000000000 /* WCache enable		*/
+#define DCU_PM		0x000001fe00000000 /* PA Watchpoint Byte Mask	*/
+#define DCU_VM		0x00000001fe000000 /* VA Watchpoint Byte Mask	*/
+#define DCU_PR		0x0000000001000000 /* PA Watchpoint Read Enable	*/
+#define DCU_PW		0x0000000000800000 /* PA Watchpoint Write Enable	*/
+#define DCU_VR		0x0000000000400000 /* VA Watchpoint Read Enable	*/
+#define DCU_VW		0x0000000000200000 /* VA Watchpoint Write Enable	*/
+#define DCU_DM		0x0000000000000008 /* DMMU Enable			*/
+#define DCU_IM		0x0000000000000004 /* IMMU Enable			*/
+#define DCU_DC		0x0000000000000002 /* Data Cache Enable		*/
+#define DCU_IC		0x0000000000000001 /* Instruction Cache Enable	*/
+
+#endif /* _SPARC64_DCU_H */
diff --git a/include/asm-sparc64/ebus.h b/include/asm-sparc64/ebus.h
index 7910d03ae..39d3d567a 100644
--- a/include/asm-sparc64/ebus.h
+++ b/include/asm-sparc64/ebus.h
@@ -1,4 +1,4 @@
-/* $Id: ebus.h,v 1.9 1999/08/30 10:14:37 davem Exp $
+/* $Id: ebus.h,v 1.10 2001/03/14 05:00:55 davem Exp $
  * ebus.h: PCI to Ebus pseudo driver software state.
  *
  * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
@@ -41,6 +41,7 @@ struct linux_ebus {
 	struct pci_pbm_info		*parent;
 	struct pci_dev			*self;
 	int				 index;
+	int				 is_rio;
 	int				 prom_node;
 	char				 prom_name[64];
 	struct linux_prom_ebus_ranges	 ebus_ranges[PROMREG_MAX];
diff --git a/include/asm-sparc64/elf.h b/include/asm-sparc64/elf.h
index 7e3adf02f..201470b52 100644
--- a/include/asm-sparc64/elf.h
+++ b/include/asm-sparc64/elf.h
@@ -1,4 +1,4 @@
-/* $Id: elf.h,v 1.25 2000/07/12 01:27:08 davem Exp $ */
+/* $Id: elf.h,v 1.28 2001/03/24 09:36:02 davem Exp $ */
 #ifndef __ASM_SPARC64_ELF_H
 #define __ASM_SPARC64_ELF_H
 
@@ -56,9 +56,10 @@ typedef struct {
    instruction set this cpu supports.  */
 
 /* On Ultra, we support all of the v8 capabilities. */
-#define ELF_HWCAP	(HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
-			 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | \
-			 HWCAP_SPARC_V9)
+#define ELF_HWCAP	((HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
+			  HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | \
+			  HWCAP_SPARC_V9) | \
+			 ((tlb_type == cheetah) ? HWCAP_SPARC_ULTRA3 : 0))
 
 /* This yields a string that ld.so will use to load implementation
    specific libraries for optimization.  This is more specific in
@@ -78,16 +79,16 @@ do {	unsigned char flags = current->thread.flags;	\
 		if (flags & SPARC_FLAG_32BIT) {		\
 		  pgd_t *pgd0 = &current->mm->pgd[0];	\
 		  if (pgd_none (*pgd0)) {		\
-		    pmd_t *page = get_pmd_fast();	\
+		    pmd_t *page = pmd_alloc_one_fast(NULL, 0);	\
 		    if (!page)				\
-		      (void) get_pmd_slow(pgd0, 0);	\
-                    else				\
-                      pgd_set(pgd0, page);		\
+		      page = pmd_alloc_one(NULL, 0);	\
+                    pgd_set(pgd0, page);		\
 		  }					\
 		  pgd_cache = pgd_val(*pgd0) << 11UL;	\
 		}					\
 		__asm__ __volatile__(			\
-			"stxa\t%0, [%1] %2"		\
+			"stxa\t%0, [%1] %2\n\t"		\
+			"membar #Sync"			\
 			: /* no outputs */		\
 			: "r" (pgd_cache),		\
 			  "r" (TSB_REG),		\
diff --git a/include/asm-sparc64/floppy.h b/include/asm-sparc64/floppy.h
index 25cc6dd9f..83d1b7fa0 100644
--- a/include/asm-sparc64/floppy.h
+++ b/include/asm-sparc64/floppy.h
@@ -1,4 +1,4 @@
-/* $Id: floppy.h,v 1.28 2000/02/18 13:50:54 davem Exp $
+/* $Id: floppy.h,v 1.29 2001/03/24 00:07:23 davem Exp $
  * asm-sparc64/floppy.h: Sparc specific parts of the Floppy driver.
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
@@ -565,6 +565,24 @@ static int sun_pci_fd_test_drive(unsigned long port, int drive)
 
 #endif /* CONFIG_PCI */
 
+#ifdef CONFIG_PCI
+static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
+{
+	if (!strcmp(edev->prom_name, "fdthree"))
+		return 1;
+	if (!strcmp(edev->prom_name, "floppy")) {
+		char compat[16];
+		prom_getstring(edev->prom_node,
+			       "compatible",
+			       compat, sizeof(compat));
+		compat[15] = '\0';
+		if (!strcmp(compat, "fdthree"))
+			return 1;
+	}
+	return 0;
+}
+#endif
+
 static unsigned long __init sun_floppy_init(void)
 {
 	char state[128];
@@ -592,7 +610,7 @@ static unsigned long __init sun_floppy_init(void)
 
 		for_each_ebus(ebus) {
 			for_each_ebusdev(edev, ebus) {
-				if (!strcmp(edev->prom_name, "fdthree"))
+				if (ebus_fdthree_p(edev))
 					goto ebus_done;
 			}
 		}
diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h
index 4e709ee25..c671d2629 100644
--- a/include/asm-sparc64/iommu.h
+++ b/include/asm-sparc64/iommu.h
@@ -1,4 +1,4 @@
-/* $Id: iommu.h,v 1.9 1999/09/21 14:39:39 davem Exp $
+/* $Id: iommu.h,v 1.10 2001/03/08 09:55:56 davem Exp $
  * iommu.h: Definitions for the sun5 IOMMU.
  *
  * Copyright (C) 1996, 1999 David S. Miller (davem@caip.rutgers.edu)
@@ -12,7 +12,7 @@
 #define IOPTE_STBUF         0x1000000000000000 /* DVMA can use streaming buffer    */
 #define IOPTE_INTRA         0x0800000000000000 /* SBUS slot-->slot direct transfer */
 #define IOPTE_CONTEXT	    0x07ff800000000000 /* Context number		   */
-#define IOPTE_PAGE          0x00007fffffffe000 /* Physical page number (PA[40:13]) */
+#define IOPTE_PAGE          0x00007fffffffe000 /* Physical page number (PA[42:13]) */
 #define IOPTE_CACHE         0x0000000000000010 /* Cached (in UPA E-cache)          */
 #define IOPTE_WRITE         0x0000000000000002 /* Writeable                        */
 
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index c5c3a2fc3..a56a9daa3 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -1,4 +1,4 @@
-/* $Id: irq.h,v 1.19 2000/06/26 19:40:27 davem Exp $
+/* $Id: irq.h,v 1.20 2001/03/09 01:31:40 davem Exp $
  * irq.h: IRQ registers on the 64-bit Sparc.
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
@@ -77,7 +77,9 @@ extern unsigned char dma_sync_reg_table_entry;
 
 /* IMAP/ICLR register defines */
 #define IMAP_VALID		0x80000000	/* IRQ Enabled		*/
-#define IMAP_TID		0x7c000000	/* UPA TargetID		*/
+#define IMAP_TID_UPA		0x7c000000	/* UPA TargetID		*/
+#define IMAP_AID_SAFARI		0x7c000000	/* Safari AgentID	*/
+#define IMAP_NID_SAFARI		0x03e00000	/* Safari NodeID	*/
 #define IMAP_IGN		0x000007c0	/* IRQ Group Number	*/
 #define IMAP_INO		0x0000003f	/* IRQ Number		*/
 #define IMAP_INR		0x000007ff	/* Full interrupt number*/
diff --git a/include/asm-sparc64/mc146818rtc.h b/include/asm-sparc64/mc146818rtc.h
index 4a9e01b4f..e9c0fcc25 100644
--- a/include/asm-sparc64/mc146818rtc.h
+++ b/include/asm-sparc64/mc146818rtc.h
@@ -7,8 +7,13 @@
 #include <asm/io.h>
 
 #ifndef RTC_PORT
-#define RTC_PORT(x)	(0x70 + (x))
-#define RTC_ALWAYS_BCD	1	/* RTC operates in binary mode */
+#ifdef CONFIG_PCI
+extern unsigned long ds1287_regs;
+#else
+#define ds1287_regs (0UL)
+#endif
+#define RTC_PORT(x)	(ds1287_regs + (x))
+#define RTC_ALWAYS_BCD	0
 #endif
 
 /*
diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h
index 6c5e894b8..27609bfbe 100644
--- a/include/asm-sparc64/mmu_context.h
+++ b/include/asm-sparc64/mmu_context.h
@@ -1,4 +1,4 @@
-/* $Id: mmu_context.h,v 1.45 2000/08/12 13:25:52 davem Exp $ */
+/* $Id: mmu_context.h,v 1.47 2001/03/22 07:26:04 davem Exp $ */
 #ifndef __SPARC64_MMU_CONTEXT_H
 #define __SPARC64_MMU_CONTEXT_H
 
@@ -72,6 +72,7 @@ do { \
 			     "mov	%3, %%g4\n\t" \
 			     "mov	%0, %%g7\n\t" \
 			     "stxa	%1, [%%g4] %2\n\t" \
+			     "membar	#Sync\n\t" \
 			     "wrpr	%%g0, 0x096, %%pstate" \
 			     : /* no outputs */ \
 			     : "r" (paddr), "r" (pgd_cache),\
@@ -84,18 +85,9 @@ do { \
 			     "flush	%%g6" \
 			     : /* No outputs */ \
 			     : "r" (CTX_HWBITS((__mm)->context)), \
-			       "r" (0x10), "i" (0x58))
+			       "r" (0x10), "i" (ASI_DMMU))
 
-/* Clean out potential stale TLB entries due to previous
- * users of this TLB context.  We flush TLB contexts
- * lazily on sparc64.
- */
-#define clean_secondary_context() \
-	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t" \
-			     "stxa	%%g0, [%0] %2\n\t" \
-			     "flush	%%g6" \
-			     : /* No outputs */ \
-			     : "r" (0x50), "i" (0x5f), "i" (0x57))
+extern void __flush_tlb_mm(unsigned long, unsigned long);
 
 /* Switch the current MM context. */
 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk, int cpu)
@@ -127,7 +119,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str
 		 */
 		if (!ctx_valid || !(mm->cpu_vm_mask & vm_mask)) {
 			mm->cpu_vm_mask |= vm_mask;
-			clean_secondary_context();
+			__flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
 		}
 	}
 	spin_unlock(&mm->page_table_lock);
@@ -147,7 +139,7 @@ static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm
 	spin_unlock(&mm->page_table_lock);
 
 	load_secondary_context(mm);
-	clean_secondary_context();
+	__flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
 	reload_tlbmiss_state(current, mm);
 }
 
diff --git a/include/asm-sparc64/openprom.h b/include/asm-sparc64/openprom.h
index 44210c08e..0a336901d 100644
--- a/include/asm-sparc64/openprom.h
+++ b/include/asm-sparc64/openprom.h
@@ -1,4 +1,4 @@
-/* $Id: openprom.h,v 1.8 2000/08/12 19:55:25 anton Exp $ */
+/* $Id: openprom.h,v 1.9 2001/03/16 10:22:02 davem Exp $ */
 #ifndef __SPARC64_OPENPROM_H
 #define __SPARC64_OPENPROM_H
 
@@ -204,6 +204,12 @@ struct linux_prom_ranges {
 	unsigned int or_size;
 };
 
+struct linux_prom64_ranges {
+	unsigned long ot_child_base;		/* Bus feels this */
+	unsigned long ot_parent_base;		/* CPU looks from here */
+	unsigned long or_size;
+};
+
 /* Ranges and reg properties are a bit different for PCI. */
 struct linux_prom_pci_registers {
 	unsigned int phys_hi;
diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h
index 6840476dd..9a0902325 100644
--- a/include/asm-sparc64/parport.h
+++ b/include/asm-sparc64/parport.h
@@ -1,4 +1,4 @@
-/* $Id: parport.h,v 1.9 2000/03/16 07:47:27 davem Exp $
+/* $Id: parport.h,v 1.10 2001/03/24 00:18:57 davem Exp $
  * parport.h: sparc64 specific parport initialization and dma.
  *
  * Copyright (C) 1999  Eddie C. Dost  (ecd@skynet.be)
@@ -99,6 +99,25 @@ get_dma_residue(unsigned int dmanr)
 	return res;
 }
 
+static int ebus_ecpp_p(struct linux_ebus_device *edev)
+{
+	if (!strcmp(edev->prom_name, "ecpp"))
+		return 1;
+	if (!strcmp(edev->prom_name, "parallel")) {
+		char compat[19];
+		prom_getstring(edev->prom_node,
+			       "compatible",
+			       compat, sizeof(compat));
+		compat[18] = '\0';
+		if (!strcmp(compat, "ecpp"))
+			return 1;
+		if (!strcmp(compat, "ns87317-ecpp") &&
+		    !strcmp(compat + 13, "ecpp"))
+			return 1;
+	}
+	return 0;
+}
+
 static int parport_pc_find_nonpci_ports (int autoirq, int autodma)
 {
 	struct linux_ebus *ebus;
@@ -110,7 +129,7 @@ static int parport_pc_find_nonpci_ports (int autoirq, int autodma)
 
 	for_each_ebus(ebus) {
 		for_each_ebusdev(edev, ebus) {
-			if (!strcmp(edev->prom_name, "ecpp")) {
+			if (ebus_ecpp_p(edev)) {
 				unsigned long base = edev->resource[0].start;
 				unsigned long config = edev->resource[1].start;
 
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index 082626725..ed71f2e7d 100644
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -1,4 +1,4 @@
-/* $Id: pbm.h,v 1.23 2001/01/11 16:26:45 davem Exp $
+/* $Id: pbm.h,v 1.25 2001/02/28 03:28:55 davem Exp $
  * pbm.h: UltraSparc PCI controller software state.
  *
  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
@@ -144,6 +144,9 @@ struct pci_pbm_info {
 	struct resource			io_space;
 	struct resource			mem_space;
 
+	/* Base of PCI Config space, can be per-PBM or shared. */
+	unsigned long			config_space;
+
 	/* State of 66MHz capabilities on this PBM. */
 	int				is_66mhz_capable;
 	int				all_devs_66mhz;
@@ -164,11 +167,8 @@ struct pci_controller_info {
 	/* List of all PCI controllers. */
 	struct pci_controller_info	*next;
 
-	/* Physical address base of controller registers
-	 * and PCI config space.
-	 */
+	/* Physical address base of controller registers. */
 	unsigned long			controller_regs;
-	unsigned long			config_space;
 
 	/* Opaque 32-bit system bus Port ID. */
 	u32				portid;
@@ -184,7 +184,7 @@ struct pci_controller_info {
 
 	/* Operations which are controller specific. */
 	void (*scan_bus)(struct pci_controller_info *);
-	unsigned int (*irq_build)(struct pci_controller_info *, struct pci_dev *, unsigned int);
+	unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int);
 	void (*base_address_update)(struct pci_dev *, int);
 	void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
 
diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h
index 45e1f1828..a0a93cbfa 100644
--- a/include/asm-sparc64/pgalloc.h
+++ b/include/asm-sparc64/pgalloc.h
@@ -1,4 +1,4 @@
-/* $Id: pgalloc.h,v 1.14 2000/12/09 04:15:24 anton Exp $ */
+/* $Id: pgalloc.h,v 1.18 2001/03/24 09:36:01 davem Exp $ */
 #ifndef _SPARC64_PGALLOC_H
 #define _SPARC64_PGALLOC_H
 
@@ -22,18 +22,22 @@
 #define flush_page_to_ram(page)			do { } while (0)
 
 /* 
- * icache doesnt snoop local stores and we don't use block commit stores
- * (which invalidate icache lines) during module load, so we need this.
+ * On spitfire, the icache doesn't snoop local stores and we don't
+ * use block commit stores (which invalidate icache lines) during
+ * module load, so we need this.
  */
 extern void flush_icache_range(unsigned long start, unsigned long end);
 
 extern void __flush_dcache_page(void *addr, int flush_icache);
 #define flush_dcache_page(page) \
-do {	if ((page)->mapping && !(page)->mapping->i_mmap && !(page)->mapping->i_mmap_shared) \
+do {	if ((page)->mapping && \
+	    !((page)->mapping->i_mmap) && \
+	    !((page)->mapping->i_mmap_shared)) \
 		set_bit(PG_dcache_dirty, &(page)->flags); \
 	else \
 		__flush_dcache_page((page)->virtual, \
-				    (page)->mapping != NULL); \
+				    ((tlb_type == spitfire) && \
+				     (page)->mapping != NULL)); \
 } while(0)
 
 extern void __flush_dcache_range(unsigned long start, unsigned long end);
@@ -93,14 +97,18 @@ extern void smp_flush_tlb_page(struct mm_struct *mm, unsigned long page);
 
 #endif /* ! CONFIG_SMP */
 
-/* This will change for Cheetah and later chips. */
-#define VPTE_BASE	0xfffffffe00000000
+#define VPTE_BASE_SPITFIRE	0xfffffffe00000000
+#if 1
+#define VPTE_BASE_CHEETAH	VPTE_BASE_SPITFIRE
+#else
+#define VPTE_BASE_CHEETAH	0xffe0000000000000
+#endif
 
 extern __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start,
 					  unsigned long end)
 {
 	/* Note the signed type.  */
-	long s = start, e = end;
+	long s = start, e = end, vpte_base;
 	if (s > e)
 		/* Nobody should call us with start below VM hole and end above.
 		   See if it is really true.  */
@@ -110,10 +118,15 @@ extern __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long st
 	s &= PMD_MASK;
 	e = (e + PMD_SIZE - 1) & PMD_MASK;
 #endif
+	vpte_base = (tlb_type == spitfire ?
+		     VPTE_BASE_SPITFIRE :
+		     VPTE_BASE_CHEETAH);
 	flush_tlb_range(mm,
-			VPTE_BASE + (s >> (PAGE_SHIFT - 3)),
-			VPTE_BASE + (e >> (PAGE_SHIFT - 3)));
+			vpte_base + (s >> (PAGE_SHIFT - 3)),
+			vpte_base + (e >> (PAGE_SHIFT - 3)));
 }
+#undef VPTE_BASE_SPITFIRE
+#undef VPTE_BASE_CHEETAH
 
 /* Page table allocation/freeing. */
 #ifdef CONFIG_SMP
@@ -214,9 +227,17 @@ extern __inline__ void free_pgd_slow(pgd_t *pgd)
 
 #endif /* CONFIG_SMP */
 
-extern pmd_t *get_pmd_slow(pgd_t *pgd, unsigned long address_premasked);
+#define pgd_populate(MM, PGD, PMD)	pgd_set(PGD, PMD)
+
+extern __inline__ pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+	pmd_t *pmd = (pmd_t *)__get_free_page(GFP_KERNEL);
+	if (pmd)
+		memset(pmd, 0, PAGE_SIZE);
+	return pmd;
+}
 
-extern __inline__ pmd_t *get_pmd_fast(void)
+extern __inline__ pmd_t *pmd_alloc_one_fast(struct mm_struct *mm, unsigned long address)
 {
 	unsigned long *ret;
 	int color = 0;
@@ -246,11 +267,13 @@ extern __inline__ void free_pmd_slow(pmd_t *pmd)
 	free_page((unsigned long)pmd);
 }
 
-extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted,
-			   unsigned long color);
+#define pmd_populate(MM, PMD, PTE)	pmd_set(PMD, PTE)
+
+extern pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address);
 
-extern __inline__ pte_t *get_pte_fast(unsigned long color)
+extern __inline__ pte_t *pte_alloc_one_fast(struct mm_struct *mm, unsigned long address)
 {
+	unsigned long color = (address >> (PAGE_SHIFT + 10)) & 0x1UL;
 	unsigned long *ret;
 
 	if((ret = (unsigned long *)pte_quicklist[color]) != NULL) {
@@ -274,46 +297,11 @@ extern __inline__ void free_pte_slow(pte_t *pte)
 	free_page((unsigned long)pte);
 }
 
-#define pte_free_kernel(pte)	free_pte_fast(pte)
 #define pte_free(pte)		free_pte_fast(pte)
-#define pmd_free_kernel(pmd)	free_pmd_fast(pmd)
 #define pmd_free(pmd)		free_pmd_fast(pmd)
 #define pgd_free(pgd)		free_pgd_fast(pgd)
 #define pgd_alloc()		get_pgd_fast()
 
-extern inline pte_t * pte_alloc(pmd_t *pmd, unsigned long address)
-{
-	address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
-	if (pmd_none(*pmd)) {
-		/* Be careful, address can be just about anything... */
-		unsigned long color = (((unsigned long)pmd)>>2UL) & 0x1UL;
-		pte_t *page = get_pte_fast(color);
-
-		if (!page)
-			return get_pte_slow(pmd, address, color);
-		pmd_set(pmd, page);
-		return page + address;
-	}
-	return (pte_t *) pmd_page(*pmd) + address;
-}
-
-extern inline pmd_t * pmd_alloc(pgd_t *pgd, unsigned long address)
-{
-	address = (address >> PMD_SHIFT) & (REAL_PTRS_PER_PMD - 1);
-	if (pgd_none(*pgd)) {
-		pmd_t *page = get_pmd_fast();
-
-		if (!page)
-			return get_pmd_slow(pgd, address);
-		pgd_set(pgd, page);
-		return page + address;
-	}
-	return (pmd_t *) pgd_page(*pgd) + address;
-}
-
-#define pte_alloc_kernel(pmd, addr)	pte_alloc(pmd, addr)
-#define pmd_alloc_kernel(pgd, addr)	pmd_alloc(pgd, addr)
-
 extern int do_check_pgt_cache(int, int);
 
 #endif /* _SPARC64_PGALLOC_H */
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
index a01042346..54dc5356e 100644
--- a/include/asm-sparc64/pgtable.h
+++ b/include/asm-sparc64/pgtable.h
@@ -1,4 +1,4 @@
-/* $Id: pgtable.h,v 1.135 2000/11/08 04:49:24 davem Exp $
+/* $Id: pgtable.h,v 1.138 2001/03/08 09:55:56 davem Exp $
  * pgtable.h: SpitFire page table operations.
  *
  * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
@@ -27,6 +27,11 @@
  */
 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
 
+/* XXX All of this needs to be rethought so we can take advantage
+ * XXX cheetah's full 64-bit virtual address space, ie. no more hole
+ * XXX in the middle like on spitfire. -DaveM
+ */
+
 /* PMD_SHIFT determines the size of the area a second-level page table can map */
 #define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-3))
 #define PMD_SIZE	(1UL << PMD_SHIFT)
@@ -70,7 +75,7 @@
 
 #endif /* !(__ASSEMBLY__) */
 
-/* SpitFire TTE bits. */
+/* Spitfire/Cheetah TTE bits. */
 #define _PAGE_VALID	0x8000000000000000	/* Valid TTE                          */
 #define _PAGE_R		0x8000000000000000	/* Used to keep ref bit up to date    */
 #define _PAGE_SZ4MB	0x6000000000000000	/* 4MB Page                           */
@@ -79,10 +84,10 @@
 #define _PAGE_SZ8K	0x0000000000000000	/* 8K Page                            */
 #define _PAGE_NFO	0x1000000000000000	/* No Fault Only                      */
 #define _PAGE_IE	0x0800000000000000	/* Invert Endianness                  */
-#define _PAGE_SOFT2	0x07FC000000000000	/* Second set of software bits        */
-#define _PAGE_DIAG	0x0003FE0000000000	/* Diagnostic TTE bits                */
-#define _PAGE_PADDR	0x000001FFFFFFE000	/* Physical Address bits [40:13]      */
-#define _PAGE_SOFT	0x0000000000001F80	/* First set of software bits         */
+#define _PAGE_SN	0x0000800000000000	/* (Cheetah) Snoop                    */
+#define _PAGE_PADDR_SF	0x000001FFFFFFE000	/* (Spitfire) Phys Address [40:13]    */
+#define _PAGE_PADDR	0x000007FFFFFFE000	/* (Cheetah) Phys Address [42:13]     */
+#define _PAGE_SOFT	0x0000000000001F80	/* Software bits                      */
 #define _PAGE_L		0x0000000000000040	/* Locked TTE                         */
 #define _PAGE_CP	0x0000000000000020	/* Cacheable in Physical Cache        */
 #define _PAGE_CV	0x0000000000000010	/* Cacheable in Virtual Cache         */
diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h
index 5e9203f13..ea5b27596 100644
--- a/include/asm-sparc64/processor.h
+++ b/include/asm-sparc64/processor.h
@@ -1,4 +1,4 @@
-/* $Id: processor.h,v 1.68 2000/12/31 10:05:43 davem Exp $
+/* $Id: processor.h,v 1.69 2001/03/08 22:08:51 davem Exp $
  * include/asm-sparc64/processor.h
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
@@ -60,8 +60,7 @@ struct thread_struct {
 	/* D$ line 2, 3, 4 */
 	struct pt_regs *kregs;
 	unsigned long *utraps;
-	unsigned char gsr[7];
-	unsigned char __pad3;
+	unsigned long gsr[7];
 	unsigned long xfsr[7];
 
 	struct reg_window reg_window[NSWINS];
@@ -97,8 +96,8 @@ struct thread_struct {
    0,       0,       0,          0,			\
 /* fault_address, fpsaved, __pad2, kregs, */		\
    0,             { 0 },   0,      0,			\
-/* utraps, gsr,   __pad3, xfsr, */			\
-   0,	   { 0 }, 0,      { 0 },			\
+/* utraps, gsr,   xfsr, */				\
+   0,	   { 0 }, { 0 },				\
 /* reg_window */					\
    { { { 0, }, { 0, } }, }, 				\
 /* rwbuf_stkptrs */					\
diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h
index 3898efdd2..2cd547a6f 100644
--- a/include/asm-sparc64/smp.h
+++ b/include/asm-sparc64/smp.h
@@ -10,6 +10,7 @@
 #include <linux/threads.h>
 #include <asm/asi.h>
 #include <asm/starfire.h>
+#include <asm/spitfire.h>
 
 #ifndef __ASSEMBLY__
 /* PROM provided per-processor information we need
@@ -60,6 +61,7 @@ extern struct cpuinfo_sparc cpu_data[NR_CPUS];
  
 extern unsigned char boot_cpu_id;
 extern unsigned long cpu_present_map;
+#define cpu_online_map cpu_present_map
 
 /*
  *	General functions that each host system must provide.
@@ -83,7 +85,13 @@ extern __inline__ int cpu_number_map(int cpu)
 
 extern __inline__ int hard_smp_processor_id(void)
 {
-	if(this_is_starfire != 0) {
+	if (tlb_type == cheetah) {
+		unsigned long safari_config;
+		__asm__ __volatile__("ldxa [%%g0] %1, %0"
+				     : "=r" (safari_config)
+				     : "i" (ASI_SAFARI_CONFIG));
+		return ((safari_config >> 17) & 0x3ff);
+	} else if (this_is_starfire != 0) {
 		return starfire_hard_smp_processor_id();
 	} else {
 		unsigned long upaconfig;
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index f24ff8415..e62c4ab52 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -1,4 +1,4 @@
-/* $Id: spitfire.h,v 1.10 2000/10/06 13:10:29 anton Exp $
+/* $Id: spitfire.h,v 1.14 2001/03/22 07:26:04 davem Exp $
  * spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
@@ -29,6 +29,23 @@
 
 #ifndef __ASSEMBLY__
 
+enum ultra_tlb_layout {
+	spitfire = 0,
+	cheetah = 1
+};
+
+extern enum ultra_tlb_layout tlb_type;
+
+#define SPARC64_USE_STICK	(tlb_type == cheetah)
+
+#define SPITFIRE_HIGHEST_LOCKED_TLBENT	(64 - 1)
+#define CHEETAH_HIGHEST_LOCKED_TLBENT	(16 - 1)
+
+#define sparc64_highest_locked_tlbent()	\
+	(tlb_type == spitfire ? \
+	 SPITFIRE_HIGHEST_LOCKED_TLBENT : \
+	 CHEETAH_HIGHEST_LOCKED_TLBENT)
+
 extern __inline__ unsigned long spitfire_get_isfsr(void)
 {
 	unsigned long ret;
@@ -61,13 +78,17 @@ extern __inline__ unsigned long spitfire_get_sfar(void)
 
 extern __inline__ void spitfire_put_isfsr(unsigned long sfsr)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2" :
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
+			     : /* no outputs */
 			     : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU));
 }
 
 extern __inline__ void spitfire_put_dsfsr(unsigned long sfsr)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2" :
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
+			     : /* no outputs */
 			     : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU));
 }
 
@@ -83,11 +104,12 @@ extern __inline__ unsigned long spitfire_get_primary_context(void)
 
 extern __inline__ void spitfire_set_primary_context(unsigned long ctx)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2"
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (ctx & 0x3ff),
 			       "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
-	membar("#Sync");
+	__asm__ __volatile__ ("membar #Sync" : : : "memory");
 }
 
 extern __inline__ unsigned long spitfire_get_secondary_context(void)
@@ -102,11 +124,12 @@ extern __inline__ unsigned long spitfire_get_secondary_context(void)
 
 extern __inline__ void spitfire_set_secondary_context(unsigned long ctx)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2"
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (ctx & 0x3ff),
 			       "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU));
-	membar("#Sync");
+	__asm__ __volatile__ ("membar #Sync" : : : "memory");
 }
 
 /* The data cache is write through, so this just invalidates the
@@ -114,10 +137,11 @@ extern __inline__ void spitfire_set_secondary_context(unsigned long ctx)
  */
 extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2"
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
-	membar("#Sync");
+	__asm__ __volatile__ ("membar #Sync" : : : "memory");
 }
 
 /* The instruction cache lines are flushed with this, but note that
@@ -128,7 +152,8 @@ extern __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
  */
 extern __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2"
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
 }
@@ -140,6 +165,10 @@ extern __inline__ unsigned long spitfire_get_dtlb_data(int entry)
 	__asm__ __volatile__("ldxa	[%1] %2, %0"
 			     : "=r" (data)
 			     : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
+
+	/* Clear TTE diag bits. */
+	data &= ~0x0003fe0000000000UL;
+
 	return data;
 }
 
@@ -155,7 +184,8 @@ extern __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
 
 extern __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2"
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (data), "r" (entry << 3),
 			       "i" (ASI_DTLB_DATA_ACCESS));
@@ -168,6 +198,10 @@ extern __inline__ unsigned long spitfire_get_itlb_data(int entry)
 	__asm__ __volatile__("ldxa	[%1] %2, %0"
 			     : "=r" (data)
 			     : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
+
+	/* Clear TTE diag bits. */
+	data &= ~0x0003fe0000000000UL;
+
 	return data;
 }
 
@@ -183,7 +217,8 @@ extern __inline__ unsigned long spitfire_get_itlb_tag(int entry)
 
 extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
 {
-	__asm__ __volatile__("stxa	%0, [%1] %2"
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (data), "r" (entry << 3),
 			       "i" (ASI_ITLB_DATA_ACCESS));
@@ -194,42 +229,48 @@ extern __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
 /* Context level flushes. */
 extern __inline__ void spitfire_flush_dtlb_primary_context(void)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (0x40), "i" (ASI_DMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_itlb_primary_context(void)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (0x40), "i" (ASI_IMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_dtlb_secondary_context(void)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (0x50), "i" (ASI_DMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_itlb_secondary_context(void)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (0x50), "i" (ASI_IMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_dtlb_nucleus_context(void)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (0x60), "i" (ASI_DMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_itlb_nucleus_context(void)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (0x60), "i" (ASI_IMMU_DEMAP));
 }
@@ -237,46 +278,209 @@ extern __inline__ void spitfire_flush_itlb_nucleus_context(void)
 /* Page level flushes. */
 extern __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (page), "i" (ASI_DMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_itlb_primary_page(unsigned long page)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (page), "i" (ASI_IMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
 }
 
 extern __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
 {
-	__asm__ __volatile__("stxa	%%g0, [%0] %1"
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
 			     : /* No outputs */
 			     : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
 }
 
+/* Cheetah has "all non-locked" tlb flushes. */
+extern __inline__ void cheetah_flush_dtlb_all(void)
+{
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
+			     : /* No outputs */
+			     : "r" (0x80), "i" (ASI_DMMU_DEMAP));
+}
+
+extern __inline__ void cheetah_flush_itlb_all(void)
+{
+	__asm__ __volatile__("stxa	%%g0, [%0] %1\n\t"
+			     "membar	#Sync"
+			     : /* No outputs */
+			     : "r" (0x80), "i" (ASI_IMMU_DEMAP));
+}
+
+/* Cheetah has a 4-tlb layout so direct access is a bit different.
+ * The first two TLBs are fully assosciative, hold 16 entries, and are
+ * used only for locked and >8K sized translations.  One exists for
+ * data accesses and one for instruction accesses.
+ *
+ * The third TLB is for data accesses to 8K non-locked translations, is
+ * 2 way assosciative, and holds 512 entries.  The fourth TLB is for
+ * instruction accesses to 8K non-locked translations, is 2 way
+ * assosciative, and holds 128 entries.
+ */
+extern __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
+{
+	unsigned long data;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (data)
+			     : "r" ((0 << 16) | (entry << 3)),
+			     "i" (ASI_DTLB_DATA_ACCESS));
+
+	return data;
+}
+
+extern __inline__ unsigned long cheetah_get_litlb_data(int entry)
+{
+	unsigned long data;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (data)
+			     : "r" ((0 << 16) | (entry << 3)),
+			     "i" (ASI_ITLB_DATA_ACCESS));
+
+	return data;
+}
+
+extern __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
+{
+	unsigned long tag;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (tag)
+			     : "r" ((0 << 16) | (entry << 3)),
+			     "i" (ASI_DTLB_TAG_READ));
+
+	return tag;
+}
+
+extern __inline__ unsigned long cheetah_get_litlb_tag(int entry)
+{
+	unsigned long tag;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (tag)
+			     : "r" ((0 << 16) | (entry << 3)),
+			     "i" (ASI_ITLB_TAG_READ));
+
+	return tag;
+}
+
+extern __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
+{
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
+			     : /* No outputs */
+			     : "r" (data),
+			       "r" ((0 << 16) | (entry << 3)),
+			       "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+extern __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
+{
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
+			     : /* No outputs */
+			     : "r" (data),
+			       "r" ((0 << 16) | (entry << 3)),
+			       "i" (ASI_ITLB_DATA_ACCESS));
+}
+
+extern __inline__ unsigned long cheetah_get_dtlb_data(int entry)
+{
+	unsigned long data;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (data)
+			     : "r" ((2 << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
+
+	return data;
+}
+
+extern __inline__ unsigned long cheetah_get_dtlb_tag(int entry)
+{
+	unsigned long tag;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (tag)
+			     : "r" ((2 << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
+	return tag;
+}
+
+extern __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data)
+{
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
+			     : /* No outputs */
+			     : "r" (data),
+			       "r" ((2 << 16) | (entry << 3)),
+			       "i" (ASI_DTLB_DATA_ACCESS));
+}
+
+extern __inline__ unsigned long cheetah_get_itlb_data(int entry)
+{
+	unsigned long data;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (data)
+			     : "r" ((2 << 16) | (entry << 3)),
+                               "i" (ASI_ITLB_DATA_ACCESS));
+
+	return data;
+}
+
+extern __inline__ unsigned long cheetah_get_itlb_tag(int entry)
+{
+	unsigned long tag;
+
+	__asm__ __volatile__("ldxa	[%1] %2, %0"
+			     : "=r" (tag)
+			     : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
+	return tag;
+}
+
+extern __inline__ void cheetah_put_itlb_data(int entry, unsigned long data)
+{
+	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
+			     "membar	#Sync"
+			     : /* No outputs */
+			     : "r" (data), "r" ((2 << 16) | (entry << 3)),
+			       "i" (ASI_ITLB_DATA_ACCESS));
+}
+
 #endif /* !(__ASSEMBLY__) */
 
 #endif /* !(_SPARC64_SPITFIRE_H) */