summaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/asmmacro.h160
-rw-r--r--include/asm-mips/offset.h12
-rw-r--r--include/asm-mips/processor.h2
-rw-r--r--include/asm-mips/ptrace.h2
-rw-r--r--include/asm-mips/stackframe.h152
-rw-r--r--include/asm-mips/unistd.h27
6 files changed, 234 insertions, 121 deletions
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index 2921797e0..ba4205dbd 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -1,89 +1,161 @@
-/* $Id: asmmacro.h,v 1.1.1.1 1997/06/01 03:17:13 ralf Exp $
+/*
* asmmacro.h: Assembler macros to make things easier to read.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1998 Ralf Baechle
+ *
+ * $Id: asmmacro.h,v 1.3 1998/03/23 06:34:33 ralf Exp $
*/
-
#ifndef __MIPS_ASMMACRO_H
#define __MIPS_ASMMACRO_H
#include <asm/offset.h>
-#define FPU_SAVE_16ODD(thread) \
- swc1 $f1, (THREAD_FPU + 0x08)(thread); \
- swc1 $f3, (THREAD_FPU + 0x18)(thread); \
- swc1 $f5, (THREAD_FPU + 0x28)(thread); \
- swc1 $f7, (THREAD_FPU + 0x38)(thread); \
- swc1 $f9, (THREAD_FPU + 0x48)(thread); \
- swc1 $f11, (THREAD_FPU + 0x58)(thread); \
- swc1 $f13, (THREAD_FPU + 0x68)(thread); \
- swc1 $f15, (THREAD_FPU + 0x78)(thread); \
- swc1 $f17, (THREAD_FPU + 0x88)(thread); \
- swc1 $f19, (THREAD_FPU + 0x98)(thread); \
- swc1 $f21, (THREAD_FPU + 0xa8)(thread); \
- swc1 $f23, (THREAD_FPU + 0xb8)(thread); \
- swc1 $f25, (THREAD_FPU + 0xc8)(thread); \
- swc1 $f27, (THREAD_FPU + 0xd8)(thread); \
- swc1 $f29, (THREAD_FPU + 0xe8)(thread); \
- swc1 $f31, (THREAD_FPU + 0xf8)(thread);
-
-
-#define FPU_RESTORE_16ODD(thread) \
- lwc1 $f1, (THREAD_FPU + 0x08)(thread); \
- lwc1 $f3, (THREAD_FPU + 0x18)(thread); \
- lwc1 $f5, (THREAD_FPU + 0x28)(thread); \
- lwc1 $f7, (THREAD_FPU + 0x38)(thread); \
- lwc1 $f9, (THREAD_FPU + 0x48)(thread); \
- lwc1 $f11, (THREAD_FPU + 0x58)(thread); \
- lwc1 $f13, (THREAD_FPU + 0x68)(thread); \
- lwc1 $f15, (THREAD_FPU + 0x78)(thread); \
- lwc1 $f17, (THREAD_FPU + 0x88)(thread); \
- lwc1 $f19, (THREAD_FPU + 0x98)(thread); \
- lwc1 $f21, (THREAD_FPU + 0xa8)(thread); \
- lwc1 $f23, (THREAD_FPU + 0xb8)(thread); \
- lwc1 $f25, (THREAD_FPU + 0xc8)(thread); \
- lwc1 $f27, (THREAD_FPU + 0xd8)(thread); \
- lwc1 $f29, (THREAD_FPU + 0xe8)(thread); \
- lwc1 $f31, (THREAD_FPU + 0xf8)(thread);
-
#define FPU_SAVE_16EVEN(thread, tmp) \
cfc1 tmp, fcr31; \
+ sdc1 $f2, (THREAD_FPU + 0x010)(thread); \
+ sdc1 $f4, (THREAD_FPU + 0x020)(thread); \
+ sdc1 $f6, (THREAD_FPU + 0x030)(thread); \
+ sdc1 $f8, (THREAD_FPU + 0x040)(thread); \
+ sdc1 $f10, (THREAD_FPU + 0x050)(thread); \
+ sdc1 $f12, (THREAD_FPU + 0x060)(thread); \
+ sdc1 $f14, (THREAD_FPU + 0x070)(thread); \
+ sdc1 $f16, (THREAD_FPU + 0x080)(thread); \
+ sdc1 $f18, (THREAD_FPU + 0x090)(thread); \
+ sdc1 $f20, (THREAD_FPU + 0x0a0)(thread); \
+ sdc1 $f22, (THREAD_FPU + 0x0b0)(thread); \
+ sdc1 $f24, (THREAD_FPU + 0x0c0)(thread); \
+ sdc1 $f26, (THREAD_FPU + 0x0d0)(thread); \
+ sdc1 $f28, (THREAD_FPU + 0x0e0)(thread); \
+ sdc1 $f30, (THREAD_FPU + 0x0f0)(thread); \
+ sw tmp, (THREAD_FPU + 0x100)(thread)
+
+#define FPU_SAVE_16ODD(thread) \
+ sdc1 $f1, (THREAD_FPU + 0x08)(thread); \
+ sdc1 $f3, (THREAD_FPU + 0x18)(thread); \
+ sdc1 $f5, (THREAD_FPU + 0x28)(thread); \
+ sdc1 $f7, (THREAD_FPU + 0x38)(thread); \
+ sdc1 $f9, (THREAD_FPU + 0x48)(thread); \
+ sdc1 $f11, (THREAD_FPU + 0x58)(thread); \
+ sdc1 $f13, (THREAD_FPU + 0x68)(thread); \
+ sdc1 $f15, (THREAD_FPU + 0x78)(thread); \
+ sdc1 $f17, (THREAD_FPU + 0x88)(thread); \
+ sdc1 $f19, (THREAD_FPU + 0x98)(thread); \
+ sdc1 $f21, (THREAD_FPU + 0xa8)(thread); \
+ sdc1 $f23, (THREAD_FPU + 0xb8)(thread); \
+ sdc1 $f25, (THREAD_FPU + 0xc8)(thread); \
+ sdc1 $f27, (THREAD_FPU + 0xd8)(thread); \
+ sdc1 $f29, (THREAD_FPU + 0xe8)(thread); \
+ sdc1 $f31, (THREAD_FPU + 0xf8)(thread)
+
+#define FPU_SAVE(thread,tmp) \
+ cfc1 tmp, fcr31; \
+ swc1 $f0, (THREAD_FPU + 0x000)(thread); \
+ swc1 $f1, (THREAD_FPU + 0x008)(thread); \
swc1 $f2, (THREAD_FPU + 0x010)(thread); \
+ swc1 $f3, (THREAD_FPU + 0x018)(thread); \
swc1 $f4, (THREAD_FPU + 0x020)(thread); \
+ swc1 $f5, (THREAD_FPU + 0x028)(thread); \
swc1 $f6, (THREAD_FPU + 0x030)(thread); \
+ swc1 $f7, (THREAD_FPU + 0x038)(thread); \
swc1 $f8, (THREAD_FPU + 0x040)(thread); \
+ swc1 $f9, (THREAD_FPU + 0x048)(thread); \
swc1 $f10, (THREAD_FPU + 0x050)(thread); \
+ swc1 $f11, (THREAD_FPU + 0x058)(thread); \
swc1 $f12, (THREAD_FPU + 0x060)(thread); \
+ swc1 $f13, (THREAD_FPU + 0x068)(thread); \
swc1 $f14, (THREAD_FPU + 0x070)(thread); \
+ swc1 $f15, (THREAD_FPU + 0x078)(thread); \
swc1 $f16, (THREAD_FPU + 0x080)(thread); \
+ swc1 $f17, (THREAD_FPU + 0x088)(thread); \
swc1 $f18, (THREAD_FPU + 0x090)(thread); \
+ swc1 $f19, (THREAD_FPU + 0x098)(thread); \
swc1 $f20, (THREAD_FPU + 0x0a0)(thread); \
+ swc1 $f21, (THREAD_FPU + 0x0a8)(thread); \
swc1 $f22, (THREAD_FPU + 0x0b0)(thread); \
+ swc1 $f23, (THREAD_FPU + 0x0b8)(thread); \
swc1 $f24, (THREAD_FPU + 0x0c0)(thread); \
+ swc1 $f25, (THREAD_FPU + 0x0c8)(thread); \
swc1 $f26, (THREAD_FPU + 0x0d0)(thread); \
+ swc1 $f27, (THREAD_FPU + 0x0d8)(thread); \
swc1 $f28, (THREAD_FPU + 0x0e0)(thread); \
+ swc1 $f29, (THREAD_FPU + 0x0e8)(thread); \
swc1 $f30, (THREAD_FPU + 0x0f0)(thread); \
- sw tmp, (THREAD_FPU + 0x100)(thread);
-
+ swc1 $f31, (THREAD_FPU + 0x0f8)(thread); \
+ sw tmp, (THREAD_FPU + 0x100)(thread)
#define FPU_RESTORE_16EVEN(thread, tmp) \
lw tmp, (THREAD_FPU + 0x100)(thread); \
+ ldc1 $f2, (THREAD_FPU + 0x010)(thread); \
+ ldc1 $f4, (THREAD_FPU + 0x020)(thread); \
+ ldc1 $f6, (THREAD_FPU + 0x030)(thread); \
+ ldc1 $f8, (THREAD_FPU + 0x040)(thread); \
+ ldc1 $f10, (THREAD_FPU + 0x050)(thread); \
+ ldc1 $f12, (THREAD_FPU + 0x060)(thread); \
+ ldc1 $f14, (THREAD_FPU + 0x070)(thread); \
+ ldc1 $f16, (THREAD_FPU + 0x080)(thread); \
+ ldc1 $f18, (THREAD_FPU + 0x090)(thread); \
+ ldc1 $f20, (THREAD_FPU + 0x0a0)(thread); \
+ ldc1 $f22, (THREAD_FPU + 0x0b0)(thread); \
+ ldc1 $f24, (THREAD_FPU + 0x0c0)(thread); \
+ ldc1 $f26, (THREAD_FPU + 0x0d0)(thread); \
+ ldc1 $f28, (THREAD_FPU + 0x0e0)(thread); \
+ ldc1 $f30, (THREAD_FPU + 0x0f0)(thread); \
+ ctc1 tmp, fcr31
+
+#define FPU_RESTORE_16ODD(thread) \
+ ldc1 $f1, (THREAD_FPU + 0x08)(thread); \
+ ldc1 $f3, (THREAD_FPU + 0x18)(thread); \
+ ldc1 $f5, (THREAD_FPU + 0x28)(thread); \
+ ldc1 $f7, (THREAD_FPU + 0x38)(thread); \
+ ldc1 $f9, (THREAD_FPU + 0x48)(thread); \
+ ldc1 $f11, (THREAD_FPU + 0x58)(thread); \
+ ldc1 $f13, (THREAD_FPU + 0x68)(thread); \
+ ldc1 $f15, (THREAD_FPU + 0x78)(thread); \
+ ldc1 $f17, (THREAD_FPU + 0x88)(thread); \
+ ldc1 $f19, (THREAD_FPU + 0x98)(thread); \
+ ldc1 $f21, (THREAD_FPU + 0xa8)(thread); \
+ ldc1 $f23, (THREAD_FPU + 0xb8)(thread); \
+ ldc1 $f25, (THREAD_FPU + 0xc8)(thread); \
+ ldc1 $f27, (THREAD_FPU + 0xd8)(thread); \
+ ldc1 $f29, (THREAD_FPU + 0xe8)(thread); \
+ ldc1 $f31, (THREAD_FPU + 0xf8)(thread)
+
+#define FPU_RESTORE(thread,tmp) \
+ lw tmp, (THREAD_FPU + 0x100)(thread); \
+ lwc1 $f0, (THREAD_FPU + 0x000)(thread); \
+ lwc1 $f1, (THREAD_FPU + 0x008)(thread); \
lwc1 $f2, (THREAD_FPU + 0x010)(thread); \
+ lwc1 $f3, (THREAD_FPU + 0x018)(thread); \
lwc1 $f4, (THREAD_FPU + 0x020)(thread); \
+ lwc1 $f5, (THREAD_FPU + 0x028)(thread); \
lwc1 $f6, (THREAD_FPU + 0x030)(thread); \
+ lwc1 $f7, (THREAD_FPU + 0x038)(thread); \
lwc1 $f8, (THREAD_FPU + 0x040)(thread); \
+ lwc1 $f9, (THREAD_FPU + 0x048)(thread); \
lwc1 $f10, (THREAD_FPU + 0x050)(thread); \
+ lwc1 $f11, (THREAD_FPU + 0x058)(thread); \
lwc1 $f12, (THREAD_FPU + 0x060)(thread); \
+ lwc1 $f13, (THREAD_FPU + 0x068)(thread); \
lwc1 $f14, (THREAD_FPU + 0x070)(thread); \
+ lwc1 $f15, (THREAD_FPU + 0x078)(thread); \
lwc1 $f16, (THREAD_FPU + 0x080)(thread); \
+ lwc1 $f17, (THREAD_FPU + 0x088)(thread); \
lwc1 $f18, (THREAD_FPU + 0x090)(thread); \
+ lwc1 $f19, (THREAD_FPU + 0x098)(thread); \
lwc1 $f20, (THREAD_FPU + 0x0a0)(thread); \
+ lwc1 $f21, (THREAD_FPU + 0x0a8)(thread); \
lwc1 $f22, (THREAD_FPU + 0x0b0)(thread); \
+ lwc1 $f23, (THREAD_FPU + 0x0b8)(thread); \
lwc1 $f24, (THREAD_FPU + 0x0c0)(thread); \
+ lwc1 $f25, (THREAD_FPU + 0x0c8)(thread); \
lwc1 $f26, (THREAD_FPU + 0x0d0)(thread); \
+ lwc1 $f27, (THREAD_FPU + 0x0d8)(thread); \
lwc1 $f28, (THREAD_FPU + 0x0e0)(thread); \
+ lwc1 $f29, (THREAD_FPU + 0x0e8)(thread); \
lwc1 $f30, (THREAD_FPU + 0x0f0)(thread); \
- ctc1 tmp, fcr31;
+ lwc1 $f31, (THREAD_FPU + 0x0f8)(thread); \
+ ctc1 tmp, fcr31
#define CPU_SAVE_NONSCRATCH(thread) \
sw s0, THREAD_REG16(thread); \
@@ -95,7 +167,7 @@
sw s6, THREAD_REG22(thread); \
sw s7, THREAD_REG23(thread); \
sw sp, THREAD_REG29(thread); \
- sw fp, THREAD_REG30(thread);
+ sw fp, THREAD_REG30(thread)
#define CPU_RESTORE_NONSCRATCH(thread) \
lw s0, THREAD_REG16(thread); \
@@ -108,6 +180,6 @@
lw s7, THREAD_REG23(thread); \
lw sp, THREAD_REG29(thread); \
lw fp, THREAD_REG30(thread); \
- lw ra, THREAD_REG31(thread);
+ lw ra, THREAD_REG31(thread)
#endif /* !(__MIPS_ASMMACRO_H) */
diff --git a/include/asm-mips/offset.h b/include/asm-mips/offset.h
index cf8583f79..3c6d274ce 100644
--- a/include/asm-mips/offset.h
+++ b/include/asm-mips/offset.h
@@ -38,13 +38,11 @@
#define PT_R31 148
#define PT_LO 152
#define PT_HI 156
-#define PT_OR2 160
-#define PT_OR7 164
-#define PT_EPC 168
-#define PT_BVADDR 172
-#define PT_STATUS 176
-#define PT_CAUSE 180
-#define PT_SIZE 184
+#define PT_EPC 160
+#define PT_BVADDR 164
+#define PT_STATUS 168
+#define PT_CAUSE 172
+#define PT_SIZE 176
/* MIPS task_struct offsets. */
#define TASK_STATE 0
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 86c9ddb00..84d6830a7 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -5,7 +5,7 @@
* written by Ralf Baechle
* Modified further for R[236]000 compatibility by Paul M. Antoine
*
- * $Id: processor.h,v 1.6 1998/03/22 23:27:19 ralf Exp $
+ * $Id: processor.h,v 1.11 1998/03/22 20:43:52 ralf Exp $
*/
#ifndef __ASM_MIPS_PROCESSOR_H
#define __ASM_MIPS_PROCESSOR_H
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index ebe4cf888..ac3876131 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -30,8 +30,6 @@ struct pt_regs {
/* Other saved registers. */
unsigned long lo;
unsigned long hi;
- unsigned long orig_reg2;
- unsigned long orig_reg7;
/*
* saved cp0 registers
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 0ee12f742..e925dcd50 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -3,7 +3,7 @@
*
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Paul M. Antoine.
*
- * $Id: stackframe.h,v 1.4 1998/03/22 23:27:19 ralf Exp $
+ * $Id: stackframe.h,v 1.6 1998/03/26 07:39:21 ralf Exp $
*/
#ifndef __ASM_MIPS_STACKFRAME_H
#define __ASM_MIPS_STACKFRAME_H
@@ -11,7 +11,53 @@
#include <asm/asm.h>
#include <asm/offset.h>
-#define SAVE_ALL \
+#define SAVE_AT \
+ sw $1, PT_R1(sp)
+
+#define SAVE_TEMP \
+ mfhi v1; \
+ sw $8, PT_R8(sp); \
+ sw $9, PT_R9(sp); \
+ sw v1, PT_HI(sp); \
+ mflo v1; \
+ sw $10,PT_R10(sp); \
+ sw $11, PT_R11(sp); \
+ sw v1, PT_LO(sp); \
+ sw $12, PT_R12(sp); \
+ sw $13, PT_R13(sp); \
+ sw $14, PT_R14(sp); \
+ sw $15, PT_R15(sp); \
+ sw $24, PT_R24(sp)
+
+#define SAVE_STATIC \
+ sw $16, PT_R16(sp); \
+ sw $17, PT_R17(sp); \
+ sw $18, PT_R18(sp); \
+ sw $19, PT_R19(sp); \
+ sw $20, PT_R20(sp); \
+ sw $21, PT_R21(sp); \
+ sw $22, PT_R22(sp); \
+ sw $23, PT_R23(sp); \
+ sw $30, PT_R30(sp)
+
+#define __str2(x) #x
+#define __str(x) __str2(x)
+
+#define save_static(frame) \
+ __asm__ __volatile__( \
+ "sw\t$16,"__str(PT_R16)"(%0)\n\t" \
+ "sw\t$17,"__str(PT_R17)"(%0)\n\t" \
+ "sw\t$18,"__str(PT_R18)"(%0)\n\t" \
+ "sw\t$19,"__str(PT_R19)"(%0)\n\t" \
+ "sw\t$20,"__str(PT_R20)"(%0)\n\t" \
+ "sw\t$21,"__str(PT_R21)"(%0)\n\t" \
+ "sw\t$22,"__str(PT_R22)"(%0)\n\t" \
+ "sw\t$23,"__str(PT_R23)"(%0)\n\t" \
+ "sw\t$30,"__str(PT_R30)"(%0)\n\t" \
+ : /* No outputs */ \
+ : "r" (frame))
+
+#define SAVE_SOME \
.set push; \
.set reorder; \
mfc0 k0, CP0_STATUS; \
@@ -28,8 +74,6 @@
subu sp, k1, PT_SIZE; \
sw k0, PT_R29(sp); \
sw $3, PT_R3(sp); \
- sw $1, PT_R1(sp); \
- sw $2, PT_OR2(sp); \
sw $0, PT_R0(sp); \
mfc0 v1, CP0_STATUS; \
sw $2, PT_R2(sp); \
@@ -42,41 +86,52 @@
mfc0 v1, CP0_EPC; \
sw $7, PT_R7(sp); \
sw v1, PT_EPC(sp); \
- sw $7, PT_OR7(sp); \
- sw $8, PT_R8(sp); \
- mfhi v1; \
- sw $9, PT_R9(sp); \
- sw v1, PT_HI(sp); \
- sw $10,PT_R10(sp); \
- mflo v1; \
- sw $11, PT_R11(sp); \
- sw v1, PT_LO(sp); \
- sw $12, PT_R12(sp); \
- sw $13, PT_R13(sp); \
- sw $14, PT_R14(sp); \
- sw $15, PT_R15(sp); \
- sw $16, PT_R16(sp); \
- sw $17, PT_R17(sp); \
- sw $18, PT_R18(sp); \
- sw $19, PT_R19(sp); \
- sw $20, PT_R20(sp); \
- sw $21, PT_R21(sp); \
- sw $22, PT_R22(sp); \
- sw $23, PT_R23(sp); \
- sw $24, PT_R24(sp); \
sw $25, PT_R25(sp); \
sw $28, PT_R28(sp); \
- sw $30, PT_R30(sp); \
sw $31, PT_R31(sp); \
ori $28, sp, 0x1fff; \
xori $28, 0x1fff; \
.set pop
-/*
- * Note that we restore the IE flags from stack. This means
- * that a modified IE mask will be nullified.
- */
-#define RESTORE_ALL \
+#define SAVE_ALL \
+ SAVE_SOME; \
+ SAVE_AT; \
+ SAVE_TEMP; \
+ SAVE_STATIC
+
+#define RESTORE_AT \
+ lw $1, PT_R1(sp); \
+
+#define RESTORE_SP \
+ lw sp, PT_R29(sp)
+
+#define RESTORE_TEMP \
+ lw $24, PT_LO(sp); \
+ lw $8, PT_R8(sp); \
+ lw $9, PT_R9(sp); \
+ mtlo $24; \
+ lw $24, PT_HI(sp); \
+ lw $10,PT_R10(sp); \
+ lw $11, PT_R11(sp); \
+ mthi $24; \
+ lw $12, PT_R12(sp); \
+ lw $13, PT_R13(sp); \
+ lw $14, PT_R14(sp); \
+ lw $15, PT_R15(sp); \
+ lw $24, PT_R24(sp)
+
+#define RESTORE_STATIC \
+ lw $16, PT_R16(sp); \
+ lw $17, PT_R17(sp); \
+ lw $18, PT_R18(sp); \
+ lw $19, PT_R19(sp); \
+ lw $20, PT_R20(sp); \
+ lw $21, PT_R21(sp); \
+ lw $22, PT_R22(sp); \
+ lw $23, PT_R23(sp); \
+ lw $30, PT_R30(sp)
+
+#define RESTORE_SOME \
.set push; \
.set reorder; \
mfc0 t0, CP0_STATUS; \
@@ -85,42 +140,25 @@
xori t0, 0x1f; \
mtc0 t0, CP0_STATUS; \
lw v0, PT_STATUS(sp); \
- lw v1, PT_LO(sp); \
mtc0 v0, CP0_STATUS; \
- mtlo v1; \
- lw v0, PT_HI(sp); \
lw v1, PT_EPC(sp); \
- mthi v0; \
mtc0 v1, CP0_EPC; \
lw $31, PT_R31(sp); \
- lw $30, PT_R30(sp); \
lw $28, PT_R28(sp); \
lw $25, PT_R25(sp); \
- lw $24, PT_R24(sp); \
- lw $23, PT_R23(sp); \
- lw $22, PT_R22(sp); \
- lw $21, PT_R21(sp); \
- lw $20, PT_R20(sp); \
- lw $19, PT_R19(sp); \
- lw $18, PT_R18(sp); \
- lw $17, PT_R17(sp); \
- lw $16, PT_R16(sp); \
- lw $15, PT_R15(sp); \
- lw $14, PT_R14(sp); \
- lw $13, PT_R13(sp); \
- lw $12, PT_R12(sp); \
- lw $11, PT_R11(sp); \
- lw $10, PT_R10(sp); \
- lw $9, PT_R9(sp); \
- lw $8, PT_R8(sp); \
lw $7, PT_R7(sp); \
lw $6, PT_R6(sp); \
lw $5, PT_R5(sp); \
lw $4, PT_R4(sp); \
lw $3, PT_R3(sp); \
- lw $2, PT_R2(sp); \
- lw $1, PT_R1(sp); \
- lw sp, PT_R29(sp);
+ lw $2, PT_R2(sp)
+
+#define RESTORE_ALL \
+ RESTORE_SOME; \
+ RESTORE_AT; \
+ RESTORE_TEMP; \
+ RESTORE_STATIC; \
+ RESTORE_SP
/*
* Move to kernel mode and disable interrupts.
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 854c95257..91202c955 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -1207,7 +1207,8 @@ register long __err __asm__ ("$7"); \
__asm__ volatile ("li\t$2,%2\n\t" \
"syscall" \
: "=r" (__res), "=r" (__err) \
- : "i" (__NR_##name)); \
+ : "i" (__NR_##name) \
+ : "$8","$9","$10","$11","$12","$13","$14","$15","$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1228,7 +1229,7 @@ __asm__ volatile ("move\t$4,%3\n\t" \
"syscall" \
: "=r" (__res), "=r" (__err) \
: "i" (__NR_##name),"r" ((long)(a)) \
- : "$4"); \
+ : "$4","$8","$9","$10","$11","$12","$13","$14","$15","$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1247,7 +1248,8 @@ __asm__ volatile ("move\t$4,%3\n\t" \
: "=r" (__res), "=r" (__err) \
: "i" (__NR_##name),"r" ((long)(a)), \
"r" ((long)(b)) \
- : "$4","$5"); \
+ : "$4","$5","$8","$9","$10","$11","$12","$13","$14","$15", \
+ "$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1268,7 +1270,8 @@ __asm__ volatile ("move\t$4,%3\n\t" \
: "i" (__NR_##name),"r" ((long)(a)), \
"r" ((long)(b)), \
"r" ((long)(c)) \
- : "$4","$5","$6"); \
+ : "$4","$5","$6","$8","$9","$10","$11","$12","$13","$14", \
+ "$15","$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1291,7 +1294,8 @@ __asm__ volatile ("move\t$4,%3\n\t" \
"r" ((long)(b)), \
"r" ((long)(c)), \
"r" ((long)(d)) \
- : "$4","$5","$6"); \
+ : "$4","$5","$6""$8","$9","$10","$11","$12","$13","$14", \
+ "$15","$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1319,7 +1323,8 @@ __asm__ volatile ("move\t$4,%3\n\t" \
"r" ((long)(c)), \
"r" ((long)(d)), \
"m" ((long)(e)) \
- : "$2","$4","$5","$6","$7"); \
+ : "$2","$4","$5","$6","$7","$8","$9","$10","$11","$12", \
+ "$13","$14","$15","$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1350,7 +1355,8 @@ __asm__ volatile ("move\t$4,%3\n\t" \
"r" ((long)(d)), \
"m" ((long)(e)), \
"m" ((long)(f)) \
- : "$2","$3","$4","$5","$6","$7"); \
+ : "$2","$3","$4","$5","$6","$7","$8","$9","$10","$11", \
+ "$12","$13","$14","$15","$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1384,7 +1390,8 @@ __asm__ volatile ("move\t$4,%3\n\t" \
"m" ((long)(e)), \
"m" ((long)(f)), \
"m" ((long)(g)) \
- : "$2","$3","$4","$5","$6","$7"); \
+ : "$2","$3","$4","$5","$6","$7","$8","$9","$10","$11", \
+ "$12","$13","$14","$15","$24"); \
if (__err == 0) \
return (type) __res; \
errno = __res; \
@@ -1440,11 +1447,11 @@ static inline pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long f
__asm__ __volatile__(
".set\tnoreorder\n\t"
- "move\t$8,$sp\n\t"
+ "move\t$6,$sp\n\t"
"move\t$4,%5\n\t"
"li\t$2,%1\n\t"
"syscall\n\t"
- "beq\t$8,$sp,1f\n\t"
+ "beq\t$6,$sp,1f\n\t"
"subu\t$sp,32\n\t" /* delay slot */
"jalr\t%4\n\t"
"move\t$4,%3\n\t" /* delay slot */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 08:05:18 +0000