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path: root/arch/mips64/sgi-ip27/ip27-init.c
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* Name change: the generic call flush_cache_all() does not do anythingKanoj Sarcar2000-07-241-2/+2
* Introduce a new cpu specific routine to flush the L2 cache. This helpsKanoj Sarcar2000-07-241-0/+2
* Include config.h.Ralf Baechle2000-07-121-0/+1
* Kill warnings in the 64-bit kernel.Ralf Baechle2000-07-091-19/+20
* Tlb miss handling updates: need to fill in the processor id only onceKanoj Sarcar2000-06-291-0/+1
* Fix a possible race in the initialization code.Kanoj Sarcar2000-06-131-8/+5
* Support to put the lowlevel exception handlers in node local memory.Kanoj Sarcar2000-06-131-0/+25
* Add in the hooks to do kernel text replication. Now start debugging thisKanoj Sarcar2000-06-091-0/+3
* Need to have the nasid of the boot/master node for future uses.Kanoj Sarcar2000-06-091-0/+2
* SMP Mapped kernel fixes to go along with the new layout. Use properlyKanoj Sarcar2000-06-081-1/+1
* Get the mapped kernel working for SMP kernels. While launching slaves,Kanoj Sarcar2000-06-061-3/+4
* Launch the CPUs one by one until we can make sure that weUlf Carlsson2000-06-061-7/+11
* The master processor now waits for all enabled cpus to come into theKanoj Sarcar2000-06-021-1/+1
* Most of the kernel arrays/data structures and low level proceduresKanoj Sarcar2000-06-021-21/+18
* Set smp_num_cpus in the IP27 specific code. Getting ready to handleKanoj Sarcar2000-06-021-1/+1
* Parallel initialization: each hub now tries to discover the xbowKanoj Sarcar2000-05-201-1/+3
* Modify the SMP bootup sequence slightly, so that the master waitsKanoj Sarcar2000-05-171-5/+7
* Rudimentary nmi support to be able to do simple debugging on SMPKanoj Sarcar2000-05-121-0/+3
* SMP bootup and slave processor wakeup needs to be improved, but forKanoj Sarcar2000-05-031-1/+1
* Initialize the slave cpu tlb registers during bootup.Kanoj Sarcar2000-04-261-0/+2
* Enalbe interrupts on slave cpus.Kanoj Sarcar2000-04-261-0/+1
* Pick a name for the idle process on each cpu - easier for debugging.Kanoj Sarcar2000-04-241-0/+1
* First cut at intercpu tlb flushing.Kanoj Sarcar2000-04-221-1/+1
* Per cpu tlbpid (asid) management for SMP. The asid cache is now perKanoj Sarcar2000-04-221-0/+2
* More intercpu interrupt work: we now have a low level inter cpu intrKanoj Sarcar2000-04-171-1/+3
* Moved set_cp0_status(SRB_DEV0 | SRB_DEV1, SRB_DEV0 | SRB_DEV1)Leo Dagum2000-04-101-1/+1
* New code to install and enable interrupt handlers for intercpu intrs.Kanoj Sarcar2000-04-081-8/+5
* Fix this UP/MP microoptimization business with cpu_data[] andKanoj Sarcar2000-04-081-2/+0
* Last tweak before enabling intrs on slave cpus ... set their intr maskKanoj Sarcar2000-04-071-0/+2
* Clear the TS bit from the master's status register (don't know whyKanoj Sarcar2000-04-071-2/+15
* Initial attempt at seperating out per-cpu and per-hub code that needs toKanoj Sarcar2000-04-071-9/+56
* Create idle threads for the slave processors and put them in theirKanoj Sarcar2000-04-061-11/+77
* Fix UP compiles.Kanoj Sarcar2000-04-051-0/+7
* Try to launch all the slave cpus in the system. Currently, I _think_Kanoj Sarcar2000-04-051-1/+18
* Record nasid/cnode/cpuslice in the per cpu data structure during boot up.Kanoj Sarcar2000-04-041-0/+32
* Added a few klconfig functions from IRIX. This triggered some house cleaning,Kanoj Sarcar2000-04-041-56/+7
* Rudimentary code to launch slave processors by the master processor.Kanoj Sarcar2000-04-041-1/+123
* Merge with Linux 2.3.49.Ralf Baechle2000-03-071-1/+0
* Reduce calias protection to access remote node memory completely.Kanoj Sarcar2000-02-051-2/+2
* Steal Irix procedures to set up multiple nodes.Kanoj Sarcar2000-02-041-0/+228
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