summaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel/r6000_fpu.S
blob: 851b4dc4887ac054c532119a5b1b91e392324bed (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
/*
 * r6000_fpu.S: Save/restore floating point context for signal handlers.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996 by Ralf Baechle
 *
 * Multi-arch abstraction and asm macros for easier reading:
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 *
 * $Id: r6000_fpu.S,v 1.5 1999/05/01 22:40:37 ralf Exp $
 */
#include <asm/asm.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/offset.h>
#include <asm/regdef.h>

	.set	noreorder
	.set	mips2
	/* Save floating point context */
	LEAF(save_fp_context)
	mfc0	t0,CP0_STATUS
	sll	t0,t0,2
	bgez	t0,1f
	 nop

	cfc1	t1,fcr31
	/* Store the 16 double precision registers */
	sdc1	$f0,(SC_FPREGS+0)(a0)
	sdc1	$f2,(SC_FPREGS+16)(a0)
	sdc1	$f4,(SC_FPREGS+32)(a0)
	sdc1	$f6,(SC_FPREGS+48)(a0)
	sdc1	$f8,(SC_FPREGS+64)(a0)
	sdc1	$f10,(SC_FPREGS+80)(a0)
	sdc1	$f12,(SC_FPREGS+96)(a0)
	sdc1	$f14,(SC_FPREGS+112)(a0)
	sdc1	$f16,(SC_FPREGS+128)(a0)
	sdc1	$f18,(SC_FPREGS+144)(a0)
	sdc1	$f20,(SC_FPREGS+160)(a0)
	sdc1	$f22,(SC_FPREGS+176)(a0)
	sdc1	$f24,(SC_FPREGS+192)(a0)
	sdc1	$f26,(SC_FPREGS+208)(a0)
	sdc1	$f28,(SC_FPREGS+224)(a0)
	sdc1	$f30,(SC_FPREGS+240)(a0)
	jr	ra
	 sw	t0,SC_FPC_CSR(a0)
1:	jr	ra
	 nop
	END(save_fp_context)

/* Restore FPU state:
 *  - fp gp registers
 *  - cp1 status/control register
 *
 * We base the decision which registers to restore from the signal stack
 * frame on the current content of c0_status, not on the content of the
 * stack frame which might have been changed by the user.
 */
	LEAF(restore_fp_context)
	mfc0	t0,CP0_STATUS
	sll	t0,t0,2

	bgez	t0,1f
	 lw	t0,SC_FPC_CSR(a0)
	/* Restore the 16 double precision registers */
	ldc1	$f0,(SC_FPREGS+0)(a0)
	ldc1	$f2,(SC_FPREGS+16)(a0)
	ldc1	$f4,(SC_FPREGS+32)(a0)
	ldc1	$f6,(SC_FPREGS+48)(a0)
	ldc1	$f8,(SC_FPREGS+64)(a0)
	ldc1	$f10,(SC_FPREGS+80)(a0)
	ldc1	$f12,(SC_FPREGS+96)(a0)
	ldc1	$f14,(SC_FPREGS+112)(a0)
	ldc1	$f16,(SC_FPREGS+128)(a0)
	ldc1	$f18,(SC_FPREGS+144)(a0)
	ldc1	$f20,(SC_FPREGS+160)(a0)
	ldc1	$f22,(SC_FPREGS+176)(a0)
	ldc1	$f24,(SC_FPREGS+192)(a0)
	ldc1	$f26,(SC_FPREGS+208)(a0)
	ldc1	$f28,(SC_FPREGS+224)(a0)
	ldc1	$f30,(SC_FPREGS+240)(a0)
	jr	ra
	 ctc1	t0,fcr31
1:	jr	ra
	 nop
	END(restore_fp_context)