blob: c0653eb645939df07851ba52e29f1c0fd7e395a4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
|
/* $Id: andes.c,v 1.5 1998/05/04 09:12:55 ralf Exp $
*
* andes.c: MMU and cache operations for the R10000 (ANDES).
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/sgialib.h>
#include <asm/mmu_context.h>
extern unsigned long mips_tlb_entries;
/* Cache operations. XXX Write these dave... */
static inline void andes_flush_cache_all(void)
{
/* XXX */
}
static void andes_flush_cache_mm(struct mm_struct *mm)
{
/* XXX */
}
static void andes_flush_cache_range(struct mm_struct *mm,
unsigned long start,
unsigned long end)
{
/* XXX */
}
static void andes_flush_cache_page(struct vm_area_struct *vma,
unsigned long page)
{
/* XXX */
}
static void andes_flush_page_to_ram(unsigned long page)
{
/* XXX */
}
static void andes_flush_cache_sigtramp(unsigned long page)
{
/* XXX */
}
/* TLB operations. XXX Write these dave... */
static inline void andes_flush_tlb_all(void)
{
/* XXX */
}
static void andes_flush_tlb_mm(struct mm_struct *mm)
{
/* XXX */
}
static void andes_flush_tlb_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
/* XXX */
}
static void andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
/* XXX */
}
static void andes_load_pgd(unsigned long pg_dir)
{
}
static void andes_pgd_init(unsigned long page)
{
}
static void andes_add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
{
/* XXX */
}
static int andes_user_mode(struct pt_regs *regs)
{
return (regs->cp0_status & ST0_KSU) == KSU_USER;
}
__initfunc(void ld_mmu_andes(void))
{
flush_cache_all = andes_flush_cache_all;
flush_cache_mm = andes_flush_cache_mm;
flush_cache_range = andes_flush_cache_range;
flush_cache_page = andes_flush_cache_page;
flush_cache_sigtramp = andes_flush_cache_sigtramp;
flush_page_to_ram = andes_flush_page_to_ram;
flush_tlb_all = andes_flush_tlb_all;
flush_tlb_mm = andes_flush_tlb_mm;
flush_tlb_range = andes_flush_tlb_range;
flush_tlb_page = andes_flush_tlb_page;
andes_asid_setup();
add_wired_entry = andes_add_wired_entry;
user_mode = andes_user_mode;
load_pgd = andes_load_pgd;
pgd_init = andes_pgd_init;
flush_cache_all();
flush_tlb_all();
}
|
