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/* $Id: r6000.c,v 1.9 2000/01/27 01:05:23 ralf Exp $
*
* r6000.c: MMU and cache routines for the R6000 processors.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/sgialib.h>
#include <asm/mmu_context.h>
__asm__(".set mips2"); /* because we know... */
/* page functions */
void r6000_clear_page(void * page)
{
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n\t"
"addiu\t$1,%0,%2\n"
"1:\tsw\t$0,(%0)\n\t"
"sw\t$0,4(%0)\n\t"
"sw\t$0,8(%0)\n\t"
"sw\t$0,12(%0)\n\t"
"addiu\t%0,32\n\t"
"sw\t$0,-16(%0)\n\t"
"sw\t$0,-12(%0)\n\t"
"sw\t$0,-8(%0)\n\t"
"bne\t$1,%0,1b\n\t"
"sw\t$0,-4(%0)\n\t"
".set\tat\n\t"
".set\treorder"
:"=r" (page)
:"0" (page),
"I" (PAGE_SIZE)
:"$1","memory");
}
static void r6000_copy_page(void * to, void * from)
{
unsigned long dummy1, dummy2;
unsigned long reg1, reg2, reg3, reg4;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n\t"
"addiu\t$1,%0,%8\n"
"1:\tlw\t%2,(%1)\n\t"
"lw\t%3,4(%1)\n\t"
"lw\t%4,8(%1)\n\t"
"lw\t%5,12(%1)\n\t"
"sw\t%2,(%0)\n\t"
"sw\t%3,4(%0)\n\t"
"sw\t%4,8(%0)\n\t"
"sw\t%5,12(%0)\n\t"
"lw\t%2,16(%1)\n\t"
"lw\t%3,20(%1)\n\t"
"lw\t%4,24(%1)\n\t"
"lw\t%5,28(%1)\n\t"
"sw\t%2,16(%0)\n\t"
"sw\t%3,20(%0)\n\t"
"sw\t%4,24(%0)\n\t"
"sw\t%5,28(%0)\n\t"
"addiu\t%0,64\n\t"
"addiu\t%1,64\n\t"
"lw\t%2,-32(%1)\n\t"
"lw\t%3,-28(%1)\n\t"
"lw\t%4,-24(%1)\n\t"
"lw\t%5,-20(%1)\n\t"
"sw\t%2,-32(%0)\n\t"
"sw\t%3,-28(%0)\n\t"
"sw\t%4,-24(%0)\n\t"
"sw\t%5,-20(%0)\n\t"
"lw\t%2,-16(%1)\n\t"
"lw\t%3,-12(%1)\n\t"
"lw\t%4,-8(%1)\n\t"
"lw\t%5,-4(%1)\n\t"
"sw\t%2,-16(%0)\n\t"
"sw\t%3,-12(%0)\n\t"
"sw\t%4,-8(%0)\n\t"
"bne\t$1,%0,1b\n\t"
"sw\t%5,-4(%0)\n\t"
".set\tat\n\t"
".set\treorder"
:"=r" (dummy1), "=r" (dummy2),
"=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
:"0" (to), "1" (from),
"I" (PAGE_SIZE));
}
/* Cache operations. XXX Write these dave... */
static inline void r6000_flush_cache_all(void)
{
/* XXX */
}
static void r6000_flush_cache_mm(struct mm_struct *mm)
{
/* XXX */
}
static void r6000_flush_cache_range(struct mm_struct *mm,
unsigned long start,
unsigned long end)
{
/* XXX */
}
static void r6000_flush_cache_page(struct vm_area_struct *vma,
unsigned long page)
{
/* XXX */
}
static void r6000_flush_page_to_ram(struct page * page)
{
/* XXX */
}
static void r6000_flush_cache_sigtramp(unsigned long page)
{
/* XXX */
}
/* TLB operations. XXX Write these dave... */
void flush_tlb_all(void)
{
/* XXX */
}
void flush_tlb_mm(struct mm_struct *mm)
{
/* XXX */
}
void flush_tlb_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
/* XXX */
}
void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
/* XXX */
}
void load_pgd(unsigned long pg_dir)
{
}
void pgd_init(unsigned long page)
{
unsigned long dummy1, dummy2;
/*
* The plain and boring version for the R3000. No cache flushing
* stuff is implemented since the R3000 has physical caches.
*/
__asm__ __volatile__(
".set\tnoreorder\n"
"1:\tsw\t%2,(%0)\n\t"
"sw\t%2,4(%0)\n\t"
"sw\t%2,8(%0)\n\t"
"sw\t%2,12(%0)\n\t"
"sw\t%2,16(%0)\n\t"
"sw\t%2,20(%0)\n\t"
"sw\t%2,24(%0)\n\t"
"sw\t%2,28(%0)\n\t"
"subu\t%1,1\n\t"
"bnez\t%1,1b\n\t"
"addiu\t%0,32\n\t"
".set\treorder"
:"=r" (dummy1),
"=r" (dummy2)
:"r" ((unsigned long) invalid_pte_table),
"0" (page),
"1" (PAGE_SIZE/(sizeof(pmd_t)*8)));
}
void update_mmu_cache(struct vm_area_struct * vma,
unsigned long address, pte_t pte)
{
r6000_flush_tlb_page(vma, address);
/*
* FIXME: We should also reload a new entry into the TLB to
* avoid unnecessary exceptions.
*/
}
void show_regs(struct pt_regs * regs)
{
/*
* Saved main processor registers
*/
printk("$0 : %08x %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
0, (unsigned long) regs->regs[1], (unsigned long) regs->regs[2],
(unsigned long) regs->regs[3], (unsigned long) regs->regs[4],
(unsigned long) regs->regs[5], (unsigned long) regs->regs[6],
(unsigned long) regs->regs[7]);
printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
(unsigned long) regs->regs[8], (unsigned long) regs->regs[9],
(unsigned long) regs->regs[10], (unsigned long) regs->regs[11],
(unsigned long) regs->regs[12], (unsigned long) regs->regs[13],
(unsigned long) regs->regs[14], (unsigned long) regs->regs[15]);
printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
(unsigned long) regs->regs[16], (unsigned long) regs->regs[17],
(unsigned long) regs->regs[18], (unsigned long) regs->regs[19],
(unsigned long) regs->regs[20], (unsigned long) regs->regs[21],
(unsigned long) regs->regs[22], (unsigned long) regs->regs[23]);
printk("$24: %08lx %08lx %08lx %08lx %08lx %08lx\n",
(unsigned long) regs->regs[24], (unsigned long) regs->regs[25],
(unsigned long) regs->regs[28], (unsigned long) regs->regs[29],
(unsigned long) regs->regs[30], (unsigned long) regs->regs[31]);
/*
* Saved cp0 registers
*/
printk("epc : %08lx\nStatus: %08x\nCause : %08x\n",
(unsigned long) regs->cp0_epc, (unsigned int) regs->cp0_status,
(unsigned int) regs->cp0_cause);
}
void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
{
/* XXX */
}
void __init ld_mmu_r6000(void)
{
clear_page = r6000_clear_page;
copy_page = r6000_copy_page;
flush_cache_all = r6000_flush_cache_all;
flush_cache_mm = r6000_flush_cache_mm;
flush_cache_range = r6000_flush_cache_range;
flush_cache_page = r6000_flush_cache_page;
flush_cache_sigtramp = r6000_flush_cache_sigtramp;
flush_page_to_ram = r6000_flush_page_to_ram;
flush_cache_all();
flush_tlb_all();
}
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