1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
/* $Id: watch.S,v 1.1 1999/08/21 21:43:01 ralf Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Kernel debug stuff to use the Watch registers.
* Useful to find stack overflows, dangling pointers etc.
*
* Copyright (C) 1995, 1996, 1999 by Ralf Baechle
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
.set noreorder
/*
* Parameter: a0 - logic address to watch
* Currently only KSEG0 addresses are allowed!
* a1 - set bit #1 to trap on load references
* bit #0 to trap on store references
* Results : none
*/
LEAF(__watch_set)
li t0,0x80000000
subu a0,t0
ori a0,7
xori a0,7
or a0,a1
mtc0 a0,CP0_WATCHLO
sw a0,watch_savelo
jr ra
mtc0 zero,CP0_WATCHHI
END(__watch_set)
/*
* Parameter: none
* Results : none
*/
LEAF(__watch_clear)
jr ra
mtc0 zero,CP0_WATCHLO
END(__watch_clear)
/*
* Parameter: none
* Results : none
*/
LEAF(__watch_reenable)
lw t0,watch_savelo
jr ra
mtc0 t0,CP0_WATCHLO
END(__watch_reenable)
/*
* Saved value of the c0_watchlo register for watch_reenable()
*/
.data
watch_savelo: .word 0
.text
|
