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/*
* $Id: dmascc.h,v 1.0
*
* Driver for high-speed SCC boards (those with DMA support)
*
* These are #define, type declarations and prototypes.
*
* Cleaned up on 03/11/2000 Jens David, <dg1kjd@afthd.tu-darmstadt.de>
*
* Copyright (C) 1997 Klaus Kudielka
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* ------------------------------------------------------------------------ */
/* Number of buffers per channel */
#define NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (2 recommended) */
#define NUM_RX_BUF 2 /* NUM_RX_BUF >= 1 (2 recommended) */
#define BUF_SIZE 2016
/* Cards supported */
#define HW_PI { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
0, 8, 1843200, 3686400 }
#define HW_PI2 { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
0, 8, 3686400, 7372800 }
#define HW_TWIN { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
0, 4, 6144000, 6144000 }
#define HARDWARE { HW_PI, HW_PI2, HW_TWIN }
#define TYPE_PI 0
#define TYPE_PI2 1
#define TYPE_TWIN 2
#define NUM_TYPES 3
#define MAX_NUM_DEVS 32
/* SCC chips supported */
#define Z8530 0
#define Z85C30 1
#define Z85230 2
#define CHIPNAMES { "Z8530", "Z85C30", "Z85230" }
/* I/O registers */
/* 8530 registers relative to card base */
#define SCCB_CMD 0x00
#define SCCB_DATA 0x01
#define SCCA_CMD 0x02
#define SCCA_DATA 0x03
/* 8253/8254 registers relative to card base */
#define TMR_CNT0 0x00
#define TMR_CNT1 0x01
#define TMR_CNT2 0x02
#define TMR_CTRL 0x03
/* Additional PI/PI2 registers relative to card base */
#define PI_DREQ_MASK 0x04
/* Additional PackeTwin registers relative to card base */
#define TWIN_INT_REG 0x08
#define TWIN_CLR_TMR1 0x09
#define TWIN_CLR_TMR2 0x0a
#define TWIN_SPARE_1 0x0b
#define TWIN_DMA_CFG 0x08
#define TWIN_SERIAL_CFG 0x09
#define TWIN_DMA_CLR_FF 0x0a
#define TWIN_SPARE_2 0x0b
/* PackeTwin I/O register values */
/* INT_REG */
#define TWIN_SCC_MSK 0x01
#define TWIN_TMR1_MSK 0x02
#define TWIN_TMR2_MSK 0x04
#define TWIN_INT_MSK 0x07
/* SERIAL_CFG */
#define TWIN_DTRA_ON 0x01
#define TWIN_DTRB_ON 0x02
#define TWIN_EXTCLKA 0x04
#define TWIN_EXTCLKB 0x08
#define TWIN_LOOPA_ON 0x10
#define TWIN_LOOPB_ON 0x20
#define TWIN_EI 0x80
/* DMA_CFG */
#define TWIN_DMA_HDX_T1 0x08
#define TWIN_DMA_HDX_R1 0x0a
#define TWIN_DMA_HDX_T3 0x14
#define TWIN_DMA_HDX_R3 0x16
#define TWIN_DMA_FDX_T3R1 0x1b
#define TWIN_DMA_FDX_T1R3 0x1d
/* Status values */
/* tx_state */
#define TX_IDLE 0
#define TX_OFF 1
#define TX_TXDELAY 2
#define TX_ACTIVE 3
#define TX_SQDELAY 4
/* ------------------------------------------------------------------------ */
/* Data types */
struct scc_hardware {
char *name;
int io_region;
int io_delta;
int io_size;
int num_devs;
int scc_offset;
int tmr_offset;
int tmr_hz;
int pclk_hz;
};
struct scc_priv {
struct ax25_dev ax25dev;
struct enet_statistics stats;
struct scc_info *info;
int channel;
int cmd, data, tmr;
struct scc_param param;
char rx_buf[NUM_RX_BUF][BUF_SIZE];
int rx_len[NUM_RX_BUF];
int rx_ptr;
struct tq_struct rx_task;
int rx_head, rx_tail, rx_count;
int rx_over;
char tx_buf[NUM_TX_BUF][BUF_SIZE];
int tx_len[NUM_TX_BUF];
int tx_ptr;
int tx_head, tx_tail, tx_count;
int tx_state;
unsigned long tx_start;
int status;
};
struct scc_info {
int type;
int chip;
int open;
int scc_base;
int tmr_base;
int twin_serial_cfg;
struct net_device dev[2];
struct scc_priv priv[2];
struct scc_info *next;
};
/* ------------------------------------------------------------------------ */
/* Prototypes */
int dmascc_init(void) __init;
static int setup_adapter(int io, int h, int n) __init;
static inline void write_scc(int ctl, int reg, int val);
static inline int read_scc(int ctl, int reg);
static int scc_open(struct net_device *dev);
static int scc_close(struct net_device *dev);
static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
static struct enet_statistics *scc_get_stats(struct net_device *dev);
static int scc_set_mac_address(struct net_device *dev, void *sa);
static void scc_isr(int irq, void *dev_id, struct pt_regs * regs);
static inline void z8530_isr(struct scc_info *info);
static void rx_isr(struct net_device *dev);
static void special_condition(struct net_device *dev, int rc);
static void rx_bh(void *arg);
static void tx_isr(struct net_device *dev);
static void es_isr(struct net_device *dev);
static void tm_isr(struct net_device *dev);
static inline void delay(struct net_device *dev, int t);
static unsigned int report_dcd(struct net_device *dev);
static unsigned int report_ptt(struct net_device *dev);
static void parameter_change_notify(struct net_device *dev, int valueno,
int old, int new);
/* ------------------------------------------------------------------------ */
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