blob: 8eb30d7d89a1cafe3358745bf3ce9212a8190e56 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
/* $Id: timer.h,v 1.2 1998/03/15 17:23:52 ecd Exp $
* timer.h: System timer definitions for sun5.
*
* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
*/
#ifndef _SPARC64_TIMER_H
#define _SPARC64_TIMER_H
/* How timers work:
*
* On uniprocessors we just use counter zero for the system wide
* ticker, this performs thread scheduling, clock book keeping,
* and runs timer based events. Previously we used the Ultra
* %tick interrupt for this purpose.
*
* On multiprocessors we pick one cpu as the master level 10 tick
* processor. Here this counter zero tick handles clock book
* keeping and timer events only. Each Ultra has it's level
* 14 %tick interrupt set to fire off as well, even the master
* tick cpu runs this locally. This ticker performs thread
* scheduling, system/user tick counting for the current thread,
* and also profiling if enabled.
*/
#include <linux/config.h>
/* Two timers, traditionally steered to PIL's 10 and 14 respectively.
* But since INO packets are used on sun5, we could use any PIL level
* we like, however for now we use the normal ones.
*
* The 'reg' and 'interrupts' properties for these live in nodes named
* 'counter-timer'. The first of three 'reg' properties describe where
* the sun5_timer registers are. The other two I have no idea. (XXX)
*/
struct sun5_timer {
u64 count0;
u64 limit0;
u64 count1;
u64 limit1;
};
#define SUN5_LIMIT_ENABLE 0x80000000
#define SUN5_LIMIT_TOZERO 0x40000000
#define SUN5_LIMIT_ZRESTART 0x20000000
#define SUN5_LIMIT_CMASK 0x1fffffff
/* Given a HZ value, set the limit register to so that the timer IRQ
* gets delivered that often.
*/
#define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz))
#ifdef CONFIG_SMP
extern unsigned long timer_tick_offset;
extern void timer_tick_interrupt(struct pt_regs *);
#endif
#endif /* _SPARC64_TIMER_H */
|
