More Atlas chainsawing.

1 files changed, 45 insertions, 50 deletions

diff --git a/arch/mips/mips-boards/generic/mipsIRQ.S b/arch/mips/mips-boards/generic/mipsIRQ.S
index 110f67fad..c2b9d891f 100644
--- a/arch/mips/mips-boards/generic/mipsIRQ.S
+++ b/arch/mips/mips-boards/generic/mipsIRQ.S
@@ -1,9 +1,6 @@
-/* $Id: mipsIRQ.S,v 1.2 2000/08/25 06:53:54 carstenl Exp $
- *
- * mipsIRQ.S
- *
+/*
  * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
  *
  * ########################################################################
  *
@@ -25,51 +22,48 @@
  * Interrupt exception dispatch code.
  *
  */
-
 #include <linux/config.h>
-	
+
 #include <asm/asm.h>
 #include <asm/mipsregs.h>
 #include <asm/regdef.h>
 #include <asm/stackframe.h>
 
-	/* A lot of complication here is taken away because:
-	 *
-	 * 1) We handle one interrupt and return, sitting in a loop
-	 *    and moving across all the pending IRQ bits in the cause
-	 *    register is _NOT_ the answer, the common case is one
-	 *    pending IRQ so optimize in that direction.
-	 *
-	 * 2) We need not check against bits in the status register
-	 *    IRQ mask, that would make this routine slow as hell.
-	 *
-	 * 3) Linux only thinks in terms of all IRQs on or all IRQs
-	 *    off, nothing in between like BSD spl() brain-damage.
-	 *
-	 * Furthermore, the IRQs on the MIPS board look basically (barring
-	 * software IRQs which we don't use at all and all external interrupt
-	 * sources are combined together on hardware interrupt 0 (MIPS 
-	 * IRQ 2)) like:
-	 *
-	 *	MIPS IRQ	Source
-	 *      --------        ------
-	 *             0	Software (ignored)
-	 *             1        Software (ignored)
-	 *             2        Combined hardware interrupt (hw0)
-	 *             3        Hardware (ignored)
-	 *             4        Hardware (ignored)
-	 *             5        Hardware (ignored)
-	 *             6        Hardware (ignored)
-	 *             7        R4k timer (what we use)
-	 *
-	 * We handle the IRQ according to _our_ priority which is:
-	 *
-	 * Highest ----     R4k Timer
-	 * Lowest  ----     Combined hardware interrupt
-	 *
-	 * then we just return, if multiple IRQs are pending then
-	 * we will just take another exception, big deal.
-	 */
+/* A lot of complication here is taken away because:
+ *
+ * 1) We handle one interrupt and return, sitting in a loop and moving across
+ *    all the pending IRQ bits in the cause register is _NOT_ the answer, the
+ *    common case is one pending IRQ so optimize in that direction.
+ *
+ * 2) We need not check against bits in the status register IRQ mask, that
+ *    would make this routine slow as hell.
+ *
+ * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
+ *    between like BSD spl() brain-damage.
+ *
+ * Furthermore, the IRQs on the MIPS board look basically (barring software
+ * IRQs which we don't use at all and all external interrupt sources are
+ * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
+ *
+ *	MIPS IRQ	Source
+ *      --------        ------
+ *             0	Software (ignored)
+ *             1        Software (ignored)
+ *             2        Combined hardware interrupt (hw0)
+ *             3        Hardware (ignored)
+ *             4        Hardware (ignored)
+ *             5        Hardware (ignored)
+ *             6        Hardware (ignored)
+ *             7        R4k timer (what we use)
+ *
+ * We handle the IRQ according to _our_ priority which is:
+ *
+ * Highest ----     R4k Timer
+ * Lowest  ----     Combined hardware interrupt
+ *
+ * then we just return, if multiple IRQs are pending then we will just take
+ * another exception, big deal.
+ */
 
 	.text
 	.set	noreorder
@@ -90,10 +84,10 @@
 	/* Wheee, a timer interrupt. */
 	move	a0, sp
 	jal	mips_timer_interrupt
-	 nop				# delay slot
+	 nop
 
 	j	ret_from_irq
-	 nop				# delay slot
+	 nop
 
 1:
 	beq	a0, zero, 1f
@@ -113,15 +107,16 @@
 	 nop				# delay slot
 
 1:
-	/* Here by mistake?  This is possible, what can happen
-	 * is that by the time we take the exception the IRQ
-	 * pin goes low, so just leave if this is the case.
+	/*
+	 * Here by mistake?  This is possible, what can happen is that by the
+	 * time we take the exception the IRQ pin goes low, so just leave if
+	 * this is the case.
 	 */
 	move	a1,s0
 	PRINT("Got interrupt: c0_cause = %08x\n")
 	mfc0	a1, CP0_EPC
 	PRINT("c0_epc = %08x\n")
-		
+
 	j	ret_from_irq
 	 nop
 	END(mipsIRQ)