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authorKanoj Sarcar <kanoj@engr.sgi.com>2000-04-07 02:14:27 +0000
committerKanoj Sarcar <kanoj@engr.sgi.com>2000-04-07 02:14:27 +0000
commit989cd949d7c7dc6e1d298b46b5f24a2543db419a (patch)
treef771cf6455c3367be92191ac39c0fadb2dd9f9d4 /arch/mips64/kernel
parent8a06a214b483c513c038fed2ae501f351b46b0af (diff)
Clear the TS bit from the master's status register (don't know why
PROM is getting the bit set before entry into kernel). Fix per cpu frequency reporting. Fix bug so that we do not clear information about mips4 availability. Have the slaves flush their cache/tlb and set status based on what the master processor did.
Diffstat (limited to 'arch/mips64/kernel')
-rw-r--r--arch/mips64/kernel/head.S7
-rw-r--r--arch/mips64/kernel/traps.c1
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips64/kernel/head.S b/arch/mips64/kernel/head.S
index 79f409c1b..8b43bb074 100644
--- a/arch/mips64/kernel/head.S
+++ b/arch/mips64/kernel/head.S
@@ -50,7 +50,12 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
CLI # disable interrupts
mfc0 t0, CP0_STATUS
- li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3)
+ /*
+ * On IP27, I am seeing the TS bit set when the
+ * kernel is loaded. Maybe because the kernel is
+ * in ckseg0 and not xkphys? Clear it anyway ...
+ */
+ li t1, ~(ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3)
and t0, t1
or t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR) # Bogosity: cu0 indicates kernel
mtc0 t0, CP0_STATUS # thread in copy_thread.
diff --git a/arch/mips64/kernel/traps.c b/arch/mips64/kernel/traps.c
index 5fe51a31c..0b41f7b9d 100644
--- a/arch/mips64/kernel/traps.c
+++ b/arch/mips64/kernel/traps.c
@@ -446,7 +446,6 @@ static inline void mips4_setup(void)
mips4_available = 1;
set_cp0_status(ST0_XX, ST0_XX);
}
- mips4_available = 0;
}
static inline void go_64(void)