diff options
| author | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-04-07 02:42:40 +0000 |
|---|---|---|
| committer | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-04-07 02:42:40 +0000 |
| commit | fba859f9a0a26b3a0d4c116e161cb8698d666b07 (patch) | |
| tree | 61c083f3dc78935d6c78463c9def7f82ae066213 /arch | |
| parent | 989cd949d7c7dc6e1d298b46b5f24a2543db419a (diff) | |
Last tweak before enabling intrs on slave cpus ... set their intr mask
right.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips64/sgi-ip27/ip27-init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips64/sgi-ip27/ip27-init.c b/arch/mips64/sgi-ip27/ip27-init.c index 40e8fd6be..51e51cd90 100644 --- a/arch/mips64/sgi-ip27/ip27-init.c +++ b/arch/mips64/sgi-ip27/ip27-init.c @@ -19,6 +19,7 @@ #include <asm/processor.h> #include <asm/sn/launch.h> #include <asm/sn/sn_private.h> +#include <asm/sn/sn0/ip27.h> #define CPU_NONE (cpuid_t)-1 @@ -332,6 +333,7 @@ void per_cpu_init(void) if (mips4_available) set_cp0_status(ST0_XX, ST0_XX); set_cp0_status(ST0_KX|ST0_SX|ST0_UX, ST0_KX|ST0_SX|ST0_UX); + set_cp0_status(SRB_DEV0 | SRB_DEV1, SRB_DEV0 | SRB_DEV1); } #if 0 install_cpuintr(cpu); |