diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
| commit | 93f107ba6cceee2c35d207349976936da48393bc (patch) | |
| tree | c33ea3d9e7e92245d6593b694cb514c8db5ff05d /include/asm-mips/cpu.h | |
| parent | f79c44e04169d10b07b53d4a524c8c41ea5504d5 (diff) | |
Add code to support the SB1 core, including mmu routines, processor
detection. This also tweaks cpu_probe() to use bits 15:8 of PRId as
a company ID, as per the mips32/mips64 specs, and use bits 7:0 as the
processor ID within the company. Patch from Justin with mods and some
additional bits by me.
Diffstat (limited to 'include/asm-mips/cpu.h')
| -rw-r--r-- | include/asm-mips/cpu.h | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 0d6db87bc..e5031ee38 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -8,11 +8,32 @@ #define _ASM_CPU_H #include <asm/cache.h> +/* Assigned Company values for bits 23:16 of the PRId Register + (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from + MTI, the PRId register is defined in this (backwards compatible) + way: + + +----------------+----------------+----------------+----------------+ + | Company Options| Company ID | Processor ID | Revision | + +----------------+----------------+----------------+----------------+ + 31 24 23 16 15 8 7 + + I don't have docs for all the previous processors, but my impression is + that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 + spec. +*/ + +#define PRID_COMP_LEGACY 0x000000 +#define PRID_COMP_MIPS 0x010000 +/* + * Don't know who should be here...QED and Sandcraft, maybe? + */ +#define PRID_COMP_SIBYTE 0x040000 /* * Assigned values for the product ID register. In order to detect a * certain CPU type exactly eventually additional registers may need to - * be examined. + * be examined. These are valid when 23:16 == PRID_COMP_LEGACY */ #define PRID_IMP_R2000 0x0100 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ @@ -40,6 +61,17 @@ #define PRID_IMP_UNKNOWN 0xff00 +/* + * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE + */ + +#define PRID_IMP_SB1 0x0100 + +/* + * Definitions for 7:0 on legacy processors + */ + + #define PRID_REV_R4400 0x0040 #define PRID_REV_R3000A 0x0030 #define PRID_REV_R3000 0x0020 |