diff options
| author | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-07-24 22:51:11 +0000 |
|---|---|---|
| committer | Kanoj Sarcar <kanoj@engr.sgi.com> | 2000-07-24 22:51:11 +0000 |
| commit | 5c61649a624af1ba36e12a2dd5a8a5f45b26f898 (patch) | |
| tree | 3c4ce513d0a6b886c5056855c702ffe5ceb67249 /include/asm-mips64/pgtable.h | |
| parent | fa338bfb88ff74c82d0e5d30a5265943c081dc53 (diff) | |
Introduce a new cpu specific routine to flush the L2 cache. This helps
the stability of DISCONTIGMEM kernels. The L2 flushing is needed during
bootup. With this, the initialization hacks of scanning the node memories
at boot up time is not needed any more.
Diffstat (limited to 'include/asm-mips64/pgtable.h')
| -rw-r--r-- | include/asm-mips64/pgtable.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h index b0c97ced1..867e78041 100644 --- a/include/asm-mips64/pgtable.h +++ b/include/asm-mips64/pgtable.h @@ -32,14 +32,12 @@ extern void (*_flush_cache_mm)(struct mm_struct *mm); extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start, unsigned long end); extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); -extern void (*_flush_cache_sigtramp)(unsigned long addr); extern void (*_flush_page_to_ram)(struct page * page); #define flush_cache_all() _flush_cache_all() #define flush_cache_mm(mm) _flush_cache_mm(mm) #define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end) #define flush_cache_page(vma,page) _flush_cache_page(vma, page) -#define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) #define flush_page_to_ram(page) _flush_page_to_ram(page) #define flush_icache_range(start, end) flush_cache_all() @@ -52,6 +50,16 @@ do { \ } while (0) /* + * The foll cache flushing routines are MIPS specific. + * flush_cache_l2 is needed only during initialization. + */ +extern void (*_flush_cache_sigtramp)(unsigned long addr); +extern void (*_flush_cache_l2)(void); + +#define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) +#define flush_cache_l2() _flush_cache_l2() + +/* * Each address space has 2 4K pages as its page directory, giving 1024 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to |