diff options
Diffstat (limited to 'arch/mips/ddb5xxx/ddb5477/int-handler.S')
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5477/int-handler.S | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/int-handler.S b/arch/mips/ddb5xxx/ddb5477/int-handler.S new file mode 100644 index 000000000..4f47a9d1c --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5477/int-handler.S @@ -0,0 +1,93 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * First-level interrupt dispatcher for ddb5477 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/config.h> + +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> + +/* this value should be the same to the one in include/asm/ddb5xxx/ddb5477.h */ +#define DDB_LED 0xbd010000 + +/* + * first level interrupt dispatcher for ocelot board - + * We check for the timer first, then check PCI ints A and D. + * Then check for serial IRQ and fall through. + */ + .align 5 + NESTED(ddb5477_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + .set noreorder + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_cputimer_irq + andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 ) + bnez t1, ll_vrc5477_irq + andi t1, t0, STATUSF_IP0 /* software int 0 */ + bnez t1, ll_cpu_ip0 + andi t1, t0, STATUSF_IP1 /* software int 1 */ + bnez t1, ll_cpu_ip1 + nop + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(ddb5477_handle_int) + + .align 5 + +ll_vrc5477_irq: + move a0, sp + jal vrc5477_irq_dispatch + j ret_from_irq + +ll_cputimer_irq: +#if defined(CONFIG_LL_DEBUG) + /* we trigger software interrupt 0 */ + mfc0 t0, CP0_CAUSE + ori t0, t0, C_SW0 + mtc0 t0, CP0_CAUSE + nop + /* we also set the LED here so when heartbeat stops we know + * intr still happens. */ + la t0, jiffies + lw t1, 0(t0) + srl t1, t1, 4 + andi t1, t1, 0xf + sb t1, DDB_LED +#endif + li a0, 7 + move a1, sp + jal do_IRQ + j ret_from_irq + + +ll_cpu_ip0: + li a0, 0 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip1: + li a0, 1 + move a1, sp + jal do_IRQ + j ret_from_irq |