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-rw-r--r--arch/mips/ddb5xxx/common/Makefile18
-rw-r--r--arch/mips/ddb5xxx/common/irq_cpu.c115
-rw-r--r--arch/mips/ddb5xxx/common/nile4.c135
-rw-r--r--arch/mips/ddb5xxx/common/pci.c179
-rw-r--r--arch/mips/ddb5xxx/common/pci_auto.c396
-rw-r--r--arch/mips/ddb5xxx/common/prom.c58
-rw-r--r--arch/mips/ddb5xxx/common/rtc_ds1386.c267
-rw-r--r--arch/mips/ddb5xxx/ddb5477/Makefile22
-rw-r--r--arch/mips/ddb5xxx/ddb5477/debug.c174
-rw-r--r--arch/mips/ddb5xxx/ddb5477/int-handler.S93
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c193
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c179
-rw-r--r--arch/mips/ddb5xxx/ddb5477/kgdb_io.c142
-rw-r--r--arch/mips/ddb5xxx/ddb5477/pci.c144
-rw-r--r--arch/mips/ddb5xxx/ddb5477/pci_ops.c416
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c251
16 files changed, 2782 insertions, 0 deletions
diff --git a/arch/mips/ddb5xxx/common/Makefile b/arch/mips/ddb5xxx/common/Makefile
new file mode 100644
index 000000000..fc625d7dd
--- /dev/null
+++ b/arch/mips/ddb5xxx/common/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for the common code of NEC DDB-Vrc5xxx board
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+.S.s:
+ $(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+ $(CC) $(CFLAGS) -c $< -o $*.o
+
+O_TARGET:= ddb5xxx.o
+
+obj-y += irq_cpu.o nile4.o prom.o pci.o pci_auto.o rtc_ds1386.o
+
+include $(TOPDIR)/Rules.make
diff --git a/arch/mips/ddb5xxx/common/irq_cpu.c b/arch/mips/ddb5xxx/common/irq_cpu.c
new file mode 100644
index 000000000..7776ef181
--- /dev/null
+++ b/arch/mips/ddb5xxx/common/irq_cpu.c
@@ -0,0 +1,115 @@
+/***********************************************************************
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/common/irq_cpu.c
+ * This file define the irq handler for MIPS CPU interrupts.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ ***********************************************************************
+ */
+
+/*
+ * Almost all MIPS CPUs define 8 interrupt sources. They are typically
+ * level triggered (i.e., cannot be cleared from CPU; must be cleared from
+ * device). The first two are software interrupts. The last one is
+ * usually cpu timer interrupt if coutner register is present.
+ *
+ * This file exports one global function:
+ * mips_cpu_irq_init(u32 irq_base);
+ */
+
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <asm/mipsregs.h>
+
+/* [jsun] sooner or later we should move this debug stuff to MIPS common */
+#include <asm/ddb5xxx/debug.h>
+
+static int mips_cpu_irq_base=-1;
+
+static void
+mips_cpu_irq_enable(unsigned int irq)
+{
+ MIPS_ASSERT(mips_cpu_irq_base != -1);
+ MIPS_ASSERT(irq >= mips_cpu_irq_base);
+ MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+
+ clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
+ set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
+}
+
+static void
+mips_cpu_irq_disable(unsigned int irq)
+{
+ MIPS_ASSERT(mips_cpu_irq_base != -1);
+ MIPS_ASSERT(irq >= mips_cpu_irq_base);
+ MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+
+ clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
+}
+
+static unsigned int mips_cpu_irq_startup(unsigned int irq)
+{
+ mips_cpu_irq_enable(irq);
+ return 0;
+}
+
+#define mips_cpu_irq_shutdown mips_cpu_irq_disable
+
+static void
+mips_cpu_irq_ack(unsigned int irq)
+{
+ MIPS_ASSERT(mips_cpu_irq_base != -1);
+ MIPS_ASSERT(irq >= mips_cpu_irq_base);
+ MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+
+ /* although we attemp to clear the IP bit in cause reigster, I think
+ * usually it is cleared by device (irq source)
+ */
+ clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
+
+ /* I am not fully convinced that I should disable irq here */
+}
+
+static void
+mips_cpu_irq_end(unsigned int irq)
+{
+ MIPS_ASSERT(mips_cpu_irq_base != -1);
+ MIPS_ASSERT(irq >= mips_cpu_irq_base);
+ MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+ /* I am not fully convinced that I should enable irq here */
+}
+
+static hw_irq_controller mips_cpu_irq_controller = {
+ "CPU_irq",
+ mips_cpu_irq_startup,
+ mips_cpu_irq_shutdown,
+ mips_cpu_irq_enable,
+ mips_cpu_irq_disable,
+ mips_cpu_irq_ack,
+ mips_cpu_irq_end,
+ NULL /* no affinity stuff for UP */
+};
+
+
+void
+mips_cpu_irq_init(u32 irq_base)
+{
+ extern irq_desc_t irq_desc[];
+ u32 i;
+
+ for (i= irq_base; i< irq_base+8; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &mips_cpu_irq_controller;
+ }
+
+ mips_cpu_irq_base = irq_base;
+}
diff --git a/arch/mips/ddb5xxx/common/nile4.c b/arch/mips/ddb5xxx/common/nile4.c
new file mode 100644
index 000000000..e8a8d013b
--- /dev/null
+++ b/arch/mips/ddb5xxx/common/nile4.c
@@ -0,0 +1,135 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/common/nile4.c
+ * misc low-level routines for vrc-5xxx controllers.
+ *
+ * derived from original code by Geert Uytterhoeven <geert@sonycom.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+#include <asm/ddb5xxx/debug.h>
+
+u32
+ddb_calc_pdar(u32 phys, u32 size, int width,
+ int on_memory_bus, int pci_visible)
+{
+ u32 maskbits;
+ u32 widthbits;
+
+ switch (size) {
+#if 0 /* We don't support 4 GB yet */
+ case 0x100000000: /* 4 GB */
+ maskbits = 4;
+ break;
+#endif
+ case 0x80000000: /* 2 GB */
+ maskbits = 5;
+ break;
+ case 0x40000000: /* 1 GB */
+ maskbits = 6;
+ break;
+ case 0x20000000: /* 512 MB */
+ maskbits = 7;
+ break;
+ case 0x10000000: /* 256 MB */
+ maskbits = 8;
+ break;
+ case 0x08000000: /* 128 MB */
+ maskbits = 9;
+ break;
+ case 0x04000000: /* 64 MB */
+ maskbits = 10;
+ break;
+ case 0x02000000: /* 32 MB */
+ maskbits = 11;
+ break;
+ case 0x01000000: /* 16 MB */
+ maskbits = 12;
+ break;
+ case 0x00800000: /* 8 MB */
+ maskbits = 13;
+ break;
+ case 0x00400000: /* 4 MB */
+ maskbits = 14;
+ break;
+ case 0x00200000: /* 2 MB */
+ maskbits = 15;
+ break;
+ case 0: /* OFF */
+ maskbits = 0;
+ break;
+ default:
+ panic("nile4_set_pdar: unsupported size %p\n", (void *) size);
+ }
+ switch (width) {
+ case 8:
+ widthbits = 0;
+ break;
+ case 16:
+ widthbits = 1;
+ break;
+ case 32:
+ widthbits = 2;
+ break;
+ case 64:
+ widthbits = 3;
+ break;
+ default:
+ panic("nile4_set_pdar: unsupported width %d\n", width);
+ }
+
+ return maskbits | (on_memory_bus ? 0x10 : 0) |
+ (pci_visible ? 0x20 : 0) | (widthbits << 6) |
+ (phys & 0xffe00000);
+}
+
+void
+ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
+ int on_memory_bus, int pci_visible)
+{
+ u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible);
+ ddb_out32(pdar, temp);
+ ddb_out32(pdar + 4, 0);
+
+ /*
+ * When programming a PDAR, the register should be read immediately
+ * after writing it. This ensures that address decoders are properly
+ * configured.
+ * [jsun] is this really necesary?
+ */
+ ddb_in32(pdar);
+ ddb_in32(pdar + 4);
+}
+
+/*
+ * routines that mess with PCIINITx registers
+ */
+
+void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options)
+{
+ switch (type) {
+ case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */
+ case DDB_PCICMD_IO: /* PCI I/O Space */
+ case DDB_PCICMD_MEM: /* PCI Memory Space */
+ case DDB_PCICMD_CFG: /* PCI Configuration Space */
+ break;
+ default:
+ panic("nile4_set_pmr: invalid type %d\n", type);
+ }
+ ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
+ ddb_out32(pmr + 4, 0);
+}
diff --git a/arch/mips/ddb5xxx/common/pci.c b/arch/mips/ddb5xxx/common/pci.c
new file mode 100644
index 000000000..33cc327d8
--- /dev/null
+++ b/arch/mips/ddb5xxx/common/pci.c
@@ -0,0 +1,179 @@
+/***********************************************************************
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/common/pci.c
+ * Common PCI routines for DDB5xxx - as a matter of fact, meant for all
+ * MIPS machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ ***********************************************************************
+ */
+
+/*
+ * This file contains common PCI routines meant to be shared for
+ * all MIPS machines.
+ *
+ * Strategies:
+ *
+ * . We rely on pci_auto.c file to assign PCI resources (MEM and IO)
+ * TODO: this shold be optional for some machines where they do have
+ * a real "pcibios" that does resource assignment.
+ *
+ * . We then use pci_scan_bus() to "discover" all the resources for
+ * later use by Linux.
+ *
+ * . We finally reply on a board supplied function, pcibios_fixup_irq(), to
+ * to assign the interrupts. We may use setup-irq.c under drivers/pci
+ * later.
+ *
+ * . Specifically, we will *NOT* use pci_assign_unassigned_resources(),
+ * because we assume all PCI devices should have the resources correctly
+ * assigned and recorded.
+ *
+ * Limitations:
+ *
+ * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus
+ * into a contiguous range.
+ *
+ * . In the case of Memory space, the rnage is 1:1 mapping with CPU physical
+ * address space.
+ *
+ * . In the case of IO space, it starts from 0, and the beginning address
+ * is mapped to KSEG0ADDR(mips_io_port) in the CPU physical address.
+ *
+ * . These are the current MIPS limitations (by ioremap, etc). In the
+ * future, we may remove them.
+ *
+ * Credits:
+ * Most of the code are derived from the pci routines from PPC and Alpha,
+ * which were mostly writtne by
+ * Cort Dougan, cort@fsmlabs.com
+ * Matt Porter, mporter@mvista.com
+ * Dave Rusling david.rusling@reo.mts.dec.com
+ * David Mosberger davidm@cs.arizona.edu
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+#include <asm/ddb5xxx/pci.h>
+#include <asm/ddb5xxx/debug.h>
+
+
+struct pci_fixup pcibios_fixups[] = { {0} };
+
+
+extern int pciauto_assign_resources(int busno, struct pci_channel * hose);
+void __init pcibios_init(void)
+{
+ struct pci_channel *p;
+ struct pci_bus *bus;
+ int busno;
+
+ /* assign resources */
+ busno=0;
+ for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
+ busno = pciauto_assign_resources(busno, p) + 1;
+ }
+
+ /* scan the buses */
+ busno = 0;
+ for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
+ bus = pci_scan_bus(busno, p->pci_ops, p);
+ busno = bus->subordinate+1;
+ }
+
+ /* fixup irqs (board specific routines) */
+ pcibios_fixup_irqs();
+
+ /*
+ * should we do a fixup of ioport_resource and iomem_resource
+ * based on mips_pci_channels?
+ * Let us wait and see if this is a common need and whether there
+ * are exceptions. Until then, each board should adjust them
+ * perhaps in their setup() function.
+ */
+}
+
+int pcibios_enable_device(struct pci_dev *dev)
+{
+ /* pciauto_assign_resources() will enable all devices found */
+ return 0;
+}
+
+unsigned long __init
+pci_bridge_check_io(struct pci_dev *bridge)
+{
+ u16 io;
+
+ pci_read_config_word(bridge, PCI_IO_BASE, &io);
+ if (!io) {
+ pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
+ pci_read_config_word(bridge, PCI_IO_BASE, &io);
+ pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
+ }
+ if (io)
+ return IORESOURCE_IO;
+ printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n",
+ bridge->name);
+ return 0;
+}
+
+void __init pcibios_fixup_bus(struct pci_bus *bus)
+{
+ /* Propogate hose info into the subordinate devices. */
+
+ struct pci_channel *hose = bus->sysdata;
+ struct pci_dev *dev = bus->self;
+
+ if (!dev) {
+ /* Root bus */
+ bus->resource[0] = hose->io_resource;
+ bus->resource[1] = hose->mem_resource;
+ } else {
+ /* This is a bridge. Do not care how it's initialized,
+ just link its resources to the bus ones */
+ int i;
+
+ for(i=0; i<3; i++) {
+ bus->resource[i] =
+ &dev->resource[PCI_BRIDGE_RESOURCES+i];
+ bus->resource[i]->name = bus->name;
+ }
+ bus->resource[0]->flags |= pci_bridge_check_io(dev);
+ bus->resource[1]->flags |= IORESOURCE_MEM;
+ /* For now, propogate hose limits to the bus;
+ we'll adjust them later. */
+ bus->resource[0]->end = hose->io_resource->end;
+ bus->resource[1]->end = hose->mem_resource->end;
+ /* Turn off downstream PF memory address range by default */
+ bus->resource[2]->start = 1024*1024;
+ bus->resource[2]->end = bus->resource[2]->start - 1;
+ }
+}
+
+char *pcibios_setup(char *str)
+{
+ return str;
+}
+
+void
+pcibios_align_resource(void *data, struct resource *res, unsigned long size)
+{
+ /* this should not be called */
+ MIPS_ASSERT(1 == 0);
+}
+
+void
+pcibios_update_resource(struct pci_dev *dev, struct resource *root,
+ struct resource *res, int resource)
+{
+ /* this should not be called */
+ MIPS_ASSERT(1 == 0);
+}
diff --git a/arch/mips/ddb5xxx/common/pci_auto.c b/arch/mips/ddb5xxx/common/pci_auto.c
new file mode 100644
index 000000000..b6e751332
--- /dev/null
+++ b/arch/mips/ddb5xxx/common/pci_auto.c
@@ -0,0 +1,396 @@
+/*
+ * arch/ppc/kernel/pci_auto.c
+ *
+ * PCI autoconfiguration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000, 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * Modified for MIPS by Jun Sun, jsun@mvista.com
+ *
+ * . Simplify the interface between pci_auto and the rest: a single function.
+ * . Assign resources from low address to upper address.
+ * . change most int to u32.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+#include <asm/ddb5xxx/pci.h>
+#include <asm/ddb5xxx/debug.h>
+
+#define DEBUG
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+/* These are used for config access before all the PCI probing
+ has been done. */
+int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val);
+int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val);
+int early_read_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 *val);
+int early_write_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 val);
+int early_write_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 val);
+int early_write_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 val);
+
+static u32 pciauto_lower_iospc;
+static u32 pciauto_upper_iospc;
+
+static u32 pciauto_lower_memspc;
+static u32 pciauto_upper_memspc;
+
+void __init
+pciauto_setup_bars(struct pci_channel *hose,
+ int current_bus,
+ int pci_devfn)
+{
+ u32 bar_response, bar_size, bar_value;
+ u32 bar, addr_mask, bar_nr = 0;
+ u32 * upper_limit;
+ u32 * lower_limit;
+ int found_mem64 = 0;
+
+ DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
+ current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
+
+ for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4)
+ {
+ /* Tickle the BAR and get the response */
+ early_write_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ bar,
+ 0xffffffff);
+ early_read_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ bar,
+ &bar_response);
+
+ /* If BAR is not implemented go to the next BAR */
+ if (!bar_response)
+ continue;
+
+ /* Check the BAR type and set our address mask */
+ if (bar_response & PCI_BASE_ADDRESS_SPACE)
+ {
+ addr_mask = PCI_BASE_ADDRESS_IO_MASK;
+ upper_limit = &pciauto_upper_iospc;
+ lower_limit = &pciauto_lower_iospc;
+ DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
+ }
+ else
+ {
+ if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64)
+ found_mem64 = 1;
+
+ addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
+ upper_limit = &pciauto_upper_memspc;
+ lower_limit = &pciauto_lower_memspc;
+ DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
+ }
+
+ /* Calculate requested size */
+ bar_size = ~(bar_response & addr_mask) + 1;
+
+ /* Allocate a base address */
+ bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
+ MIPS_ASSERT(bar_value + bar_size <= *upper_limit);
+
+ /* Write it out and update our limit */
+ early_write_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ bar,
+ bar_value);
+
+ *lower_limit = bar_value + bar_size;
+
+ /*
+ * If we are a 64-bit decoder then increment to the
+ * upper 32 bits of the bar and force it to locate
+ * in the lower 4GB of memory.
+ */
+ if (found_mem64)
+ {
+ bar += 4;
+ early_write_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ bar,
+ 0x00000000);
+ }
+
+ bar_nr++;
+
+ DBG("size=0x%x, address=0x%x\n",
+ bar_size, bar_value);
+ }
+
+}
+
+void __init
+pciauto_prescan_setup_bridge(struct pci_channel *hose,
+ int current_bus,
+ int pci_devfn,
+ int sub_bus)
+{
+ int cmdstat;
+
+ /* Configure bus number registers */
+ early_write_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_PRIMARY_BUS,
+ current_bus);
+ early_write_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_SECONDARY_BUS,
+ sub_bus + 1);
+ early_write_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_SUBORDINATE_BUS,
+ 0xff);
+
+ /* Round memory allocator to 1MB boundary */
+ pciauto_upper_memspc &= ~(0x100000 - 1);
+
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_upper_iospc &= ~(0x1000 - 1);
+
+ /* Set up memory and I/O filter limits, assume 32-bit I/O space */
+ early_write_config_word(hose,
+ current_bus,
+ pci_devfn,
+ PCI_MEMORY_LIMIT,
+ ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
+ early_write_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_IO_LIMIT,
+ ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
+ early_write_config_word(hose,
+ current_bus,
+ pci_devfn,
+ PCI_IO_LIMIT_UPPER16,
+ ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
+
+ /* We don't support prefetchable memory for now, so disable */
+ early_write_config_word(hose,
+ current_bus,
+ pci_devfn,
+ PCI_PREF_MEMORY_BASE,
+ 0x1000);
+ early_write_config_word(hose,
+ current_bus,
+ pci_devfn,
+ PCI_PREF_MEMORY_LIMIT,
+ 0x1000);
+
+ /* Enable memory and I/O accesses, enable bus master */
+ early_read_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ PCI_COMMAND,
+ &cmdstat);
+ early_write_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ PCI_COMMAND,
+ cmdstat |
+ PCI_COMMAND_IO |
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER);
+}
+
+void __init
+pciauto_postscan_setup_bridge(struct pci_channel *hose,
+ int current_bus,
+ int pci_devfn,
+ int sub_bus)
+{
+ /* Configure bus number registers */
+ early_write_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_SUBORDINATE_BUS,
+ sub_bus);
+
+ /* Round memory allocator to 1MB boundary */
+ pciauto_upper_memspc &= ~(0x100000 - 1);
+ early_write_config_word(hose,
+ current_bus,
+ pci_devfn,
+ PCI_MEMORY_BASE,
+ pciauto_upper_memspc >> 16);
+
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_upper_iospc &= ~(0x1000 - 1);
+ early_write_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_IO_BASE,
+ (pciauto_upper_iospc & 0x0000f000) >> 8);
+ early_write_config_word(hose,
+ current_bus,
+ pci_devfn,
+ PCI_IO_BASE_UPPER16,
+ pciauto_upper_iospc >> 16);
+}
+
+#define PCIAUTO_IDE_MODE_MASK 0x05
+
+int __init
+pciauto_bus_scan(struct pci_channel *hose, int current_bus)
+{
+ int sub_bus;
+ u32 pci_devfn, pci_class, cmdstat, found_multi=0;
+ unsigned short vid;
+ unsigned char header_type;
+
+ sub_bus = current_bus;
+
+ for (pci_devfn=0; pci_devfn<0xff; pci_devfn++) {
+
+ if (PCI_FUNC(pci_devfn) && !found_multi)
+ continue;
+
+ early_read_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_HEADER_TYPE,
+ &header_type);
+
+ if (!PCI_FUNC(pci_devfn))
+ found_multi = header_type & 0x80;
+
+ early_read_config_word(hose,
+ current_bus,
+ pci_devfn,
+ PCI_VENDOR_ID,
+ &vid);
+
+ if (vid == 0xffff) continue;
+
+ early_read_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ PCI_CLASS_REVISION, &pci_class);
+ if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
+ DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
+ pciauto_prescan_setup_bridge(hose,
+ current_bus,
+ pci_devfn,
+ sub_bus);
+ sub_bus = pciauto_bus_scan(hose, sub_bus+1);
+ pciauto_postscan_setup_bridge(hose,
+ current_bus,
+ pci_devfn,
+ sub_bus);
+
+ } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
+
+ unsigned char prg_iface;
+
+ early_read_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_CLASS_PROG,
+ &prg_iface);
+ if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
+ DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
+ continue;
+ }
+ }
+
+ /*
+ * Found a peripheral, enable some standard
+ * settings
+ */
+ early_read_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ PCI_COMMAND,
+ &cmdstat);
+ early_write_config_dword(hose,
+ current_bus,
+ pci_devfn,
+ PCI_COMMAND,
+ cmdstat |
+ PCI_COMMAND_IO |
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER);
+ early_write_config_byte(hose,
+ current_bus,
+ pci_devfn,
+ PCI_LATENCY_TIMER,
+ 0x80);
+
+ /* Allocate PCI I/O and/or memory space */
+ pciauto_setup_bars(hose,
+ current_bus,
+ pci_devfn);
+ }
+ return sub_bus;
+}
+
+int __init
+pciauto_assign_resources(int busno, struct pci_channel *hose)
+{
+ /* setup resource limits */
+ pciauto_lower_iospc = hose->io_resource->start;
+ pciauto_upper_iospc = hose->io_resource->end + 1;
+ pciauto_lower_memspc = hose->mem_resource->start;
+ pciauto_upper_memspc = hose->mem_resource->end + 1;
+
+ return pciauto_bus_scan(hose, busno);
+}
+
+
+/*
+ * These functions are used early on before PCI scanning is done
+ * and all of the pci_dev and pci_bus structures have been created.
+ */
+static struct pci_dev *
+fake_pci_dev(struct pci_channel *hose, int busnr, int devfn)
+{
+ static struct pci_dev dev;
+ static struct pci_bus bus;
+
+ dev.bus = &bus;
+ dev.sysdata = hose;
+ dev.devfn = devfn;
+ bus.number = busnr;
+ bus.ops = hose->pci_ops;
+ return &dev;
+}
+
+#define EARLY_PCI_OP(rw, size, type) \
+int early_##rw##_config_##size(struct pci_channel *hose, int bus, \
+ int devfn, int offset, type value) \
+{ \
+ return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
+ offset, value); \
+}
+
+EARLY_PCI_OP(read, byte, u8 *)
+EARLY_PCI_OP(read, word, u16 *)
+EARLY_PCI_OP(read, dword, u32 *)
+EARLY_PCI_OP(write, byte, u8)
+EARLY_PCI_OP(write, word, u16)
+EARLY_PCI_OP(write, dword, u32)
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c
new file mode 100644
index 000000000..9333b5278
--- /dev/null
+++ b/arch/mips/ddb5xxx/common/prom.c
@@ -0,0 +1,58 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/common/prom.c
+ * prom.c file.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+char arcs_cmdline[COMMAND_LINE_SIZE];
+
+/* [jsun@junsun.net] PMON passes arguments in C main() style */
+void __init prom_init(int argc, const char **arg)
+{
+ int i;
+
+ /* arg[0] is "g", the rest is boot parameters */
+ arcs_cmdline[0] = '\0';
+ for (i = 1; i < argc; i++) {
+ if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
+ >= sizeof(arcs_cmdline))
+ break;
+ strcat(arcs_cmdline, arg[i]);
+ strcat(arcs_cmdline, " ");
+ }
+
+ mips_machgroup = MACH_GROUP_NEC_DDB;
+
+#if defined(CONFIG_DDB5074)
+ mips_machtype = MACH_NEC_DDB5074;
+#elif defined(CONFIG_DDB5476)
+ mips_machtype = MACH_NEC_DDB5476;
+#elif defined(CONFIG_DDB5477)
+ mips_machtype = MACH_NEC_DDB5477;
+#endif
+
+ add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
diff --git a/arch/mips/ddb5xxx/common/rtc_ds1386.c b/arch/mips/ddb5xxx/common/rtc_ds1386.c
new file mode 100644
index 000000000..ff1d81c60
--- /dev/null
+++ b/arch/mips/ddb5xxx/common/rtc_ds1386.c
@@ -0,0 +1,267 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/common/rtc_ds1386.c
+ * low-level RTC hookups for s for Dallas 1396 chip.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+
+
+/*
+ * This file exports a function, rtc_ds1386_init(), which expects an
+ * uncached base address as the argument. It will set the two function
+ * pointers expected by the MIPS generic timer code.
+ */
+
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/rtc.h>
+
+#include <asm/time.h>
+#include <asm/addrspace.h>
+
+#include <asm/ddb5xxx/debug.h>
+
+#define EPOCH 2000
+
+#undef BCD_TO_BIN
+#define BCD_TO_BIN(val) (((val)&15) + ((val)>>4)*10)
+
+#undef BIN_TO_BCD
+#define BIN_TO_BCD(val) ((((val)/10)<<4) + (val)%10)
+
+#define READ_RTC(x) *(volatile unsigned char*)(rtc_base+x)
+#define WRITE_RTC(x, y) *(volatile unsigned char*)(rtc_base+x) = y
+
+static unsigned long rtc_base;
+
+static unsigned long
+rtc_ds1386_get_time(void)
+{
+ u8 byte;
+ u8 temp;
+ unsigned int year, month, day, hour, minute, second;
+
+ /* let us freeze external registers */
+ byte = READ_RTC(0xB);
+ byte &= 0x3f;
+ WRITE_RTC(0xB, byte);
+
+ /* read time data */
+ year = BCD_TO_BIN(READ_RTC(0xA)) + EPOCH;
+ month = BCD_TO_BIN(READ_RTC(0x9) & 0x1f);
+ day = BCD_TO_BIN(READ_RTC(0x8));
+ minute = BCD_TO_BIN(READ_RTC(0x2));
+ second = BCD_TO_BIN(READ_RTC(0x1));
+
+ /* hour is special - deal with it later */
+ temp = READ_RTC(0x4);
+
+ /* enable time transfer */
+ byte |= 0x80;
+ WRITE_RTC(0xB, byte);
+
+ /* calc hour */
+ if (temp & 0x40) {
+ /* 12 hour format */
+ hour = BCD_TO_BIN(temp & 0x1f);
+ if (temp & 0x20) hour += 12; /* PM */
+ } else {
+ /* 24 hour format */
+ hour = BCD_TO_BIN(temp & 0x3f);
+ }
+
+ return mktime(year, month, day, hour, minute, second);
+}
+
+void to_tm(unsigned long tim, struct rtc_time * tm);
+static int
+rtc_ds1386_set_time(unsigned long t)
+{
+ struct rtc_time tm;
+ u8 byte;
+ u8 temp;
+ u8 year, month, day, hour, minute, second;
+
+ /* let us freeze external registers */
+ byte = READ_RTC(0xB);
+ byte &= 0x3f;
+ WRITE_RTC(0xB, byte);
+
+ /* convert */
+ to_tm(t, &tm);
+
+ /* check each field one by one */
+ year = BIN_TO_BCD(tm.tm_year - EPOCH);
+ if (year != READ_RTC(0xA)) {
+ WRITE_RTC(0xA, year);
+ }
+
+ temp = READ_RTC(0x9);
+ month = BIN_TO_BCD(tm.tm_mon);
+ if (month != (temp & 0x1f)) {
+ WRITE_RTC( 0x9,
+ (month & 0x1f) | (temp & ~0x1f) );
+ }
+
+ day = BIN_TO_BCD(tm.tm_mday);
+ if (day != READ_RTC(0x8)) {
+ WRITE_RTC(0x8, day);
+ }
+
+ temp = READ_RTC(0x4);
+ if (temp & 0x40) {
+ /* 12 hour format */
+ hour = 0x40;
+ if (tm.tm_hour > 12) {
+ hour |= 0x20 | (BIN_TO_BCD(hour-12) & 0x1f);
+ } else {
+ hour |= BIN_TO_BCD(tm.tm_hour);
+ }
+ } else {
+ /* 24 hour format */
+ hour = BIN_TO_BCD(tm.tm_hour) & 0x3f;
+ }
+ if (hour != temp) WRITE_RTC(0x4, hour);
+
+ minute = BIN_TO_BCD(tm.tm_min);
+ if (minute != READ_RTC(0x2)) {
+ WRITE_RTC(0x2, minute);
+ }
+
+ second = BIN_TO_BCD(tm.tm_sec);
+ if (second != READ_RTC(0x1)) {
+ WRITE_RTC(0x1, second);
+ }
+
+ return 0;
+}
+
+void
+rtc_ds1386_init(unsigned long base)
+{
+ unsigned char byte;
+
+ /* remember the base */
+ rtc_base = base;
+ MIPS_ASSERT((rtc_base & 0xe0000000) == KSEG1);
+
+ /* turn on RTC if it is not on */
+ byte = READ_RTC(0x9);
+ if (byte & 0x80) {
+ byte &= 0x7f;
+ WRITE_RTC(0x9, byte);
+ }
+
+ /* enable time transfer */
+ byte = READ_RTC(0xB);
+ byte |= 0x80;
+ WRITE_RTC(0xB, byte);
+
+ /* set the function pointers */
+ rtc_get_time = rtc_ds1386_get_time;
+ rtc_set_time = rtc_ds1386_set_time;
+}
+
+
+/* ================================================== */
+#define TICK_SIZE tick
+#define FEBRUARY 2
+#define STARTOFTIME 1970
+#define SECDAY 86400L
+#define SECYR (SECDAY * 365)
+#define leapyear(year) ((year) % 4 == 0)
+#define days_in_year(a) (leapyear(a) ? 366 : 365)
+#define days_in_month(a) (month_days[(a) - 1])
+
+static int month_days[12] = {
+ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
+};
+
+/*
+ * This only works for the Gregorian calendar - i.e. after 1752 (in the UK)
+ */
+static void
+GregorianDay(struct rtc_time * tm)
+{
+ int leapsToDate;
+ int lastYear;
+ int day;
+ int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 };
+
+ lastYear=tm->tm_year-1;
+
+ /*
+ * Number of leap corrections to apply up to end of last year
+ */
+ leapsToDate = lastYear/4 - lastYear/100 + lastYear/400;
+
+ /*
+ * This year is a leap year if it is divisible by 4 except when it is
+ * divisible by 100 unless it is divisible by 400
+ *
+ * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be
+ */
+ if((tm->tm_year%4==0) &&
+ ((tm->tm_year%100!=0) || (tm->tm_year%400==0)) &&
+ (tm->tm_mon>2))
+ {
+ /*
+ * We are past Feb. 29 in a leap year
+ */
+ day=1;
+ }
+ else
+ {
+ day=0;
+ }
+
+ day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] +
+ tm->tm_mday;
+
+ tm->tm_wday=day%7;
+}
+
+
+void to_tm(unsigned long tim, struct rtc_time * tm)
+{
+ register int i;
+ register long hms, day;
+
+ day = tim / SECDAY;
+ hms = tim % SECDAY;
+
+ /* Hours, minutes, seconds are easy */
+ tm->tm_hour = hms / 3600;
+ tm->tm_min = (hms % 3600) / 60;
+ tm->tm_sec = (hms % 3600) % 60;
+
+ /* Number of years in days */
+ for (i = STARTOFTIME; day >= days_in_year(i); i++)
+ day -= days_in_year(i);
+ tm->tm_year = i;
+
+ /* Number of months in days left */
+ if (leapyear(tm->tm_year))
+ days_in_month(FEBRUARY) = 29;
+ for (i = 1; day >= days_in_month(i); i++)
+ day -= days_in_month(i);
+ days_in_month(FEBRUARY) = 28;
+ tm->tm_mon = i;
+
+ /* Days are what is left over (+1) from all that. */
+ tm->tm_mday = day + 1;
+
+ /*
+ * Determine the day of week
+ */
+ GregorianDay(tm);
+}
diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile
new file mode 100644
index 000000000..18377fccd
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/Makefile
@@ -0,0 +1,22 @@
+#
+# Makefile for NEC DDB-Vrc5477 board
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+
+.S.s:
+ $(CPP) $(CFLAGS) $< -o $*.s
+.S.o:
+ $(CC) $(CFLAGS) -c $< -o $*.o
+
+O_TARGET:= ddb5477.o
+
+obj-y += int-handler.o irq.o irq_5477.o setup.o pci.o pci_ops.o
+
+obj-$(CONFIG_LL_DEBUG) += debug.o
+obj-$(CONFIG_REMOTE_DEBUG) += kgdb_io.o
+obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o
+
+include $(TOPDIR)/Rules.make
diff --git a/arch/mips/ddb5xxx/ddb5477/debug.c b/arch/mips/ddb5xxx/ddb5477/debug.c
new file mode 100644
index 000000000..a4f820511
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/debug.c
@@ -0,0 +1,174 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/debug.c
+ * vrc5477 specific debug routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/signal.h> /* SA_INTERRUPT */
+
+#include "debug.h"
+#include <asm/mipsregs.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+typedef struct {
+ const char *regname;
+ unsigned regaddr;
+} Register;
+
+void jsun_show_regs(char *name, Register *regs)
+{
+ int i;
+
+ printk("\nshow regs: %s\n", name);
+ for(i=0;regs[i].regname!= NULL; i++) {
+ printk("%-16s= %08x\t\t(@%08x)\n",
+ regs[i].regname,
+ *(unsigned *)(regs[i].regaddr),
+ regs[i].regaddr);
+ }
+}
+
+static Register int_regs[] = {
+ {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
+ {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
+ {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
+ {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
+ {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
+ {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
+ {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
+ {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
+ {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
+ {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
+ {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
+ {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
+ {NULL, 0x0}
+};
+
+void vrc5477_show_int_regs()
+{
+ jsun_show_regs("interrupt registers", int_regs);
+ printk("CPU CAUSE = %08x\n", read_32bit_cp0_register(CP0_CAUSE));
+ printk("CPU STATUS = %08x\n", read_32bit_cp0_register(CP0_STATUS));
+}
+static Register pdar_regs[] = {
+ {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
+ {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
+ {"DDB_LDCS0", DDB_BASE + DDB_LDCS0},
+ {"DDB_LDCS1", DDB_BASE + DDB_LDCS1},
+ {"DDB_LDCS2", DDB_BASE + DDB_LDCS2},
+ {"DDB_INTCS", DDB_BASE + DDB_INTCS},
+ {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
+ {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
+ {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
+ {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
+ {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
+ {NULL, 0x0}
+};
+void vrc5477_show_pdar_regs(void)
+{
+ jsun_show_regs("PDAR regs", pdar_regs);
+}
+
+static Register bar_regs[] = {
+ {"DDB_BARC0", DDB_BASE + DDB_BARC0},
+ {"DDB_BARM010", DDB_BASE + DDB_BARM010},
+ {"DDB_BARM230", DDB_BASE + DDB_BARM230},
+ {"DDB_BAR00", DDB_BASE + DDB_BAR00},
+ {"DDB_BAR10", DDB_BASE + DDB_BAR10},
+ {"DDB_BAR20", DDB_BASE + DDB_BAR20},
+ {"DDB_BAR30", DDB_BASE + DDB_BAR30},
+ {"DDB_BAR40", DDB_BASE + DDB_BAR40},
+ {"DDB_BAR50", DDB_BASE + DDB_BAR50},
+ {"DDB_BARB0", DDB_BASE + DDB_BARB0},
+ {"DDB_BARC1", DDB_BASE + DDB_BARC1},
+ {"DDB_BARM011", DDB_BASE + DDB_BARM011},
+ {"DDB_BARM231", DDB_BASE + DDB_BARM231},
+ {"DDB_BAR01", DDB_BASE + DDB_BAR01},
+ {"DDB_BAR11", DDB_BASE + DDB_BAR11},
+ {"DDB_BAR21", DDB_BASE + DDB_BAR21},
+ {"DDB_BAR31", DDB_BASE + DDB_BAR31},
+ {"DDB_BAR41", DDB_BASE + DDB_BAR41},
+ {"DDB_BAR51", DDB_BASE + DDB_BAR51},
+ {"DDB_BARB1", DDB_BASE + DDB_BARB1},
+ {NULL, 0x0}
+};
+void vrc5477_show_bar_regs(void)
+{
+ jsun_show_regs("BAR regs", bar_regs);
+}
+
+static Register pci_regs[] = {
+ {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
+ {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
+ {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
+ {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
+ {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
+ {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
+ {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
+ {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
+ {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
+ {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
+ {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
+ {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
+ {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
+ {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
+ {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
+ {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
+ {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
+ {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
+ {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
+ {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
+ {NULL, 0x0}
+};
+void vrc5477_show_pci_regs(void)
+{
+ jsun_show_regs("PCI regs", pci_regs);
+}
+
+void vrc5477_show_all_regs(void)
+{
+ vrc5477_show_pdar_regs();
+ vrc5477_show_pci_regs();
+ vrc5477_show_bar_regs();
+ vrc5477_show_int_regs();
+}
+
+/*
+ * We provide heartbeat interrupt handler.
+ * The interrupt comes from soft interrupt 0, which in turn is triggered
+ * cpu timer interrupt. We display the heartbeat to LED.
+ *
+ * If heartbeat runs fine, we know interrupt works and no infinite looping
+ * of interrupt handling (because soft interrupt has the lowest priority).
+ */
+static void heartbeat_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ static int count1=0;
+ static int count2=0;
+
+ if (++count1 == 10) {
+ count1 = 0;
+ count2++;
+ }
+ *(unsigned char*)(DDB_LED + 0xa0000000)= (unsigned char)count2;
+}
+
+struct irqaction heartbeat_irqaction = {
+ heartbeat_interrupt,
+ SA_INTERRUPT,
+ 0,
+ "heartbeat",
+ NULL,
+ NULL};
diff --git a/arch/mips/ddb5xxx/ddb5477/int-handler.S b/arch/mips/ddb5xxx/ddb5477/int-handler.S
new file mode 100644
index 000000000..4f47a9d1c
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/int-handler.S
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * First-level interrupt dispatcher for ddb5477
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/config.h>
+
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+/* this value should be the same to the one in include/asm/ddb5xxx/ddb5477.h */
+#define DDB_LED 0xbd010000
+
+/*
+ * first level interrupt dispatcher for ocelot board -
+ * We check for the timer first, then check PCI ints A and D.
+ * Then check for serial IRQ and fall through.
+ */
+ .align 5
+ NESTED(ddb5477_handle_int, PT_SIZE, sp)
+ SAVE_ALL
+ CLI
+ .set at
+ .set noreorder
+ mfc0 t0, CP0_CAUSE
+ mfc0 t2, CP0_STATUS
+
+ and t0, t2
+
+ andi t1, t0, STATUSF_IP7 /* cpu timer */
+ bnez t1, ll_cputimer_irq
+ andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 )
+ bnez t1, ll_vrc5477_irq
+ andi t1, t0, STATUSF_IP0 /* software int 0 */
+ bnez t1, ll_cpu_ip0
+ andi t1, t0, STATUSF_IP1 /* software int 1 */
+ bnez t1, ll_cpu_ip1
+ nop
+ .set reorder
+
+ /* wrong alarm or masked ... */
+ j spurious_interrupt
+ nop
+ END(ddb5477_handle_int)
+
+ .align 5
+
+ll_vrc5477_irq:
+ move a0, sp
+ jal vrc5477_irq_dispatch
+ j ret_from_irq
+
+ll_cputimer_irq:
+#if defined(CONFIG_LL_DEBUG)
+ /* we trigger software interrupt 0 */
+ mfc0 t0, CP0_CAUSE
+ ori t0, t0, C_SW0
+ mtc0 t0, CP0_CAUSE
+ nop
+ /* we also set the LED here so when heartbeat stops we know
+ * intr still happens. */
+ la t0, jiffies
+ lw t1, 0(t0)
+ srl t1, t1, 4
+ andi t1, t1, 0xf
+ sb t1, DDB_LED
+#endif
+ li a0, 7
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+
+ll_cpu_ip0:
+ li a0, 0
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_cpu_ip1:
+ li a0, 1
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
new file mode 100644
index 000000000..5b4ca0673
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -0,0 +1,193 @@
+/***********************************************************************
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/irq.c
+ * The irq setup and misc routines for DDB5476.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ ***********************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+#include <asm/system.h>
+#include <asm/mipsregs.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+/* [jsun] sooner or later we should move this debug stuff to MIPS common */
+#include <asm/ddb5xxx/debug.h>
+
+/*
+ * IRQ mapping
+ *
+ * 0-7: 8 CPU interrupts
+ * 0 - software interrupt 0
+ * 1 - software interrupt 1
+ * 2 - most Vrc5477 interrupts are routed to this pin
+ * 3 - (optional) some other interrupts routed to this pin for debugg
+ * 4 - not used
+ * 5 - not used
+ * 6 - not used
+ * 7 - cpu timer (used by default)
+ *
+ * 8-39: 32 Vrc5477 interrupt sources
+ * (refer to the Vrc5477 manual)
+ */
+
+#define PCI0 DDB_INTPPES0
+#define PCI1 DDB_INTPPES1
+
+#define ACTIVE_LOW 1
+#define ACTIVE_HIGH 0
+
+#define LEVEL_SENSE 2
+#define EDGE_TRIGGER 0
+
+#define INTA 0
+#define INTB 1
+#define INTC 2
+#define INTD 3
+#define INTE 4
+
+static inline void
+set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+
+ reg_value = ddb_in32(pci);
+ reg_bitmask = 0x3 << (intn * 2);
+
+ reg_value &= ~reg_bitmask;
+ reg_value |= (active | trigger) << (intn * 2);
+ ddb_out32(pci, reg_value);
+}
+
+extern void vrc5477_irq_init(u32 base);
+extern void mips_cpu_irq_init(u32 base);
+extern asmlinkage void ddb5477_handle_int(void);
+
+#if defined(CONFIG_LL_DEBUG)
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+extern struct irqaction heartbeat_irqaction;
+#endif
+
+void
+ddb5477_irq_setup(void)
+{
+ MIPS_DEBUG(printk("ddb5477_irq_setup invoked.\n"));
+
+ /* by default, we disable all interrupts and route all vrc5477
+ * interrupts to pin 0 (irq 2) */
+ ddb_out32(DDB_INTCTRL0, 0);
+ ddb_out32(DDB_INTCTRL1, 0);
+ ddb_out32(DDB_INTCTRL2, 0);
+ ddb_out32(DDB_INTCTRL3, 0);
+
+ clear_cp0_status(0xff00);
+ set_cp0_status(0x0400);
+
+ /* setup PCI interrupt attributes */
+ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
+
+ set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
+ set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
+
+ /*
+ * for debugging purpose, we enable several error interrupts
+ * and route them to pin 1. (IP3)
+ */
+ /* cpu parity check - 0 */
+ ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
+ /* cpu no-target decode - 1 */
+ ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
+ /* local bus read time-out - 7 */
+ ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
+ /* PCI SERR# - 14 */
+ ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
+ /* PCI internal error - 15 */
+ ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
+ /* IOPCI SERR# - 30 */
+ ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
+ /* IOPCI internal error - 31 */
+ ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
+
+ /* init all controllers */
+ mips_cpu_irq_init(0);
+ vrc5477_irq_init(8);
+
+ /* hook up the first-level interrupt handler */
+ set_except_vector(0, ddb5477_handle_int);
+
+#if defined(CONFIG_LL_DEBUG)
+ setup_irq(0, &heartbeat_irqaction);
+#endif
+}
+
+/*
+ * the first level int-handler will jump here if it is a vrc5477 irq
+ */
+#define NUM_5477_IRQS 32
+asmlinkage void
+vrc5477_irq_dispatch(struct pt_regs *regs)
+{
+ extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
+
+ u32 intStatus;
+ u32 bitmask;
+ u32 i;
+
+ MIPS_ASSERT(ddb_in32(DDB_INT2STAT) == 0);
+ MIPS_ASSERT(ddb_in32(DDB_INT3STAT) == 0);
+ MIPS_ASSERT(ddb_in32(DDB_INT4STAT) == 0);
+ MIPS_ASSERT(ddb_in32(DDB_NMISTAT) == 0);
+
+ if (ddb_in32(DDB_INT1STAT) != 0) {
+#if defined(CONFIG_LL_DEBUG)
+ vrc5477_show_int_regs();
+#endif
+ panic("error interrupt has happened.\n");
+ }
+
+ intStatus = ddb_in32(DDB_INT0STAT);
+ for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
+ /* do we need to "and" with the int mask? */
+ if (intStatus & bitmask) {
+ do_IRQ(8 + i, regs);
+ }
+ }
+}
+
+void (*irq_setup)(void);
+
+void __init init_IRQ(void)
+{
+
+#ifdef CONFIG_REMOTE_DEBUG
+ extern void breakpoint(void);
+ extern void set_debug_traps(void);
+
+ printk("Wait for gdb client connection ...\n");
+ set_debug_traps();
+ breakpoint();
+#endif
+
+ /* invoke board-specific irq setup */
+ irq_setup();
+}
+
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
new file mode 100644
index 000000000..95e995743
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -0,0 +1,179 @@
+/***********************************************************************
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/irq_5477.c
+ * This file defines the irq handler for Vrc5477.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ ***********************************************************************
+ */
+
+/*
+ * Vrc5477 defines 32 IRQs.
+ *
+ * This file exports one function:
+ * vrc5477_irq_init(u32 irq_base);
+ */
+
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+/* [jsun] sooner or later we should move this debug stuff to MIPS common */
+#include <asm/ddb5xxx/debug.h>
+
+/* number of total irqs supported by Vrc5477 */
+#define NUM_5477_IRQ 32
+
+static int vrc5477_irq_base=-1;
+
+
+static void
+vrc5477_irq_enable(unsigned int irq)
+{
+ MIPS_ASSERT(vrc5477_irq_base != -1);
+ MIPS_ASSERT(irq >= vrc5477_irq_base);
+ MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+
+ ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
+}
+
+static void
+vrc5477_irq_disable(unsigned int irq)
+{
+ MIPS_ASSERT(vrc5477_irq_base != -1);
+ MIPS_ASSERT(irq >= vrc5477_irq_base);
+ MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
+
+ ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
+}
+
+static unsigned int vrc5477_irq_startup(unsigned int irq)
+{
+ vrc5477_irq_enable(irq);
+ return 0;
+}
+
+#define vrc5477_irq_shutdown vrc5477_irq_disable
+
+static void
+vrc5477_irq_ack(unsigned int irq)
+{
+ MIPS_ASSERT(vrc5477_irq_base != -1);
+ MIPS_ASSERT(irq >= vrc5477_irq_base);
+ MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
+
+ /* clear the interrupt bit */
+ /* some irqs require the driver to clear the sources */
+ ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
+
+ /* disable interrupt - some handler will re-enable the irq
+ * and if the interrupt is leveled, we will have infinite loop
+ */
+ ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
+}
+
+static void
+vrc5477_irq_end(unsigned int irq)
+{
+ MIPS_ASSERT(vrc5477_irq_base != -1);
+ MIPS_ASSERT(irq >= vrc5477_irq_base);
+ MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
+
+ ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
+}
+
+hw_irq_controller vrc5477_irq_controller = {
+ "vrc5477_irq",
+ vrc5477_irq_startup,
+ vrc5477_irq_shutdown,
+ vrc5477_irq_enable,
+ vrc5477_irq_disable,
+ vrc5477_irq_ack,
+ vrc5477_irq_end,
+ NULL /* no affinity stuff for UP */
+};
+
+void
+vrc5477_irq_init(u32 irq_base)
+{
+ extern irq_desc_t irq_desc[];
+ u32 i;
+
+ for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &vrc5477_irq_controller;
+ }
+
+ vrc5477_irq_base = irq_base;
+}
+
+
+int vrc5477_irq_to_irq(int irq)
+{
+ MIPS_ASSERT(irq >= 0);
+ MIPS_ASSERT(irq < NUM_5477_IRQ);
+
+ return irq + vrc5477_irq_base;
+}
+
+void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+ u32 reg_index;
+
+ MIPS_ASSERT(vrc5477_irq >= 0);
+ MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
+ MIPS_ASSERT(ip >= 0);
+ MIPS_ASSERT((ip < 5) || (ip == 6));
+
+ reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
+ reg_value = ddb_in32(reg_index);
+ reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
+ reg_value &= ~reg_bitmask;
+ reg_value |= ip << (vrc5477_irq % 8 * 4);
+ ddb_out32(reg_index, reg_value);
+}
+
+void ll_vrc5477_irq_enable(int vrc5477_irq)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+ u32 reg_index;
+
+ MIPS_ASSERT(vrc5477_irq >= 0);
+ MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
+
+ reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
+ reg_value = ddb_in32(reg_index);
+ reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
+ MIPS_ASSERT((reg_value & reg_bitmask) == 0);
+ ddb_out32(reg_index, reg_value | reg_bitmask);
+}
+
+void ll_vrc5477_irq_disable(int vrc5477_irq)
+{
+ u32 reg_value;
+ u32 reg_bitmask;
+ u32 reg_index;
+
+ MIPS_ASSERT(vrc5477_irq >= 0);
+ MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
+
+ reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
+ reg_value = ddb_in32(reg_index);
+ reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
+
+ /* we assert that the interrupt is enabled (perhaps over-zealous) */
+ MIPS_ASSERT( (reg_value & reg_bitmask) != 0);
+ ddb_out32(reg_index, reg_value & ~reg_bitmask);
+}
diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
new file mode 100644
index 000000000..487d0bddf
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
@@ -0,0 +1,142 @@
+
+#include <linux/config.h>
+
+#if (defined(CONFIG_DDB5477) && defined(CONFIG_REMOTE_DEBUG))
+
+/* --- CONFIG --- */
+
+/* we need uint32 uint8 */
+/* #include "types.h" */
+typedef unsigned char uint8;
+typedef unsigned int uint32;
+
+/* --- END OF CONFIG --- */
+
+#define UART16550_BAUD_2400 2400
+#define UART16550_BAUD_4800 4800
+#define UART16550_BAUD_9600 9600
+#define UART16550_BAUD_19200 19200
+#define UART16550_BAUD_38400 38400
+#define UART16550_BAUD_57600 57600
+#define UART16550_BAUD_115200 115200
+
+#define UART16550_PARITY_NONE 0
+#define UART16550_PARITY_ODD 0x08
+#define UART16550_PARITY_EVEN 0x18
+#define UART16550_PARITY_MARK 0x28
+#define UART16550_PARITY_SPACE 0x38
+
+#define UART16550_DATA_5BIT 0x0
+#define UART16550_DATA_6BIT 0x1
+#define UART16550_DATA_7BIT 0x2
+#define UART16550_DATA_8BIT 0x3
+
+#define UART16550_STOP_1BIT 0x0
+#define UART16550_STOP_2BIT 0x4
+
+/* ----------------------------------------------------- */
+
+/* === CONFIG === */
+
+/* [jsun] we use the second serial port for kdb */
+#define BASE 0xbfa04240
+#define MAX_BAUD 115200
+#define REG_OFFSET 8
+
+/* === END OF CONFIG === */
+
+/* register offset */
+#define OFS_RCV_BUFFER (0*REG_OFFSET)
+#define OFS_TRANS_HOLD (0*REG_OFFSET)
+#define OFS_SEND_BUFFER (0*REG_OFFSET)
+#define OFS_INTR_ENABLE (1*REG_OFFSET)
+#define OFS_INTR_ID (2*REG_OFFSET)
+#define OFS_DATA_FORMAT (3*REG_OFFSET)
+#define OFS_LINE_CONTROL (3*REG_OFFSET)
+#define OFS_MODEM_CONTROL (4*REG_OFFSET)
+#define OFS_RS232_OUTPUT (4*REG_OFFSET)
+#define OFS_LINE_STATUS (5*REG_OFFSET)
+#define OFS_MODEM_STATUS (6*REG_OFFSET)
+#define OFS_RS232_INPUT (6*REG_OFFSET)
+#define OFS_SCRATCH_PAD (7*REG_OFFSET)
+
+#define OFS_DIVISOR_LSB (0*REG_OFFSET)
+#define OFS_DIVISOR_MSB (1*REG_OFFSET)
+
+
+/* memory-mapped read/write of the port */
+#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
+#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
+
+void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+ /* disable interrupts */
+ UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+ /* set up buad rate */
+ {
+ uint32 divisor;
+
+ /* set DIAB bit */
+ UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+ /* set divisor */
+ divisor = MAX_BAUD / baud;
+ UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+ UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+
+ /* clear DIAB bit */
+ UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+ }
+
+ /* set data format */
+ UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+static int remoteDebugInitialized = 0;
+
+int debug_state = -1;
+
+uint8 getDebugChar(void)
+{
+ uint8 c;
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(UART16550_BAUD_38400,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+ }
+
+ while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+ c= UART16550_READ(OFS_RCV_BUFFER);
+/*
+ if (state != 1) {
+ state = 1;
+ debug_out("\ngetDebugChar: ", 15);
+ }
+ debug_out(&c, 1);
+*/
+ return c;
+}
+
+
+int putDebugChar(uint8 byte)
+{
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(UART16550_BAUD_9600,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+ }
+
+ while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
+ UART16550_WRITE(OFS_SEND_BUFFER, byte);
+ if (debug_state != 2) {
+ debug_state = 2;
+ // debug_out("\nputDebugChar: ", 15);
+ }
+ // debug_out(&byte, 1);
+ return 1;
+}
+
+#endif
diff --git a/arch/mips/ddb5xxx/ddb5477/pci.c b/arch/mips/ddb5xxx/ddb5477/pci.c
new file mode 100644
index 000000000..c17413fdd
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/pci.c
@@ -0,0 +1,144 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+#include <asm/ddb5xxx/debug.h>
+#include <asm/ddb5xxx/pci.h>
+
+static struct resource extpci_io_resource = {
+ "ext pci IO space",
+ DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE,
+ DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE -1,
+ IORESOURCE_IO};
+
+static struct resource extpci_mem_resource = {
+ "ext pci memory space",
+ DDB_PCI0_MEM_BASE,
+ DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE -1,
+ IORESOURCE_MEM};
+
+static struct resource iopci_io_resource = {
+ "io pci IO space",
+ DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
+ DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE -1,
+ IORESOURCE_IO};
+
+static struct resource iopci_mem_resource = {
+ "ext pci memory space",
+ DDB_PCI1_MEM_BASE,
+ DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE -1,
+ IORESOURCE_MEM};
+
+extern struct pci_ops ddb5477_ext_pci_ops;
+extern struct pci_ops ddb5477_io_pci_ops;
+
+struct pci_channel mips_pci_channels[] = {
+ { &ddb5477_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource },
+ { &ddb5477_io_pci_ops, &iopci_io_resource, &iopci_mem_resource },
+ { NULL, NULL, NULL}
+};
+
+
+/*
+ * we fix up irqs based on the slot number.
+ * The first entry is at AD:11.
+ * Fortunately this works because, although we have two pci buses,
+ * they all have different slot numbers.
+ *
+ * This does not work for devices on sub-buses.
+ *
+ * Note that the irq number in the array is relative number in vrc5477.
+ * We need to translate it to global irq number.
+ */
+
+/*
+ * irq mapping : PCI int # -> vrc5477 irq #
+ * based on vrc5477 manual page 46
+ */
+#define PCI_EXT_INTA 8
+#define PCI_EXT_INTB 9
+#define PCI_EXT_INTC 10
+#define PCI_EXT_INTD 11
+#define PCI_EXT_INTE 12
+
+#define PCI_IO_INTA 16
+#define PCI_IO_INTB 17
+#define PCI_IO_INTC 18
+#define PCI_IO_INTD 19
+
+/*
+ * irq mapping : device -> pci int #,
+ * ddb5477 board manual page 4 and vrc5477 manual page 46
+ */
+#define INT_ONBOARD_TULIP PCI_EXT_INTA
+#define INT_SLOT1 PCI_EXT_INTB
+#define INT_SLOT2 PCI_EXT_INTC
+#define INT_SLOT3 PCI_EXT_INTD
+#define INT_SLOT4 PCI_EXT_INTE
+
+#define INT_USB_HOST PCI_IO_INTA
+#define INT_USB_PERI PCI_IO_INTB
+#define INT_AC97 PCI_IO_INTC
+
+/*
+ * based on ddb5477 manual page 11
+ */
+#define MAX_SLOT_NUM 21
+static unsigned char irq_map[MAX_SLOT_NUM] = {
+ /* AD:11 */ 0xff, 0xff, 0xff, 0xff,
+ /* AD:15 */ INT_ONBOARD_TULIP, INT_SLOT1, INT_SLOT2, INT_SLOT3,
+ /* AD:19 */ INT_SLOT4, 0xff, 0xff, 0xff,
+ /* AD:23 */ 0xff, 0xff, 0xff, 0xff,
+ /* AD:27 */ 0xff, 0xff, INT_AC97, INT_USB_PERI,
+ /* AD:31 */ INT_USB_HOST
+};
+
+extern int vrc5477_irq_to_irq(int irq);
+void __init pcibios_fixup_irqs(void)
+{
+ struct pci_dev *dev;
+ int slot_num;
+
+ pci_for_each_dev(dev) {
+ slot_num = PCI_SLOT(dev->devfn);
+ MIPS_ASSERT(slot_num < MAX_SLOT_NUM);
+ MIPS_ASSERT(irq_map[slot_num] != 0xff);
+
+ pci_write_config_byte(dev,
+ PCI_INTERRUPT_LINE,
+ irq_map[slot_num]);
+ dev->irq = vrc5477_irq_to_irq(irq_map[slot_num]);
+ }
+}
+
+#if defined(CONFIG_LL_DEBUG)
+extern void jsun_scan_pci_bus(void);
+extern void jsun_assign_pci_resource(void);
+#endif
+void __init ddb_pci_reset_bus(void)
+{
+ u32 temp;
+
+ /*
+ * I am not sure about the "official" procedure, the following
+ * steps work as far as I know:
+ * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
+ * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
+ * The same is true for both PCI channels.
+ */
+ temp = ddb_in32(DDB_PCICTL0_H);
+ temp |= 0x80000000;
+ ddb_out32(DDB_PCICTL0_H, temp);
+ temp &= ~0xc0000000;
+ ddb_out32(DDB_PCICTL0_H, temp);
+
+ temp = ddb_in32(DDB_PCICTL1_H);
+ temp |= 0x80000000;
+ ddb_out32(DDB_PCICTL1_H, temp);
+ temp &= ~0xc0000000;
+ ddb_out32(DDB_PCICTL1_H, temp);
+}
+
+
diff --git a/arch/mips/ddb5xxx/ddb5477/pci_ops.c b/arch/mips/ddb5xxx/ddb5477/pci_ops.c
new file mode 100644
index 000000000..3bd3e2189
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/pci_ops.c
@@ -0,0 +1,416 @@
+/***********************************************************************
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/pci_ops.c
+ * Define the pci_ops for DB5477.
+ *
+ * Much of the code is derived from the original DDB5074 port by
+ * Geert Uytterhoeven <geert@sonycom.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ ***********************************************************************
+ */
+
+/*
+ * DDB5477 has two PCI channels, external PCI and IOPIC (internal)
+ * Therefore we provide two sets of pci_ops.
+ */
+
+#include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+#include <asm/ddb5xxx/debug.h>
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+/*
+ * config_swap structure records what set of pdar/pmr are used
+ * to access pci config space. It also provides a place hold the
+ * original values for future restoring.
+ */
+struct pci_config_swap {
+ u32 pdar;
+ u32 pmr;
+ u32 config_base;
+ u32 config_size;
+ u32 pdar_backup;
+ u32 pmr_backup;
+};
+
+/*
+ * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI.
+ */
+struct pci_config_swap ext_pci_swap = {
+ DDB_PCIW0,
+ DDB_PCIINIT00,
+ DDB_PCI0_CONFIG_BASE,
+ DDB_PCI0_CONFIG_SIZE
+};
+struct pci_config_swap io_pci_swap = {
+ DDB_IOPCIW0,
+ DDB_PCIINIT01,
+ DDB_PCI1_CONFIG_BASE,
+ DDB_PCI1_CONFIG_SIZE
+};
+
+
+/*
+ * access config space
+ */
+static inline u32 ddb_access_config_base(struct pci_config_swap *swap,
+ u32 bus,/* 0 means top level bus */
+ u32 slot_num)
+{
+ u32 pci_addr = 0;
+ u32 pciinit_offset = 0;
+ u32 virt_addr = swap->config_base;
+ u32 option;
+
+ /* [jsun] hack for testing */
+ // if (slot_num == 4) slot_num = 0;
+
+ /* minimum pdar (window) size is 2MB */
+ MIPS_ASSERT(swap->config_size >= (2 << 20));
+
+ MIPS_ASSERT(slot_num < (1 << 5));
+ MIPS_ASSERT(bus < (1 << 8));
+
+ /* backup registers */
+ swap->pdar_backup = ddb_in32(swap->pdar);
+ swap->pmr_backup = ddb_in32(swap->pmr);
+
+ /* set the pdar (pci window) register */
+ ddb_set_pdar(swap->pdar,
+ swap->config_base,
+ swap->config_size,
+ 32, /* 32 bit wide */
+ 0, /* not on local memory bus */
+ 0); /* not visible from PCI bus (N/A) */
+
+ /*
+ * calcuate the absolute pci config addr;
+ * according to the spec, we start scanning from adr:11 (0x800)
+ */
+ if (bus == 0) {
+ /* type 0 config */
+ pci_addr = 0x800 << slot_num;
+ } else {
+ /* type 1 config */
+ pci_addr = (bus << 16) | (slot_num << 11);
+ panic("ddb_access_config_base: we don't support type 1 config Yet");
+ }
+
+ /*
+ * if pci_addr is less than pci config window size, we set
+ * pciinit_offset to 0 and adjust the virt_address.
+ * Otherwise we will try to adjust pciinit_offset.
+ */
+ if (pci_addr < swap->config_size) {
+ virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
+ pciinit_offset = 0;
+ } else {
+ MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0);
+ virt_addr = KSEG1ADDR(swap->config_base);
+ pciinit_offset = pci_addr;
+ }
+
+ /* set the pmr register */
+ option = DDB_PCI_ACCESS_32;
+ if (bus != 0) option |= DDB_PCI_CFGTYPE1;
+ ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
+
+ return virt_addr;
+}
+
+static inline void ddb_close_config_base(struct pci_config_swap *swap)
+{
+ ddb_out32(swap->pdar, swap->pdar_backup);
+ ddb_out32(swap->pmr, swap->pmr_backup);
+}
+
+static int read_config_dword(struct pci_config_swap *swap,
+ struct pci_dev *dev,
+ u32 where,
+ u32 *val)
+{
+ u32 bus, slot_num, func_num;
+ u32 base;
+
+ MIPS_ASSERT((where & 3) == 0);
+ MIPS_ASSERT(where < (1 << 8));
+
+ /* check if the bus is top-level */
+ if (dev->bus->parent != NULL) {
+ bus = dev->bus->number;
+ MIPS_ASSERT(bus != 0);
+ } else {
+ bus = 0;
+ }
+
+ slot_num = PCI_SLOT(dev->devfn);
+ func_num = PCI_FUNC(dev->devfn);
+ base = ddb_access_config_base(swap, bus, slot_num);
+ *val = *(volatile u32*) (base + (func_num << 8) + where);
+ ddb_close_config_base(swap);
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int read_config_word(struct pci_config_swap *swap,
+ struct pci_dev *dev,
+ u32 where,
+ u16 *val)
+{
+ int status;
+ u32 result;
+
+ MIPS_ASSERT((where & 1) == 0);
+
+ status = read_config_dword(swap, dev, where & ~3, &result);
+ if (where & 2) result >>= 16;
+ *val = result & 0xffff;
+ return status;
+}
+
+static int read_config_byte(struct pci_config_swap *swap,
+ struct pci_dev *dev,
+ u32 where,
+ u8 *val)
+{
+ int status;
+ u32 result;
+
+ status = read_config_dword(swap, dev, where & ~3, &result);
+ if (where & 1) result >>= 8;
+ if (where & 2) result >>= 16;
+ *val = result & 0xff;
+ return status;
+}
+
+static int write_config_dword(struct pci_config_swap *swap,
+ struct pci_dev *dev,
+ u32 where,
+ u32 val)
+{
+ u32 bus, slot_num, func_num;
+ u32 base;
+
+ MIPS_ASSERT((where & 3) == 0);
+ MIPS_ASSERT(where < (1 << 8));
+
+ /* check if the bus is top-level */
+ if (dev->bus->parent != NULL) {
+ bus = dev->bus->number;
+ MIPS_ASSERT(bus != 0);
+ } else {
+ bus = 0;
+ }
+
+ slot_num = PCI_SLOT(dev->devfn);
+ func_num = PCI_FUNC(dev->devfn);
+ base = ddb_access_config_base(swap, bus, slot_num);
+ *(volatile u32*) (base + (func_num << 8) + where) = val;
+ ddb_close_config_base(swap);
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_word(struct pci_config_swap *swap,
+ struct pci_dev *dev,
+ u32 where,
+ u16 val)
+{
+ int status, shift=0;
+ u32 result;
+
+ MIPS_ASSERT((where & 1) == 0);
+
+ status = read_config_dword(swap, dev, where & ~3, &result);
+ if (status != PCIBIOS_SUCCESSFUL) return status;
+
+ if (where & 2)
+ shift += 16;
+ result &= ~(0xffff << shift);
+ result |= val << shift;
+ return write_config_dword(swap, dev, where & ~3, result);
+}
+
+static int write_config_byte(struct pci_config_swap *swap,
+ struct pci_dev *dev,
+ u32 where,
+ u8 val)
+{
+ int status, shift=0;
+ u32 result;
+
+ status = read_config_dword(swap, dev, where & ~3, &result);
+ if (status != PCIBIOS_SUCCESSFUL) return status;
+
+ if (where & 2)
+ shift += 16;
+ if (where & 1)
+ shift += 8;
+ result &= ~(0xff << shift);
+ result |= val << shift;
+ return write_config_dword(swap, dev, where & ~3, result);
+}
+
+#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
+static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
+{ \
+ return rw##_config_##unitname(pciswap, \
+ dev, \
+ where, \
+ val); \
+}
+
+MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
+
+MAKE_PCI_OPS(iopci, read, byte, u8 *, &io_pci_swap)
+MAKE_PCI_OPS(iopci, read, word, u16 *, &io_pci_swap)
+MAKE_PCI_OPS(iopci, read, dword, u32 *, &io_pci_swap)
+
+MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
+MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
+
+MAKE_PCI_OPS(iopci, write, byte, u8, &io_pci_swap)
+MAKE_PCI_OPS(iopci, write, word, u16, &io_pci_swap)
+MAKE_PCI_OPS(iopci, write, dword, u32, &io_pci_swap)
+
+struct pci_ops ddb5477_ext_pci_ops ={
+ extpci_read_config_byte,
+ extpci_read_config_word,
+ extpci_read_config_dword,
+ extpci_write_config_byte,
+ extpci_write_config_word,
+ extpci_write_config_dword
+};
+
+
+struct pci_ops ddb5477_io_pci_ops ={
+ iopci_read_config_byte,
+ iopci_read_config_word,
+ iopci_read_config_dword,
+ iopci_write_config_byte,
+ iopci_write_config_word,
+ iopci_write_config_dword
+};
+
+#if defined(CONFIG_LL_DEBUG)
+void jsun_scan_pci_bus(void)
+{
+ struct pci_bus bus;
+ struct pci_dev dev;
+ unsigned int devfn;
+ int j;
+
+ bus.parent = NULL; /* we scan the top level only */
+ dev.bus = &bus;
+ dev.sysdata = NULL;
+
+ /* scan ext pci bus and io pci bus*/
+ for (j=0; j< 2; j++) {
+ if (j == 0) {
+ printk("scan ddb5477 external PCI bus:\n");
+ bus.ops = &ddb5477_ext_pci_ops;
+ } else {
+ printk("scan ddb5477 IO PCI bus:\n");
+ bus.ops = &ddb5477_io_pci_ops;
+ }
+
+ for (devfn = 0; devfn < 0x100; devfn += 8) {
+ u32 temp;
+ u16 temp16;
+ u8 temp8;
+ int i;
+
+ dev.devfn = devfn;
+ MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp),
+ == PCIBIOS_SUCCESSFUL);
+ if (temp == 0xffffffff) continue;
+
+ printk("slot %d: (addr %d) \n", devfn/8, 11+devfn/8);
+
+ /* verify read word and byte */
+ MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16),
+ == PCIBIOS_SUCCESSFUL);
+ MIPS_ASSERT(temp16 == (temp >> 16));
+ MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8),
+ == PCIBIOS_SUCCESSFUL);
+ MIPS_ASSERT(temp8 == (temp >> 24));
+ MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8),
+ == PCIBIOS_SUCCESSFUL);
+ MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff));
+
+ for (i=0; i < 16; i++) {
+ MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp),
+ == PCIBIOS_SUCCESSFUL);
+ printk("\t%08X", temp);
+ if ((i%4) == 3) printk("\n");
+ }
+ }
+ }
+}
+
+
+static void jsun_hardcode_pci_resources_eepro(void)
+{
+ struct pci_bus bus;
+ struct pci_dev dev;
+ u32 temp;
+
+ bus.parent = NULL; /* we scan the top level only */
+ bus.ops = &ddb5477_ext_pci_ops;
+ dev.bus = &bus;
+ dev.sysdata = NULL;
+
+ /* for slot 5 (ext pci 1) eepro card */
+ dev.devfn = 5*8;
+ pci_read_config_dword(&dev, 0, &temp);
+ MIPS_ASSERT(temp == 0x12298086);
+
+ pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, DDB_PCI0_MEM_BASE);
+ pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config_dword(&dev, PCI_BASE_ADDRESS_2, DDB_PCI0_MEM_BASE+0x100000);
+ pci_write_config_dword(&dev, PCI_INTERRUPT_LINE, 17);
+}
+
+static void jsun_hardcode_pci_resources_onboard_tulip(void)
+{
+ struct pci_bus bus;
+ struct pci_dev dev;
+ u32 temp;
+
+ bus.parent = NULL; /* we scan the top level only */
+ bus.ops = &ddb5477_ext_pci_ops;
+ dev.bus = &bus;
+ dev.sysdata = NULL;
+
+ /* for slot 4 on board ether chip */
+ dev.devfn = 4*8;
+ pci_read_config_dword(&dev, 0, &temp);
+ MIPS_ASSERT(temp == 0x00191011);
+
+ pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, 0x1000);
+ pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, DDB_PCI0_MEM_BASE);
+ pci_write_config_dword(&dev, PCI_INTERRUPT_LINE, 16);
+}
+
+static void jsun_hardcode_pci_resources(void)
+{
+ jsun_hardcode_pci_resources_onboard_tulip();
+}
+
+void jsun_assign_pci_resource(void)
+{
+ jsun_hardcode_pci_resources();
+}
+
+#endif
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
new file mode 100644
index 000000000..c236295f3
--- /dev/null
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -0,0 +1,251 @@
+/***********************************************************************
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * arch/mips/ddb5xxx/ddb5477/setup.c
+ * Setup file for DDB5477.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ ***********************************************************************
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/console.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/ide.h>
+#include <linux/fs.h> /* for ROOT_DEV */
+#include <linux/ioport.h>
+#include <linux/param.h> /* for HZ */
+
+#include <asm/addrspace.h>
+#include <asm/time.h>
+#include <asm/bcache.h>
+#include <asm/irq.h>
+#include <asm/reboot.h>
+#include <asm/gdb-stub.h>
+
+#include <asm/ddb5xxx/ddb5xxx.h>
+
+
+
+#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
+
+#ifdef USE_CPU_COUNTER_TIMER
+#define CPU_COUNTER_FREQUENCY 83000000
+#else
+/* otherwise we use special timer 1 */
+#define SP_TIMER_FREQUENCY 83000000
+#define SP_TIMER_BASE DDB_SPT1CTRL_L
+#define SP_TIMER_IRQ (8 + 6)
+#endif
+
+static void ddb_machine_restart(char *command)
+{
+ static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
+
+ u32 t;
+
+ /* PCI cold reset */
+ ddb_pci_reset_bus();
+
+ /* CPU cold reset */
+ t = ddb_in32(DDB_CPUSTAT);
+ MIPS_ASSERT((t&1));
+ ddb_out32(DDB_CPUSTAT, t);
+
+ /* Call the PROM */
+ back_to_prom();
+}
+
+static void ddb_machine_halt(void)
+{
+ printk("DDB Vrc-5477 halted.\n");
+ while (1);
+}
+
+static void ddb_machine_power_off(void)
+{
+ printk("DDB Vrc-5477 halted. Please turn off the power.\n");
+ while (1);
+}
+
+extern void rtc_ds1386_init(unsigned long base);
+static void __init ddb_time_init(void)
+{
+#if defined(USE_CPU_COUNTER_TIMER)
+ mips_counter_frequency = CPU_COUNTER_FREQUENCY;
+#endif
+
+ /* we have ds1396 RTC chip */
+ rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE));
+}
+
+#if defined(CONFIG_LL_DEBUG)
+int board_init_done_flag = 0;
+#endif
+
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+static void __init ddb_timer_setup(struct irqaction *irq)
+{
+#if defined(USE_CPU_COUNTER_TIMER)
+ unsigned int count;
+
+ /* we are using the cpu counter for timer interrupts */
+ setup_irq(7, irq);
+
+ /* to generate the first timer interrupt */
+ count = read_32bit_cp0_register(CP0_COUNT);
+ write_32bit_cp0_register(CP0_COMPARE, count + 1000);
+
+#else
+
+ /* if we don't use Special purpose timer 1 */
+ ddb_out32(SP_TIMER_BASE, SP_TIMER_FREQUENCY/HZ);
+ ddb_out32(SP_TIMER_BASE+4, 0x1);
+ setup_irq(SP_TIMER_IRQ, irq);
+
+#endif
+
+ /* this is the last board dependent code */
+ MIPS_DEBUG(board_init_done_flag = 1);
+}
+
+static void ddb5477_board_init(void);
+extern void ddb5477_irq_setup(void);
+
+#if defined(CONFIG_BLK_DEV_INITRD)
+extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
+#endif
+
+void __init ddb_setup(void)
+{
+ extern int panic_timeout;
+
+ irq_setup = ddb5477_irq_setup;
+ mips_io_port_base = KSEG1ADDR(DDB_PCI_IO_BASE);
+
+ board_time_init = ddb_time_init;
+ board_timer_setup = ddb_timer_setup;
+
+ _machine_restart = ddb_machine_restart;
+ _machine_halt = ddb_machine_halt;
+ _machine_power_off = ddb_machine_power_off;
+
+ /* setup resource limits */
+ ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
+ iomem_resource.end = 0xffffffff;
+
+ /* Reboot on panic */
+ panic_timeout = 180;
+
+ /* initialize board - we don't trust the loader */
+ ddb5477_board_init();
+
+#if defined(CONFIG_BLK_DEV_INITRD)
+ ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
+ initrd_start = (unsigned long)&__rd_start;
+ initrd_end = (unsigned long)&__rd_end;
+#endif
+
+}
+
+static void __init ddb5477_board_init()
+{
+ /* ----------- setup PDARs ------------ */
+
+ /* SDRAM should have been set */
+ MIPS_ASSERT(ddb_in32(DDB_SDRAM0) ==
+ ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
+
+ /* SDRAM1 should be turned off. What is this for anyway ? */
+ MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+
+ /* Set LDCSs */
+ /* flash */
+ ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
+ /* misc */
+ ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
+ /* mezzanie (?) */
+ ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
+
+ /* verify VRC5477 base addr */
+ MIPS_ASSERT(ddb_in32(DDB_VRC5477) ==
+ ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
+
+ /* verify BOOT ROM addr */
+ MIPS_ASSERT(ddb_in32(DDB_BOOTCS) ==
+ ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
+
+ /* setup PCI windows - window0 for MEM/config, window1 for IO */
+ ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
+
+ /* ------------ reset PCI bus and BARs ----------------- */
+ ddb_pci_reset_bus();
+
+ ddb_out32(DDB_BARM010, 0x00000008);
+ ddb_out32(DDB_BARM011, 0x00000008);
+
+ ddb_out32(DDB_BARC0, 0xffffffff);
+ ddb_out32(DDB_BARM230, 0xffffffff);
+ ddb_out32(DDB_BAR00, 0xffffffff);
+ ddb_out32(DDB_BAR10, 0xffffffff);
+ ddb_out32(DDB_BAR20, 0xffffffff);
+ ddb_out32(DDB_BAR30, 0xffffffff);
+ ddb_out32(DDB_BAR40, 0xffffffff);
+ ddb_out32(DDB_BAR50, 0xffffffff);
+ ddb_out32(DDB_BARB0, 0xffffffff);
+
+ ddb_out32(DDB_BARC1, 0xffffffff);
+ ddb_out32(DDB_BARM231, 0xffffffff);
+ ddb_out32(DDB_BAR01, 0xffffffff);
+ ddb_out32(DDB_BAR11, 0xffffffff);
+ ddb_out32(DDB_BAR21, 0xffffffff);
+ ddb_out32(DDB_BAR31, 0xffffffff);
+ ddb_out32(DDB_BAR41, 0xffffffff);
+ ddb_out32(DDB_BAR51, 0xffffffff);
+ ddb_out32(DDB_BARB1, 0xffffffff);
+
+ /*
+ * We use pci master register 0 for memory space / config space
+ * And we use register 1 for IO space.
+ * Note that for memory space, we bump up the pci base address
+ * so that we have 1:1 mapping between PCI memory and cpu physical.
+ * For PCI IO space, it starts from 0 in PCI IO space but with
+ * DDB_xx_IO_BASE in CPU physical address space.
+ */
+ ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
+ DDB_PCI_ACCESS_32);
+ ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
+
+ ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
+ DDB_PCI_ACCESS_32);
+ ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
+ DDB_PCI_ACCESS_32);
+
+
+ /* PCI cross window should be set properly */
+ ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
+ ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
+
+ /* enable USB input buffers */
+ ddb_out32(DDB_PIBMISC, 0x00000007);
+
+ /* For dual-function pins, make them all non-GPIO */
+ ddb_out32(DDB_GIUFUNSEL, 0x0);
+ // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 15:30:29 +0000