diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-01-11 04:02:40 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-01-11 04:02:40 +0000 |
| commit | e47f00743fc4776491344f2c618cc8dc2c23bcbc (patch) | |
| tree | 13e03a113a82a184c51c19c209867cfd3a59b3b9 /include/asm-ia64/sn/sn1 | |
| parent | b2ad5f821b1381492d792ca10b1eb7a107b48f14 (diff) | |
Merge with Linux 2.4.0.
Diffstat (limited to 'include/asm-ia64/sn/sn1')
25 files changed, 21136 insertions, 0 deletions
diff --git a/include/asm-ia64/sn/sn1/addrs.h b/include/asm-ia64/sn/sn1/addrs.h new file mode 100644 index 000000000..d5f6f7f93 --- /dev/null +++ b/include/asm-ia64/sn/sn1/addrs.h @@ -0,0 +1,311 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_ADDRS_H +#define _ASM_SN_SN1_ADDRS_H + +/* + * IP35 (on a TRex) Address map + * + * This file contains a set of definitions and macros which are used + * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, + * and UNCAC) used by the IP35 architecture. It also contains addresses + * for "major" statically locatable PROM/Kernel data structures, such as + * the partition table, the configuration data structure, etc. + * We make an implicit assumption that the processor using this file + * follows the R12K's provisions for specifying uncached attributes; + * should this change, the base registers may very well become processor- + * dependent. + * + * For more information on the address spaces, see the "Local Resources" + * chapter of the Hub specification. + * + * NOTE: This header file is included both by C and by assembler source + * files. Please bracket any language-dependent definitions + * appropriately. + */ + +#include <linux/config.h> + +/* + * Some of the macros here need to be casted to appropriate types when used + * from C. They definitely must not be casted from assembly language so we + * use some new ANSI preprocessor stuff to paste these on where needed. + */ + +#if defined(_RUN_UNCACHED) +#define CAC_BASE 0x9600000000000000 +#else +#define CAC_BASE 0xa800000000000000 +#endif + +#ifdef Colin +#define HSPEC_BASE 0x9000000000000000 +#define IO_BASE 0x9200000000000000 +#define MSPEC_BASE 0x9400000000000000 +#define UNCAC_BASE 0x9600000000000000 +#else +#define HSPEC_BASE 0xc0000b0000000000 +#define HSPEC_SWIZ_BASE 0xc000030000000000 +#define IO_BASE 0xc0000a0000000000 +#define IO_SWIZ_BASE 0xc000020000000000 +#define MSPEC_BASE 0xc000000000000000 +#define UNCAC_BASE 0xc000000000000000 +#endif + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) + + +/* + * The following couple of definitions will eventually need to be variables, + * since the amount of address space assigned to each node depends on + * whether the system is running in N-mode (more nodes with less memory) + * or M-mode (fewer nodes with more memory). We expect that it will + * be a while before we need to make this decision dynamically, though, + * so for now we just use defines bracketed by an ifdef. + */ + +#if defined(N_MODE) + +#define NODE_SIZE_BITS 32 +#define BWIN_SIZE_BITS 28 + +#define NASID_BITS 8 +#define NASID_BITMASK (0xffLL) +#define NASID_SHFT 32 +#define NASID_META_BITS 1 +#define NASID_LOCAL_BITS 7 + +#define BDDIR_UPPER_MASK (UINT64_CAST 0x1ffffff << 4) +#define BDECC_UPPER_MASK (UINT64_CAST 0x1fffffff ) + +#else /* !defined(N_MODE), assume that M-mode is desired */ + +#define NODE_SIZE_BITS 33 +#define BWIN_SIZE_BITS 29 + +#define NASID_BITMASK (0x7fLL) +#define NASID_BITS 7 +#define NASID_SHFT 33 +#define NASID_META_BITS 0 +#define NASID_LOCAL_BITS 7 + +#define BDDIR_UPPER_MASK (UINT64_CAST 0x3ffffff << 4) +#define BDECC_UPPER_MASK (UINT64_CAST 0x3fffffff) + +#endif /* defined(N_MODE) */ + +#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) + +#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) +#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ + NASID_SHFT) & NASID_BITMASK) + +#if _LANGUAGE_C && !defined(_STANDALONE) +#ifndef REAL_HARDWARE +#define NODE_SWIN_BASE(nasid, widget) RAW_NODE_SWIN_BASE(nasid, widget) +#else +#define NODE_SWIN_BASE(nasid, widget) \ + ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ + : RAW_NODE_SWIN_BASE(nasid, widget)) +#endif +#else +#define NODE_SWIN_BASE(nasid, widget) \ + (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) +#endif /* _LANGUAGE_C */ + +/* + * The following definitions pertain to the IO special address + * space. They define the location of the big and little windows + * of any given node. + */ + +#define BWIN_INDEX_BITS 3 +#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) +#define BWIN_SIZEMASK (BWIN_SIZE - 1) +#define BWIN_WIDGET_MASK 0x7 +#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) +#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ + (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) + +#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) +#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) +/* + * Verify if addr belongs to large window address of node with "nasid" + * + * + * NOTE: "addr" is expected to be XKPHYS address, and NOT physical + * address + * + * + */ + +#define NODE_BWIN_ADDR(nasid, addr) \ + (((addr) >= NODE_BWIN_BASE0(nasid)) && \ + ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ + BWIN_SIZE))) + +/* + * The following define the major position-independent aliases used + * in IP27. + * CALIAS -- Varies in size, points to the first n bytes of memory + * on the reader's node. + */ + +#define CALIAS_BASE CAC_BASE + + + +#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ + ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) + +#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) + +#if _LANGUAGE_C +#define KERN_NMI_ADDR(nasid, slice) \ + TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ + (IP27_NMI_KREGS_CPU_SIZE * (slice))) +#endif /* _LANGUAGE_C */ + + +/* + * needed by symmon so it needs to be outside #if PROM + * (see also POD_ELSCSIZE) + */ +#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x020e0000) +#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x020e0800) +#define IP27PROM_ELSC_BASE_C PHYS_TO_K0(0x020e1000) +#define IP27PROM_ELSC_BASE_D PHYS_TO_K0(0x020e1800) +#define IP27PROM_ELSC_SHFT 11 +#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) + +#define FREEMEM_BASE PHYS_TO_K0(0x4000000) + +#define IO6PROM_STACK_SHFT 14 /* stack per cpu */ +#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) + + +#define KL_UART_BASE LOCAL_HSPEC(HSPEC_UART_0) /* base of UART regs */ +#define KL_UART_CMD LOCAL_HSPEC(HSPEC_UART_0) /* UART command reg */ +#define KL_UART_DATA LOCAL_HSPEC(HSPEC_UART_1) /* UART data reg */ + +#if !_LANGUAGE_ASSEMBLY +/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc + * CACHE_ERR_SP_PTR could either contain an address to the stack, or + * the stack could start at CACHE_ERR_SP_PTR + */ +#define CACHE_ERR_EFRAME 0x400 + +#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) +#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ +#define CACHE_ERR_IBASE_PTR (0x1000 - 40) +#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) +#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) + +#endif /* !_LANGUAGE_ASSEMBLY */ + +/* Each CPU accesses UALIAS at a different physaddr, on 32k boundaries + * This determines the locations of the exception vectors + */ +#define UALIAS_FLIP_BASE UALIAS_BASE +#define UALIAS_FLIP_SHIFT 15 +#define UALIAS_FLIP_ADDR(_x) ((_x) ^ (cputoslice(getcpuid())<<UALIAS_FLIP_SHIFT)) + +#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC) +#define EX_HANDLER_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT) +#endif +#define EX_HANDLER_ADDR(nasid, slice) \ + PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice)) +#define EX_HANDLER_SIZE 0x0400 + +#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC) +#define EX_FRAME_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT | 0x400) +#endif +#define EX_FRAME_ADDR(nasid, slice) \ + PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice)) +#define EX_FRAME_SIZE 0x0c00 + +#define _ARCSPROM + +#ifdef _STANDALONE + +/* + * The PROM needs to pass the device base address and the + * device pci cfg space address to the device drivers during + * install. The COMPONENT->Key field is used for this purpose. + * Macros needed by IP27 device drivers to convert the + * COMPONENT->Key field to the respective base address. + * Key field looks as follows: + * + * +----------------------------------------------------+ + * |devnasid | widget |pciid |hubwidid|hstnasid | adap | + * | 2 | 1 | 1 | 1 | 2 | 1 | + * +----------------------------------------------------+ + * | | | | | | | + * 64 48 40 32 24 8 0 + * + * These are used by standalone drivers till the io infrastructure + * is in place. + */ + +#if _LANGUAGE_C + +#define uchar unsigned char + +#define KEY_DEVNASID_SHFT 48 +#define KEY_WIDID_SHFT 40 +#define KEY_PCIID_SHFT 32 +#define KEY_HUBWID_SHFT 24 +#define KEY_HSTNASID_SHFT 8 + +#define MK_SN0_KEY(nasid, widid, pciid) \ + ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\ + ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\ + ((__psunsigned_t)pciid) << KEY_PCIID_SHFT) + +#define ADD_HUBWID_KEY(key,hubwid)\ + (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT)) + +#define ADD_HSTNASID_KEY(key,hstnasid)\ + (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT)) + +#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT)) +#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT)) +#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT)) +#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT)) +#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT)) + +#define PCI_64_TARGID_SHFT 60 + +#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ + GET_WIDID_FROM_KEY(key))\ + | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key))) + +#define GET_PCICFGBASE_FROM_KEY(key) \ + (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ + GET_WIDID_FROM_KEY(key))\ + | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key))) + +#define GET_WIDBASE_FROM_KEY(key) \ + (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ + GET_WIDID_FROM_KEY(key))) + +#define PUT_INSTALL_STATUS(c,s) c->Revision = s +#define GET_INSTALL_STATUS(c) c->Revision + +#endif /* LANGUAGE_C */ + +#endif /* _STANDALONE */ + +#endif /* _ASM_SN_SN1_ADDRS_H */ diff --git a/include/asm-ia64/sn/sn1/arch.h b/include/asm-ia64/sn/sn1/arch.h new file mode 100644 index 000000000..94458112d --- /dev/null +++ b/include/asm-ia64/sn/sn1/arch.h @@ -0,0 +1,79 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_ARCH_H +#define _ASM_SN_SN1_ARCH_H + +#if defined(N_MODE) +#error "ERROR constants defined only for M-mode" +#endif + +/* + * This is the maximum number of NASIDS that can be present in a system. + * (Highest NASID plus one.) + */ +#define MAX_NASIDS 128 + +/* + * MAXCPUS refers to the maximum number of CPUs in a single kernel. + * This is not necessarily the same as MAXNODES * CPUS_PER_NODE + */ +#define MAXCPUS 512 + +/* + * This is the maximum number of nodes that can be part of a kernel. + * Effectively, it's the maximum number of compact node ids (cnodeid_t). + * This is not necessarily the same as MAX_NASIDS. + */ +#define MAX_COMPACT_NODES 128 + +/* + * MAX_REGIONS refers to the maximum number of hardware partitioned regions. + */ +#define MAX_REGIONS 64 +#define MAX_NONPREMIUM_REGIONS 16 +#define MAX_PREMIUM_REGIONS MAX_REGIONS + + +/* + * MAX_PARITIONS refers to the maximum number of logically defined + * partitions the system can support. + */ +#define MAX_PARTITIONS MAX_REGIONS + + +#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) + +/* + * Slot constants for IP35 + */ + +#define MAX_MEM_SLOTS 8 /* max slots per node */ + +#if defined(N_MODE) +#error "N-mode not supported" +#endif + +#define SLOT_SHIFT (30) +#define SLOT_MIN_MEM_SIZE (64*1024*1024) + +/* + * two PIs per bedrock, two CPUs per PI + */ +#define NUM_SUBNODES 2 +#define SUBNODE_SHFT 1 +#define SUBNODE_MASK (0x1 << SUBNODE_SHFT) +#define LOCALCPU_SHFT 0 +#define LOCALCPU_MASK (0x1 << LOCALCPU_SHFT) +#define SUBNODE(slice) (((slice) & SUBNODE_MASK) >> SUBNODE_SHFT) +#define LOCALCPU(slice) (((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT) +#define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ + ((local) << LOCALCPU_SHFT)) + +#endif /* _ASM_SN_SN1_ARCH_H */ diff --git a/include/asm-ia64/sn/sn1/bedrock.h b/include/asm-ia64/sn/sn1/bedrock.h new file mode 100644 index 000000000..fa98dfd68 --- /dev/null +++ b/include/asm-ia64/sn/sn1/bedrock.h @@ -0,0 +1,82 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_BEDROCK_H +#define _ASM_SN_SN1_BEDROCK_H + +/* The secret password; used to release protection */ +#define HUB_PASSWORD 0x53474972756c6573ull + +#define CHIPID_HUB 0x3012 +#define CHIPID_ROUTER 0x3017 + +#define BEDROCK_REV_1_0 1 +#define BEDROCK_REV_1_1 2 + +#define MAX_HUB_PATH 80 + +#include <linux/config.h> +#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#include <asm/sn/arch.h> +#include <asm/sn/sn1/addrs.h> +#include <asm/sn/sn1/hubpi.h> +#include <asm/sn/sn1/hubmd.h> +#include <asm/sn/sn1/hubio.h> +#include <asm/sn/sn1/hubni.h> +#include <asm/sn/sn1/hublb.h> +#include <asm/sn/sn1/hubxb.h> +#include <asm/sn/sn1/hubpi_next.h> +#include <asm/sn/sn1/hubmd_next.h> +#include <asm/sn/sn1/hubio_next.h> +#include <asm/sn/sn1/hubni_next.h> +#include <asm/sn/sn1/hublb_next.h> +#include <asm/sn/sn1/hubxb_next.h> + +#else /* ! CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */ + +<< BOMB! CONFIG_SGI_IP35 is only defined for IP35 >> + +#endif /* defined(CONFIG_SGI_IP35) */ + +/* Translation of uncached attributes */ +#define UATTR_HSPEC 0 +#define UATTR_IO 1 +#define UATTR_MSPEC 2 +#define UATTR_UNCAC 3 + +#if _LANGUAGE_ASSEMBLY + +/* + * Get nasid into register, r (uses at) + */ +#define GET_NASID_ASM(r) \ + dli r, LOCAL_HUB_ADDR(LB_REV_ID); \ + ld r, (r); \ + and r, LRI_NODEID_MASK; \ + dsrl r, LRI_NODEID_SHFT + +#endif /* _LANGUAGE_ASSEMBLY */ + +#if _LANGUAGE_C + +#include <asm/sn/xtalk/xwidget.h> + +/* hub-as-widget iograph info, labelled by INFO_LBL_XWIDGET */ +typedef struct v_hub_s *v_hub_t; +typedef uint64_t rtc_time_t; + +struct nodepda_s; +int hub_check_pci_equiv(void *addra, void *addrb); +void capture_hub_stats(cnodeid_t, struct nodepda_s *); +void init_hub_stats(cnodeid_t, struct nodepda_s *); + +#endif /* _LANGUAGE_C */ + +#endif /* _ASM_SN_SN1_BEDROCK_H */ diff --git a/include/asm-ia64/sn/sn1/hubdev.h b/include/asm-ia64/sn/sn1/hubdev.h new file mode 100644 index 000000000..63aecadf9 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubdev.h @@ -0,0 +1,22 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_HUBDEV_H +#define _ASM_SN_SN1_HUBDEV_H + +extern void hubdev_init(void); +extern void hubdev_register(int (*attach_method)(devfs_handle_t)); +extern int hubdev_unregister(int (*attach_method)(devfs_handle_t)); +extern int hubdev_docallouts(devfs_handle_t hub); + +extern caddr_t hubdev_prombase_get(devfs_handle_t hub); +extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub); + +#endif /* _ASM_SN_SN1_HUBDEV_H */ diff --git a/include/asm-ia64/sn/sn1/hubio.h b/include/asm-ia64/sn/sn1/hubio.h new file mode 100644 index 000000000..523741108 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubio.h @@ -0,0 +1,5017 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +/************************************************************************ + * * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * + * * + * This file is created by an automated script. Any (minimal) changes * + * made manually to this file should be made with care. * + * * + * MAKE ALL ADDITIONS TO THE END OF THIS FILE * + * * + ************************************************************************/ + + +#ifndef _ASM_SN_SN1_HUBIO_H +#define _ASM_SN_SN1_HUBIO_H + + +#define IIO_WID 0x00400000 /* + * Crosstalk Widget + * Identification This + * register is also + * accessible from + * Crosstalk at + * address 0x0. + */ + + + +#define IIO_WSTAT 0x00400008 /* + * Crosstalk Widget + * Status + */ + + + +#define IIO_WCR 0x00400020 /* + * Crosstalk Widget + * Control Register + */ + + + +#define IIO_ILAPR 0x00400100 /* + * IO Local Access + * Protection Register + */ + + + +#define IIO_ILAPO 0x00400108 /* + * IO Local Access + * Protection Override + */ + + + +#define IIO_IOWA 0x00400110 /* + * IO Outbound Widget + * Access + */ + + + +#define IIO_IIWA 0x00400118 /* + * IO Inbound Widget + * Access + */ + + + +#define IIO_IIDEM 0x00400120 /* + * IO Inbound Device + * Error Mask + */ + + + +#define IIO_ILCSR 0x00400128 /* + * IO LLP Control and + * Status Register + */ + + + +#define IIO_ILLR 0x00400130 /* IO LLP Log Register */ + + + +#define IIO_IIDSR 0x00400138 /* + * IO Interrupt + * Destination + */ + + + +#define IIO_IGFX0 0x00400140 /* + * IO Graphics + * Node-Widget Map 0 + */ + + + +#define IIO_IGFX1 0x00400148 /* + * IO Graphics + * Node-Widget Map 1 + */ + + + +#define IIO_ISCR0 0x00400150 /* + * IO Scratch Register + * 0 + */ + + + +#define IIO_ISCR1 0x00400158 /* + * IO Scratch Register + * 1 + */ + + + +#define IIO_ITTE1 0x00400160 /* + * IO Translation + * Table Entry 1 + */ + + + +#define IIO_ITTE2 0x00400168 /* + * IO Translation + * Table Entry 2 + */ + + + +#define IIO_ITTE3 0x00400170 /* + * IO Translation + * Table Entry 3 + */ + + + +#define IIO_ITTE4 0x00400178 /* + * IO Translation + * Table Entry 4 + */ + + + +#define IIO_ITTE5 0x00400180 /* + * IO Translation + * Table Entry 5 + */ + + + +#define IIO_ITTE6 0x00400188 /* + * IO Translation + * Table Entry 6 + */ + + + +#define IIO_ITTE7 0x00400190 /* + * IO Translation + * Table Entry 7 + */ + + + +#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ + + + +#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ + + + +#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ + + + +#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ + + + +#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ + + + +#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ + + + +#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ + + + +#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ + + + +#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ + + + +#define IIO_IXCC 0x004001E0 /* + * IO Crosstalk Credit + * Count Timeout + */ + + + +#define IIO_IMEM 0x004001E8 /* + * IO Miscellaneous + * Error Mask + */ + + + +#define IIO_IXTT 0x004001F0 /* + * IO Crosstalk + * Timeout Threshold + */ + + + +#define IIO_IECLR 0x004001F8 /* + * IO Error Clear + * Register + */ + + + +#define IIO_IBCR 0x00400200 /* + * IO BTE Control + * Register + */ + + + +#define IIO_IXSM 0x00400208 /* + * IO Crosstalk + * Spurious Message + */ + + + +#define IIO_IXSS 0x00400210 /* + * IO Crosstalk + * Spurious Sideband + */ + + + +#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ + + + +#define IIO_IIEPH1 0x00400220 /* + * IO Incoming Error + * Packet Header, Part + * 1 + */ + + + +#define IIO_IIEPH2 0x00400228 /* + * IO Incoming Error + * Packet Header, Part + * 2 + */ + + + +#define IIO_IPCA 0x00400300 /* + * IO PRB Counter + * Adjust + */ + + + +#define IIO_IPRTE0 0x00400308 /* + * IO PIO Read Address + * Table Entry 0 + */ + + + +#define IIO_IPRTE1 0x00400310 /* + * IO PIO Read Address + * Table Entry 1 + */ + + + +#define IIO_IPRTE2 0x00400318 /* + * IO PIO Read Address + * Table Entry 2 + */ + + + +#define IIO_IPRTE3 0x00400320 /* + * IO PIO Read Address + * Table Entry 3 + */ + + + +#define IIO_IPRTE4 0x00400328 /* + * IO PIO Read Address + * Table Entry 4 + */ + + + +#define IIO_IPRTE5 0x00400330 /* + * IO PIO Read Address + * Table Entry 5 + */ + + + +#define IIO_IPRTE6 0x00400338 /* + * IO PIO Read Address + * Table Entry 6 + */ + + + +#define IIO_IPRTE7 0x00400340 /* + * IO PIO Read Address + * Table Entry 7 + */ + + + +#define IIO_IPDR 0x00400388 /* + * IO PIO Deallocation + * Register + */ + + + +#define IIO_ICDR 0x00400390 /* + * IO CRB Entry + * Deallocation + * Register + */ + + + +#define IIO_IFDR 0x00400398 /* + * IO IOQ FIFO Depth + * Register + */ + + + +#define IIO_IIAP 0x004003A0 /* + * IO IIQ Arbitration + * Parameters + */ + + + +#define IIO_ICMR 0x004003A8 /* + * IO CRB Management + * Register + */ + + + +#define IIO_ICCR 0x004003B0 /* + * IO CRB Control + * Register + */ + + + +#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ + + + +#define IIO_ICTP 0x004003C0 /* + * IO CRB Timeout + * Prescalar + */ + + + +#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ + + + +#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ + + + +#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ + + + +#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ + + + +#define IIO_ICRB1_A 0x00400420 /* IO CRB Entry 1_A */ + + + +#define IIO_ICRB1_B 0x00400428 /* IO CRB Entry 1_B */ + + + +#define IIO_ICRB1_C 0x00400430 /* IO CRB Entry 1_C */ + + + +#define IIO_ICRB1_D 0x00400438 /* IO CRB Entry 1_D */ + + + +#define IIO_ICRB2_A 0x00400440 /* IO CRB Entry 2_A */ + + + +#define IIO_ICRB2_B 0x00400448 /* IO CRB Entry 2_B */ + + + +#define IIO_ICRB2_C 0x00400450 /* IO CRB Entry 2_C */ + + + +#define IIO_ICRB2_D 0x00400458 /* IO CRB Entry 2_D */ + + + +#define IIO_ICRB3_A 0x00400460 /* IO CRB Entry 3_A */ + + + +#define IIO_ICRB3_B 0x00400468 /* IO CRB Entry 3_B */ + + + +#define IIO_ICRB3_C 0x00400470 /* IO CRB Entry 3_C */ + + + +#define IIO_ICRB3_D 0x00400478 /* IO CRB Entry 3_D */ + + + +#define IIO_ICRB4_A 0x00400480 /* IO CRB Entry 4_A */ + + + +#define IIO_ICRB4_B 0x00400488 /* IO CRB Entry 4_B */ + + + +#define IIO_ICRB4_C 0x00400490 /* IO CRB Entry 4_C */ + + + +#define IIO_ICRB4_D 0x00400498 /* IO CRB Entry 4_D */ + + + +#define IIO_ICRB5_A 0x004004A0 /* IO CRB Entry 5_A */ + + + +#define IIO_ICRB5_B 0x004004A8 /* IO CRB Entry 5_B */ + + + +#define IIO_ICRB5_C 0x004004B0 /* IO CRB Entry 5_C */ + + + +#define IIO_ICRB5_D 0x004004B8 /* IO CRB Entry 5_D */ + + + +#define IIO_ICRB6_A 0x004004C0 /* IO CRB Entry 6_A */ + + + +#define IIO_ICRB6_B 0x004004C8 /* IO CRB Entry 6_B */ + + + +#define IIO_ICRB6_C 0x004004D0 /* IO CRB Entry 6_C */ + + + +#define IIO_ICRB6_D 0x004004D8 /* IO CRB Entry 6_D */ + + + +#define IIO_ICRB7_A 0x004004E0 /* IO CRB Entry 7_A */ + + + +#define IIO_ICRB7_B 0x004004E8 /* IO CRB Entry 7_B */ + + + +#define IIO_ICRB7_C 0x004004F0 /* IO CRB Entry 7_C */ + + + +#define IIO_ICRB7_D 0x004004F8 /* IO CRB Entry 7_D */ + + + +#define IIO_ICRB8_A 0x00400500 /* IO CRB Entry 8_A */ + + + +#define IIO_ICRB8_B 0x00400508 /* IO CRB Entry 8_B */ + + + +#define IIO_ICRB8_C 0x00400510 /* IO CRB Entry 8_C */ + + + +#define IIO_ICRB8_D 0x00400518 /* IO CRB Entry 8_D */ + + + +#define IIO_ICRB9_A 0x00400520 /* IO CRB Entry 9_A */ + + + +#define IIO_ICRB9_B 0x00400528 /* IO CRB Entry 9_B */ + + + +#define IIO_ICRB9_C 0x00400530 /* IO CRB Entry 9_C */ + + + +#define IIO_ICRB9_D 0x00400538 /* IO CRB Entry 9_D */ + + + +#define IIO_ICRBA_A 0x00400540 /* IO CRB Entry A_A */ + + + +#define IIO_ICRBA_B 0x00400548 /* IO CRB Entry A_B */ + + + +#define IIO_ICRBA_C 0x00400550 /* IO CRB Entry A_C */ + + + +#define IIO_ICRBA_D 0x00400558 /* IO CRB Entry A_D */ + + + +#define IIO_ICRBB_A 0x00400560 /* IO CRB Entry B_A */ + + + +#define IIO_ICRBB_B 0x00400568 /* IO CRB Entry B_B */ + + + +#define IIO_ICRBB_C 0x00400570 /* IO CRB Entry B_C */ + + + +#define IIO_ICRBB_D 0x00400578 /* IO CRB Entry B_D */ + + + +#define IIO_ICRBC_A 0x00400580 /* IO CRB Entry C_A */ + + + +#define IIO_ICRBC_B 0x00400588 /* IO CRB Entry C_B */ + + + +#define IIO_ICRBC_C 0x00400590 /* IO CRB Entry C_C */ + + + +#define IIO_ICRBC_D 0x00400598 /* IO CRB Entry C_D */ + + + +#define IIO_ICRBD_A 0x004005A0 /* IO CRB Entry D_A */ + + + +#define IIO_ICRBD_B 0x004005A8 /* IO CRB Entry D_B */ + + + +#define IIO_ICRBD_C 0x004005B0 /* IO CRB Entry D_C */ + + + +#define IIO_ICRBD_D 0x004005B8 /* IO CRB Entry D_D */ + + + +#define IIO_ICRBE_A 0x004005C0 /* IO CRB Entry E_A */ + + + +#define IIO_ICRBE_B 0x004005C8 /* IO CRB Entry E_B */ + + + +#define IIO_ICRBE_C 0x004005D0 /* IO CRB Entry E_C */ + + + +#define IIO_ICRBE_D 0x004005D8 /* IO CRB Entry E_D */ + + + +#define IIO_ICSML 0x00400600 /* + * IO CRB Spurious + * Message Low + */ + + + +#define IIO_ICSMH 0x00400608 /* + * IO CRB Spurious + * Message High + */ + + + +#define IIO_IDBSS 0x00400610 /* + * IO Debug Submenu + * Select + */ + + + +#define IIO_IBLS0 0x00410000 /* + * IO BTE Length + * Status 0 + */ + + + +#define IIO_IBSA0 0x00410008 /* + * IO BTE Source + * Address 0 + */ + + + +#define IIO_IBDA0 0x00410010 /* + * IO BTE Destination + * Address 0 + */ + + + +#define IIO_IBCT0 0x00410018 /* + * IO BTE Control + * Terminate 0 + */ + + + +#define IIO_IBNA0 0x00410020 /* + * IO BTE Notification + * Address 0 + */ + + + +#define IIO_IBIA0 0x00410028 /* + * IO BTE Interrupt + * Address 0 + */ + + + +#define IIO_IBLS1 0x00420000 /* + * IO BTE Length + * Status 1 + */ + + + +#define IIO_IBSA1 0x00420008 /* + * IO BTE Source + * Address 1 + */ + + + +#define IIO_IBDA1 0x00420010 /* + * IO BTE Destination + * Address 1 + */ + + + +#define IIO_IBCT1 0x00420018 /* + * IO BTE Control + * Terminate 1 + */ + + + +#define IIO_IBNA1 0x00420020 /* + * IO BTE Notification + * Address 1 + */ + + + +#define IIO_IBIA1 0x00420028 /* + * IO BTE Interrupt + * Address 1 + */ + + + +#define IIO_IPCR 0x00430000 /* + * IO Performance + * Control + */ + + + +#define IIO_IPPR 0x00430008 /* + * IO Performance + * Profiling + */ + + + + + +#ifdef _LANGUAGE_C + +/************************************************************************ + * * + * Description: This register echoes some information from the * + * LB_REV_ID register. It is available through Crosstalk as described * + * above. The REV_NUM and MFG_NUM fields receive their values from * + * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * + * The PART_NUM field's value is the Crosstalk device ID number that * + * Steve Miller assigned to the Bedrock chip. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_wid_u { + bdrkreg_t ii_wid_regval; + struct { + bdrkreg_t w_rsvd_1 : 1; + bdrkreg_t w_mfg_num : 11; + bdrkreg_t w_part_num : 16; + bdrkreg_t w_rev_num : 4; + bdrkreg_t w_rsvd : 32; + } ii_wid_fld_s; +} ii_wid_u_t; + +#else + +typedef union ii_wid_u { + bdrkreg_t ii_wid_regval; + struct { + bdrkreg_t w_rsvd : 32; + bdrkreg_t w_rev_num : 4; + bdrkreg_t w_part_num : 16; + bdrkreg_t w_mfg_num : 11; + bdrkreg_t w_rsvd_1 : 1; + } ii_wid_fld_s; +} ii_wid_u_t; + +#endif + + + + +/************************************************************************ + * * + * The fields in this register are set upon detection of an error * + * and cleared by various mechanisms, as explained in the * + * description. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_wstat_u { + bdrkreg_t ii_wstat_regval; + struct { + bdrkreg_t w_pending : 4; + bdrkreg_t w_xt_crd_to : 1; + bdrkreg_t w_xt_tail_to : 1; + bdrkreg_t w_rsvd_3 : 3; + bdrkreg_t w_tx_mx_rty : 1; + bdrkreg_t w_rsvd_2 : 6; + bdrkreg_t w_llp_tx_cnt : 8; + bdrkreg_t w_rsvd_1 : 8; + bdrkreg_t w_crazy : 1; + bdrkreg_t w_rsvd : 31; + } ii_wstat_fld_s; +} ii_wstat_u_t; + +#else + +typedef union ii_wstat_u { + bdrkreg_t ii_wstat_regval; + struct { + bdrkreg_t w_rsvd : 31; + bdrkreg_t w_crazy : 1; + bdrkreg_t w_rsvd_1 : 8; + bdrkreg_t w_llp_tx_cnt : 8; + bdrkreg_t w_rsvd_2 : 6; + bdrkreg_t w_tx_mx_rty : 1; + bdrkreg_t w_rsvd_3 : 3; + bdrkreg_t w_xt_tail_to : 1; + bdrkreg_t w_xt_crd_to : 1; + bdrkreg_t w_pending : 4; + } ii_wstat_fld_s; +} ii_wstat_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This is a read-write enabled register. It controls * + * various aspects of the Crosstalk flow control. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_wcr_u { + bdrkreg_t ii_wcr_regval; + struct { + bdrkreg_t w_wid : 4; + bdrkreg_t w_tag : 1; + bdrkreg_t w_rsvd_1 : 8; + bdrkreg_t w_dst_crd : 3; + bdrkreg_t w_f_bad_pkt : 1; + bdrkreg_t w_dir_con : 1; + bdrkreg_t w_e_thresh : 5; + bdrkreg_t w_rsvd : 41; + } ii_wcr_fld_s; +} ii_wcr_u_t; + +#else + +typedef union ii_wcr_u { + bdrkreg_t ii_wcr_regval; + struct { + bdrkreg_t w_rsvd : 41; + bdrkreg_t w_e_thresh : 5; + bdrkreg_t w_dir_con : 1; + bdrkreg_t w_f_bad_pkt : 1; + bdrkreg_t w_dst_crd : 3; + bdrkreg_t w_rsvd_1 : 8; + bdrkreg_t w_tag : 1; + bdrkreg_t w_wid : 4; + } ii_wcr_fld_s; +} ii_wcr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register's value is a bit vector that guards * + * access to local registers within the II as well as to external * + * Crosstalk widgets. Each bit in the register corresponds to a * + * particular region in the system; a region consists of one, two or * + * four nodes (depending on the value of the REGION_SIZE field in the * + * LB_REV_ID register, which is documented in Section 8.3.1.1). The * + * protection provided by this register applies to PIO read * + * operations as well as PIO write operations. The II will perform a * + * PIO read or write request only if the bit for the requestor's * + * region is set; otherwise, the II will not perform the requested * + * operation and will return an error response. When a PIO read or * + * write request targets an external Crosstalk widget, then not only * + * must the bit for the requestor's region be set in the ILAPR, but * + * also the target widget's bit in the IOWA register must be set in * + * order for the II to perform the requested operation; otherwise, * + * the II will return an error response. Hence, the protection * + * provided by the IOWA register supplements the protection provided * + * by the ILAPR for requests that target external Crosstalk widgets. * + * This register itself can be accessed only by the nodes whose * + * region ID bits are enabled in this same register. It can also be * + * accessed through the IAlias space by the local processors. * + * The reset value of this register allows access by all nodes. * + * * + ************************************************************************/ + + + + +typedef union ii_ilapr_u { + bdrkreg_t ii_ilapr_regval; + struct { + bdrkreg_t i_region : 64; + } ii_ilapr_fld_s; +} ii_ilapr_u_t; + + + + +/************************************************************************ + * * + * Description: A write to this register of the 64-bit value * + * "SGIrules" in ASCII, will cause the bit in the ILAPR register * + * corresponding to the region of the requestor to be set (allow * + * access). A write of any other value will be ignored. Access * + * protection for this register is "SGIrules". * + * This register can also be accessed through the IAlias space. * + * However, this access will not change the access permissions in the * + * ILAPR. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ilapo_u { + bdrkreg_t ii_ilapo_regval; + struct { + bdrkreg_t i_io_ovrride : 9; + bdrkreg_t i_rsvd : 55; + } ii_ilapo_fld_s; +} ii_ilapo_u_t; + +#else + +typedef union ii_ilapo_u { + bdrkreg_t ii_ilapo_regval; + struct { + bdrkreg_t i_rsvd : 55; + bdrkreg_t i_io_ovrride : 9; + } ii_ilapo_fld_s; +} ii_ilapo_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register qualifies all the PIO and Graphics writes launched * + * from the Bedrock towards a widget. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iowa_u { + bdrkreg_t ii_iowa_regval; + struct { + bdrkreg_t i_w0_oac : 1; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_wx_oac : 8; + bdrkreg_t i_rsvd : 48; + } ii_iowa_fld_s; +} ii_iowa_u_t; + +#else + +typedef union ii_iowa_u { + bdrkreg_t ii_iowa_regval; + struct { + bdrkreg_t i_rsvd : 48; + bdrkreg_t i_wx_oac : 8; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_w0_oac : 1; + } ii_iowa_fld_s; +} ii_iowa_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register qualifies all the requests launched * + * from a widget towards the Bedrock. This register is intended to be * + * used by software in case of misbehaving widgets. * + * * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iiwa_u { + bdrkreg_t ii_iiwa_regval; + struct { + bdrkreg_t i_w0_iac : 1; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_wx_iac : 8; + bdrkreg_t i_rsvd : 48; + } ii_iiwa_fld_s; +} ii_iiwa_u_t; + +#else + +typedef union ii_iiwa_u { + bdrkreg_t ii_iiwa_regval; + struct { + bdrkreg_t i_rsvd : 48; + bdrkreg_t i_wx_iac : 8; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_w0_iac : 1; + } ii_iiwa_fld_s; +} ii_iiwa_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register qualifies all the operations launched * + * from a widget towards the Bedrock. It allows individual access * + * control for up to 8 devices per widget. A device refers to * + * individual DMA master hosted by a widget. * + * The bits in each field of this register are cleared by the Bedrock * + * upon detection of an error which requires the device to be * + * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric * + * Crosstalk). Whether or not a device has access rights to this * + * Bedrock is determined by an AND of the device enable bit in the * + * appropriate field of this register and the corresponding bit in * + * the Wx_IAC field (for the widget which this device belongs to). * + * The bits in this field are set by writing a 1 to them. Incoming * + * replies from Crosstalk are not subject to this access control * + * mechanism. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iidem_u { + bdrkreg_t ii_iidem_regval; + struct { + bdrkreg_t i_w8_dxs : 8; + bdrkreg_t i_w9_dxs : 8; + bdrkreg_t i_wa_dxs : 8; + bdrkreg_t i_wb_dxs : 8; + bdrkreg_t i_wc_dxs : 8; + bdrkreg_t i_wd_dxs : 8; + bdrkreg_t i_we_dxs : 8; + bdrkreg_t i_wf_dxs : 8; + } ii_iidem_fld_s; +} ii_iidem_u_t; + +#else + +typedef union ii_iidem_u { + bdrkreg_t ii_iidem_regval; + struct { + bdrkreg_t i_wf_dxs : 8; + bdrkreg_t i_we_dxs : 8; + bdrkreg_t i_wd_dxs : 8; + bdrkreg_t i_wc_dxs : 8; + bdrkreg_t i_wb_dxs : 8; + bdrkreg_t i_wa_dxs : 8; + bdrkreg_t i_w9_dxs : 8; + bdrkreg_t i_w8_dxs : 8; + } ii_iidem_fld_s; +} ii_iidem_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the various programmable fields necessary * + * for controlling and observing the LLP signals. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ilcsr_u { + bdrkreg_t ii_ilcsr_regval; + struct { + bdrkreg_t i_nullto : 6; + bdrkreg_t i_rsvd_4 : 2; + bdrkreg_t i_wrmrst : 1; + bdrkreg_t i_rsvd_3 : 1; + bdrkreg_t i_llp_en : 1; + bdrkreg_t i_bm8 : 1; + bdrkreg_t i_llp_stat : 2; + bdrkreg_t i_remote_power : 1; + bdrkreg_t i_rsvd_2 : 1; + bdrkreg_t i_maxrtry : 10; + bdrkreg_t i_d_avail_sel : 2; + bdrkreg_t i_rsvd_1 : 4; + bdrkreg_t i_maxbrst : 10; + bdrkreg_t i_rsvd : 22; + + } ii_ilcsr_fld_s; +} ii_ilcsr_u_t; + +#else + +typedef union ii_ilcsr_u { + bdrkreg_t ii_ilcsr_regval; + struct { + bdrkreg_t i_rsvd : 22; + bdrkreg_t i_maxbrst : 10; + bdrkreg_t i_rsvd_1 : 4; + bdrkreg_t i_d_avail_sel : 2; + bdrkreg_t i_maxrtry : 10; + bdrkreg_t i_rsvd_2 : 1; + bdrkreg_t i_remote_power : 1; + bdrkreg_t i_llp_stat : 2; + bdrkreg_t i_bm8 : 1; + bdrkreg_t i_llp_en : 1; + bdrkreg_t i_rsvd_3 : 1; + bdrkreg_t i_wrmrst : 1; + bdrkreg_t i_rsvd_4 : 2; + bdrkreg_t i_nullto : 6; + } ii_ilcsr_fld_s; +} ii_ilcsr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This is simply a status registers that monitors the LLP error * + * rate. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_illr_u { + bdrkreg_t ii_illr_regval; + struct { + bdrkreg_t i_sn_cnt : 16; + bdrkreg_t i_cb_cnt : 16; + bdrkreg_t i_rsvd : 32; + } ii_illr_fld_s; +} ii_illr_u_t; + +#else + +typedef union ii_illr_u { + bdrkreg_t ii_illr_regval; + struct { + bdrkreg_t i_rsvd : 32; + bdrkreg_t i_cb_cnt : 16; + bdrkreg_t i_sn_cnt : 16; + } ii_illr_fld_s; +} ii_illr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: All II-detected non-BTE error interrupts are * + * specified via this register. * + * NOTE: The PI interrupt register address is hardcoded in the II. If * + * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI * + * packet) to address offset 0x0180_0090 within the local register * + * address space of PI0 on the node specified by the NODE field. If * + * PI_ID==1, then the II sends the interrupt request to address * + * offset 0x01A0_0090 within the local register address space of PI1 * + * on the node specified by the NODE field. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iidsr_u { + bdrkreg_t ii_iidsr_regval; + struct { + bdrkreg_t i_level : 7; + bdrkreg_t i_rsvd_4 : 1; + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_node : 8; + bdrkreg_t i_rsvd_3 : 7; + bdrkreg_t i_enable : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_int_sent : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_pi0_forward_int : 1; + bdrkreg_t i_pi1_forward_int : 1; + bdrkreg_t i_rsvd : 30; + } ii_iidsr_fld_s; +} ii_iidsr_u_t; + +#else + +typedef union ii_iidsr_u { + bdrkreg_t ii_iidsr_regval; + struct { + bdrkreg_t i_rsvd : 30; + bdrkreg_t i_pi1_forward_int : 1; + bdrkreg_t i_pi0_forward_int : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_int_sent : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_enable : 1; + bdrkreg_t i_rsvd_3 : 7; + bdrkreg_t i_node : 8; + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_rsvd_4 : 1; + bdrkreg_t i_level : 7; + } ii_iidsr_fld_s; +} ii_iidsr_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are two instances of this register. This register is used * + * for matching up the incoming responses from the graphics widget to * + * the processor that initiated the graphics operation. The * + * write-responses are converted to graphics credits and returned to * + * the processor so that the processor interface can manage the flow * + * control. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_igfx0_u { + bdrkreg_t ii_igfx0_regval; + struct { + bdrkreg_t i_w_num : 4; + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_n_num : 8; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_p_num : 1; + bdrkreg_t i_rsvd : 47; + } ii_igfx0_fld_s; +} ii_igfx0_u_t; + +#else + +typedef union ii_igfx0_u { + bdrkreg_t ii_igfx0_regval; + struct { + bdrkreg_t i_rsvd : 47; + bdrkreg_t i_p_num : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_n_num : 8; + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_w_num : 4; + } ii_igfx0_fld_s; +} ii_igfx0_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are two instances of this register. This register is used * + * for matching up the incoming responses from the graphics widget to * + * the processor that initiated the graphics operation. The * + * write-responses are converted to graphics credits and returned to * + * the processor so that the processor interface can manage the flow * + * control. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_igfx1_u { + bdrkreg_t ii_igfx1_regval; + struct { + bdrkreg_t i_w_num : 4; + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_n_num : 8; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_p_num : 1; + bdrkreg_t i_rsvd : 47; + } ii_igfx1_fld_s; +} ii_igfx1_u_t; + +#else + +typedef union ii_igfx1_u { + bdrkreg_t ii_igfx1_regval; + struct { + bdrkreg_t i_rsvd : 47; + bdrkreg_t i_p_num : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_n_num : 8; + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_w_num : 4; + } ii_igfx1_fld_s; +} ii_igfx1_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are two instances of this registers. These registers are * + * used as scratch registers for software use. * + * * + ************************************************************************/ + + + + +typedef union ii_iscr0_u { + bdrkreg_t ii_iscr0_regval; + struct { + bdrkreg_t i_scratch : 64; + } ii_iscr0_fld_s; +} ii_iscr0_u_t; + + + + +/************************************************************************ + * * + * There are two instances of this registers. These registers are * + * used as scratch registers for software use. * + * * + ************************************************************************/ + + + + +typedef union ii_iscr1_u { + bdrkreg_t ii_iscr1_regval; + struct { + bdrkreg_t i_scratch : 64; + } ii_iscr1_fld_s; +} ii_iscr1_u_t; + + + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Bedrock Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Bedrock is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Bedrock is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_itte1_u { + bdrkreg_t ii_itte1_regval; + struct { + bdrkreg_t i_offset : 5; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_rsvd : 51; + } ii_itte1_fld_s; +} ii_itte1_u_t; + +#else + +typedef union ii_itte1_u { + bdrkreg_t ii_itte1_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_offset : 5; + } ii_itte1_fld_s; +} ii_itte1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Bedrock Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Bedrock is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Bedrock is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_itte2_u { + bdrkreg_t ii_itte2_regval; + struct { + bdrkreg_t i_offset : 5; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_rsvd : 51; + } ii_itte2_fld_s; +} ii_itte2_u_t; + +#else +typedef union ii_itte2_u { + bdrkreg_t ii_itte2_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_offset : 5; + } ii_itte2_fld_s; +} ii_itte2_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Bedrock Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Bedrock is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Bedrock is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_itte3_u { + bdrkreg_t ii_itte3_regval; + struct { + bdrkreg_t i_offset : 5; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_rsvd : 51; + } ii_itte3_fld_s; +} ii_itte3_u_t; + +#else + +typedef union ii_itte3_u { + bdrkreg_t ii_itte3_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_offset : 5; + } ii_itte3_fld_s; +} ii_itte3_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Bedrock Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Bedrock is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Bedrock is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_itte4_u { + bdrkreg_t ii_itte4_regval; + struct { + bdrkreg_t i_offset : 5; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_rsvd : 51; + } ii_itte4_fld_s; +} ii_itte4_u_t; + +#else + +typedef union ii_itte4_u { + bdrkreg_t ii_itte4_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_offset : 5; + } ii_itte4_fld_s; +} ii_itte4_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Bedrock Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Bedrock is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Bedrock is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_itte5_u { + bdrkreg_t ii_itte5_regval; + struct { + bdrkreg_t i_offset : 5; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_rsvd : 51; + } ii_itte5_fld_s; +} ii_itte5_u_t; + +#else + +typedef union ii_itte5_u { + bdrkreg_t ii_itte5_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_offset : 5; + } ii_itte5_fld_s; +} ii_itte5_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Bedrock Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Bedrock is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Bedrock is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_itte6_u { + bdrkreg_t ii_itte6_regval; + struct { + bdrkreg_t i_offset : 5; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_rsvd : 51; + } ii_itte6_fld_s; +} ii_itte6_u_t; + +#else + +typedef union ii_itte6_u { + bdrkreg_t ii_itte6_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_offset : 5; + } ii_itte6_fld_s; +} ii_itte6_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Bedrock Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Bedrock is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Bedrock is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_itte7_u { + bdrkreg_t ii_itte7_regval; + struct { + bdrkreg_t i_offset : 5; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_rsvd : 51; + } ii_itte7_fld_s; +} ii_itte7_u_t; + +#else + +typedef union ii_itte7_u { + bdrkreg_t ii_itte7_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_iosp : 1; + bdrkreg_t i_w_num : 4; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_offset : 5; + } ii_itte7_fld_s; +} ii_itte7_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprb0_u { + bdrkreg_t ii_iprb0_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprb0_fld_s; +} ii_iprb0_u_t; + +#else + +typedef union ii_iprb0_u { + bdrkreg_t ii_iprb0_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprb0_fld_s; +} ii_iprb0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprb8_u { + bdrkreg_t ii_iprb8_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprb8_fld_s; +} ii_iprb8_u_t; + +#else + + +typedef union ii_iprb8_u { + bdrkreg_t ii_iprb8_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprb8_fld_s; +} ii_iprb8_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprb9_u { + bdrkreg_t ii_iprb9_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprb9_fld_s; +} ii_iprb9_u_t; + +#else + +typedef union ii_iprb9_u { + bdrkreg_t ii_iprb9_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprb9_fld_s; +} ii_iprb9_u_t; + +#endif + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprba_u { + bdrkreg_t ii_iprba_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprba_fld_s; +} ii_iprba_u_t; + +#else + +typedef union ii_iprba_u { + bdrkreg_t ii_iprba_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprba_fld_s; +} ii_iprba_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprbb_u { + bdrkreg_t ii_iprbb_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprbb_fld_s; +} ii_iprbb_u_t; + +#else + +typedef union ii_iprbb_u { + bdrkreg_t ii_iprbb_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprbb_fld_s; +} ii_iprbb_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprbc_u { + bdrkreg_t ii_iprbc_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprbc_fld_s; +} ii_iprbc_u_t; + +#else + +typedef union ii_iprbc_u { + bdrkreg_t ii_iprbc_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprbc_fld_s; +} ii_iprbc_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprbd_u { + bdrkreg_t ii_iprbd_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprbd_fld_s; +} ii_iprbd_u_t; + +#else + +typedef union ii_iprbd_u { + bdrkreg_t ii_iprbd_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprbd_fld_s; +} ii_iprbd_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprbe_u { + bdrkreg_t ii_iprbe_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprbe_fld_s; +} ii_iprbe_u_t; + +#else + +typedef union ii_iprbe_u { + bdrkreg_t ii_iprbe_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprbe_fld_s; +} ii_iprbe_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Bedrock and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprbf_u { + bdrkreg_t ii_iprbf_regval; + struct { + bdrkreg_t i_c : 8; + bdrkreg_t i_na : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_m : 2; + bdrkreg_t i_f : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_error : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_mult_err : 1; + } ii_iprbe_fld_s; +} ii_iprbf_u_t; + +#else + +typedef union ii_iprbf_u { + bdrkreg_t ii_iprbf_regval; + struct { + bdrkreg_t i_mult_err : 1; + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_spur_rd : 1; + bdrkreg_t i_spur_wr : 1; + bdrkreg_t i_rd_to : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_of_cnt : 5; + bdrkreg_t i_f : 1; + bdrkreg_t i_m : 2; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_nb : 14; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_na : 14; + bdrkreg_t i_c : 8; + } ii_iprbf_fld_s; +} ii_iprbf_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register specifies the timeout value to use for monitoring * + * Crosstalk credits which are used outbound to Crosstalk. An * + * internal counter called the Crosstalk Credit Timeout Counter * + * increments every 128 II clocks. The counter starts counting * + * anytime the credit count drops below a threshold, and resets to * + * zero (stops counting) anytime the credit count is at or above the * + * threshold. The threshold is 1 credit in direct connect mode and 2 * + * in Crossbow connect mode. When the internal Crosstalk Credit * + * Timeout Counter reaches the value programmed in this register, a * + * Crosstalk Credit Timeout has occurred. The internal counter is not * + * readable from software, and stops counting at its maximum value, * + * so it cannot cause more than one interrupt. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ixcc_u { + bdrkreg_t ii_ixcc_regval; + struct { + bdrkreg_t i_time_out : 26; + bdrkreg_t i_rsvd : 38; + } ii_ixcc_fld_s; +} ii_ixcc_u_t; + +#else + +typedef union ii_ixcc_u { + bdrkreg_t ii_ixcc_regval; + struct { + bdrkreg_t i_rsvd : 38; + bdrkreg_t i_time_out : 26; + } ii_ixcc_fld_s; +} ii_ixcc_u_t; + +#endif + + + +/************************************************************************ + * * + * Description: This register qualifies all the PIO and DMA * + * operations launched from widget 0 towards the Bedrock. In * + * addition, it also qualifies accesses by the BTE streams. * + * The bits in each field of this register are cleared by the Bedrock * + * upon detection of an error which requires widget 0 or the BTE * + * streams to be terminated. Whether or not widget x has access * + * rights to this Bedrock is determined by an AND of the device * + * enable bit in the appropriate field of this register and bit 0 in * + * the Wx_IAC field. The bits in this field are set by writing a 1 to * + * them. Incoming replies from Crosstalk are not subject to this * + * access control mechanism. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_imem_u { + bdrkreg_t ii_imem_regval; + struct { + bdrkreg_t i_w0_esd : 1; + bdrkreg_t i_rsvd_3 : 3; + bdrkreg_t i_b0_esd : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_b1_esd : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_clr_precise : 1; + bdrkreg_t i_rsvd : 51; + } ii_imem_fld_s; +} ii_imem_u_t; + +#else + +typedef union ii_imem_u { + bdrkreg_t ii_imem_regval; + struct { + bdrkreg_t i_rsvd : 51; + bdrkreg_t i_clr_precise : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_b1_esd : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_b0_esd : 1; + bdrkreg_t i_rsvd_3 : 3; + bdrkreg_t i_w0_esd : 1; + } ii_imem_fld_s; +} ii_imem_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register specifies the timeout value to use for * + * monitoring Crosstalk tail flits coming into the Bedrock in the * + * TAIL_TO field. An internal counter associated with this register * + * is incremented every 128 II internal clocks (7 bits). The counter * + * starts counting anytime a header micropacket is received and stops * + * counting (and resets to zero) any time a micropacket with a Tail * + * bit is received. Once the counter reaches the threshold value * + * programmed in this register, it generates an interrupt to the * + * processor that is programmed into the IIDSR. The counter saturates * + * (does not roll over) at its maximum value, so it cannot cause * + * another interrupt until after it is cleared. * + * The register also contains the Read Response Timeout values. The * + * Prescalar is 23 bits, and counts II clocks. An internal counter * + * increments on every II clock and when it reaches the value in the * + * Prescalar field, all IPRTE registers with their valid bits set * + * have their Read Response timers bumped. Whenever any of them match * + * the value in the RRSP_TO field, a Read Response Timeout has * + * occurred, and error handling occurs as described in the Error * + * Handling section of this document. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ixtt_u { + bdrkreg_t ii_ixtt_regval; + struct { + bdrkreg_t i_tail_to : 26; + bdrkreg_t i_rsvd_1 : 6; + bdrkreg_t i_rrsp_ps : 23; + bdrkreg_t i_rrsp_to : 5; + bdrkreg_t i_rsvd : 4; + } ii_ixtt_fld_s; +} ii_ixtt_u_t; + +#else + +typedef union ii_ixtt_u { + bdrkreg_t ii_ixtt_regval; + struct { + bdrkreg_t i_rsvd : 4; + bdrkreg_t i_rrsp_to : 5; + bdrkreg_t i_rrsp_ps : 23; + bdrkreg_t i_rsvd_1 : 6; + bdrkreg_t i_tail_to : 26; + } ii_ixtt_fld_s; +} ii_ixtt_u_t; + +#endif + + + + +/************************************************************************ + * * + * Writing a 1 to the fields of this register clears the appropriate * + * error bits in other areas of Bedrock_II. Note that when the * + * E_PRB_x bits are used to clear error bits in PRB registers, * + * SPUR_RD and SPUR_WR may persist, because they require additional * + * action to clear them. See the IPRBx and IXSS Register * + * specifications. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ieclr_u { + bdrkreg_t ii_ieclr_regval; + struct { + bdrkreg_t i_e_prb_0 : 1; + bdrkreg_t i_rsvd : 7; + bdrkreg_t i_e_prb_8 : 1; + bdrkreg_t i_e_prb_9 : 1; + bdrkreg_t i_e_prb_a : 1; + bdrkreg_t i_e_prb_b : 1; + bdrkreg_t i_e_prb_c : 1; + bdrkreg_t i_e_prb_d : 1; + bdrkreg_t i_e_prb_e : 1; + bdrkreg_t i_e_prb_f : 1; + bdrkreg_t i_e_crazy : 1; + bdrkreg_t i_e_bte_0 : 1; + bdrkreg_t i_e_bte_1 : 1; + bdrkreg_t i_reserved_1 : 9; + bdrkreg_t i_ii_internal : 1; + bdrkreg_t i_spur_rd_hdr : 1; + bdrkreg_t i_pi0_forward_int : 1; + bdrkreg_t i_pi1_forward_int : 1; + bdrkreg_t i_reserved : 32; + } ii_ieclr_fld_s; +} ii_ieclr_u_t; + +#else + +typedef union ii_ieclr_u { + bdrkreg_t ii_ieclr_regval; + struct { + bdrkreg_t i_reserved : 32; + bdrkreg_t i_pi1_forward_int : 1; + bdrkreg_t i_pi0_forward_int : 1; + bdrkreg_t i_spur_rd_hdr : 1; + bdrkreg_t i_ii_internal : 1; + bdrkreg_t i_reserved_1 : 9; + bdrkreg_t i_e_bte_1 : 1; + bdrkreg_t i_e_bte_0 : 1; + bdrkreg_t i_e_crazy : 1; + bdrkreg_t i_e_prb_f : 1; + bdrkreg_t i_e_prb_e : 1; + bdrkreg_t i_e_prb_d : 1; + bdrkreg_t i_e_prb_c : 1; + bdrkreg_t i_e_prb_b : 1; + bdrkreg_t i_e_prb_a : 1; + bdrkreg_t i_e_prb_9 : 1; + bdrkreg_t i_e_prb_8 : 1; + bdrkreg_t i_rsvd : 7; + bdrkreg_t i_e_prb_0 : 1; + } ii_ieclr_fld_s; +} ii_ieclr_u_t; + +#endif + + + + + +/************************************************************************ + * * + * This register controls both BTEs. SOFT_RESET is intended for * + * recovery after an error. COUNT controls the total number of CRBs * + * that both BTEs (combined) can use, which affects total BTE * + * bandwidth. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibcr_u { + bdrkreg_t ii_ibcr_regval; + struct { + bdrkreg_t i_count : 4; + bdrkreg_t i_rsvd_1 : 4; + bdrkreg_t i_soft_reset : 1; + bdrkreg_t i_rsvd : 55; + } ii_ibcr_fld_s; +} ii_ibcr_u_t; + +#else + +typedef union ii_ibcr_u { + bdrkreg_t ii_ibcr_regval; + struct { + bdrkreg_t i_rsvd : 55; + bdrkreg_t i_soft_reset : 1; + bdrkreg_t i_rsvd_1 : 4; + bdrkreg_t i_count : 4; + } ii_ibcr_fld_s; +} ii_ibcr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the header of a spurious read response * + * received from Crosstalk. A spurious read response is defined as a * + * read response received by II from a widget for which (1) the SIDN * + * has a value between 1 and 7, inclusive (II never sends requests to * + * these widgets (2) there is no valid IPRTE register which * + * corresponds to the TNUM, or (3) the widget indicated in SIDN is * + * not the same as the widget recorded in the IPRTE register * + * referenced by the TNUM. If this condition is true, and if the * + * IXSS[VALID] bit is clear, then the header of the spurious read * + * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * + * errant header is thereby captured, and no further spurious read * + * respones are captured until IXSS[VALID] is cleared by setting the * + * appropriate bit in IECLR.Everytime a spurious read response is * + * detected, the SPUR_RD bit of the PRB corresponding to the incoming * + * message's SIDN field is set. This always happens, regarless of * + * whether a header is captured. The programmer should check * + * IXSM[SIDN] to determine which widget sent the spurious response, * + * because there may be more than one SPUR_RD bit set in the PRB * + * registers. The widget indicated by IXSM[SIDN] was the first * + * spurious read response to be received since the last time * + * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB * + * will be set. Any SPUR_RD bits in any other PRB registers indicate * + * spurious messages from other widets which were detected after the * + * header was captured.. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ixsm_u { + bdrkreg_t ii_ixsm_regval; + struct { + bdrkreg_t i_byte_en : 32; + bdrkreg_t i_reserved : 1; + bdrkreg_t i_tag : 3; + bdrkreg_t i_alt_pactyp : 4; + bdrkreg_t i_bo : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_vbpm : 1; + bdrkreg_t i_gbr : 1; + bdrkreg_t i_ds : 2; + bdrkreg_t i_ct : 1; + bdrkreg_t i_tnum : 5; + bdrkreg_t i_pactyp : 4; + bdrkreg_t i_sidn : 4; + bdrkreg_t i_didn : 4; + } ii_ixsm_fld_s; +} ii_ixsm_u_t; + +#else + +typedef union ii_ixsm_u { + bdrkreg_t ii_ixsm_regval; + struct { + bdrkreg_t i_didn : 4; + bdrkreg_t i_sidn : 4; + bdrkreg_t i_pactyp : 4; + bdrkreg_t i_tnum : 5; + bdrkreg_t i_ct : 1; + bdrkreg_t i_ds : 2; + bdrkreg_t i_gbr : 1; + bdrkreg_t i_vbpm : 1; + bdrkreg_t i_error : 1; + bdrkreg_t i_bo : 1; + bdrkreg_t i_alt_pactyp : 4; + bdrkreg_t i_tag : 3; + bdrkreg_t i_reserved : 1; + bdrkreg_t i_byte_en : 32; + } ii_ixsm_fld_s; +} ii_ixsm_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the sideband bits of a spurious read * + * response received from Crosstalk. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ixss_u { + bdrkreg_t ii_ixss_regval; + struct { + bdrkreg_t i_sideband : 8; + bdrkreg_t i_rsvd : 55; + bdrkreg_t i_valid : 1; + } ii_ixss_fld_s; +} ii_ixss_u_t; + +#else + +typedef union ii_ixss_u { + bdrkreg_t ii_ixss_regval; + struct { + bdrkreg_t i_valid : 1; + bdrkreg_t i_rsvd : 55; + bdrkreg_t i_sideband : 8; + } ii_ixss_fld_s; +} ii_ixss_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register enables software to access the II LLP's test port. * + * Refer to the LLP 2.5 documentation for an explanation of the test * + * port. Software can write to this register to program the values * + * for the control fields (TestErrCapture, TestClear, TestFlit, * + * TestMask and TestSeed). Similarly, software can read from this * + * register to obtain the values of the test port's status outputs * + * (TestCBerr, TestValid and TestData). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ilct_u { + bdrkreg_t ii_ilct_regval; + struct { + bdrkreg_t i_rsvd : 9; + bdrkreg_t i_test_err_capture : 1; + bdrkreg_t i_test_clear : 1; + bdrkreg_t i_test_flit : 3; + bdrkreg_t i_test_cberr : 1; + bdrkreg_t i_test_valid : 1; + bdrkreg_t i_test_data : 20; + bdrkreg_t i_test_mask : 8; + bdrkreg_t i_test_seed : 20; + } ii_ilct_fld_s; +} ii_ilct_u_t; + +#else + +typedef union ii_ilct_u { + bdrkreg_t ii_ilct_regval; + struct { + bdrkreg_t i_rsvd : 9; + bdrkreg_t i_test_err_capture : 1; + bdrkreg_t i_test_clear : 1; + bdrkreg_t i_test_flit : 3; + bdrkreg_t i_test_cberr : 1; + bdrkreg_t i_test_valid : 1; + bdrkreg_t i_test_data : 20; + bdrkreg_t i_test_mask : 8; + bdrkreg_t i_test_seed : 20; + } ii_ilct_fld_s; +} ii_ilct_u_t; + +#endif + + + + +/************************************************************************ + * * + * If the II detects an illegal incoming Duplonet packet (request or * + * reply) when VALID==0 in the IIEPH1 register, then it saves the * + * contents of the packet's header flit in the IIEPH1 and IIEPH2 * + * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, * + * and assigns a value to the ERR_TYPE field which indicates the * + * specific nature of the error. The II recognizes four different * + * types of errors: short request packets (ERR_TYPE==2), short reply * + * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long * + * reply packets (ERR_TYPE==5). The encodings for these types of * + * errors were chosen to be consistent with the same types of errors * + * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in * + * the LB unit). If the II detects an illegal incoming Duplonet * + * packet when VALID==1 in the IIEPH1 register, then it merely sets * + * the OVERRUN bit to indicate that a subsequent error has happened, * + * and does nothing further. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iieph1_u { + bdrkreg_t ii_iieph1_regval; + struct { + bdrkreg_t i_command : 7; + bdrkreg_t i_rsvd_5 : 1; + bdrkreg_t i_suppl : 11; + bdrkreg_t i_rsvd_4 : 1; + bdrkreg_t i_source : 11; + bdrkreg_t i_rsvd_3 : 1; + bdrkreg_t i_err_type : 4; + bdrkreg_t i_rsvd_2 : 4; + bdrkreg_t i_overrun : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_valid : 1; + bdrkreg_t i_rsvd : 19; + } ii_iieph1_fld_s; +} ii_iieph1_u_t; + +#else + +typedef union ii_iieph1_u { + bdrkreg_t ii_iieph1_regval; + struct { + bdrkreg_t i_rsvd : 19; + bdrkreg_t i_valid : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_overrun : 1; + bdrkreg_t i_rsvd_2 : 4; + bdrkreg_t i_err_type : 4; + bdrkreg_t i_rsvd_3 : 1; + bdrkreg_t i_source : 11; + bdrkreg_t i_rsvd_4 : 1; + bdrkreg_t i_suppl : 11; + bdrkreg_t i_rsvd_5 : 1; + bdrkreg_t i_command : 7; + } ii_iieph1_fld_s; +} ii_iieph1_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register holds the Address field from the header flit of an * + * incoming erroneous Duplonet packet, along with the tail bit which * + * accompanied this header flit. This register is essentially an * + * extension of IIEPH1. Two registers were necessary because the 64 * + * bits available in only a single register were insufficient to * + * capture the entire header flit of an erroneous packet. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iieph2_u { + bdrkreg_t ii_iieph2_regval; + struct { + bdrkreg_t i_address : 38; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_tail : 1; + bdrkreg_t i_rsvd : 23; + } ii_iieph2_fld_s; +} ii_iieph2_u_t; + +#else + +typedef union ii_iieph2_u { + bdrkreg_t ii_iieph2_regval; + struct { + bdrkreg_t i_rsvd : 23; + bdrkreg_t i_tail : 1; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_address : 38; + } ii_iieph2_fld_s; +} ii_iieph2_u_t; + +#endif + + + + +/************************************************************************ + * * + * A write to this register causes a particular field in the * + * corresponding widget's PRB entry to be adjusted up or down by 1. * + * This counter should be used when recovering from error and reset * + * conditions. Note that software would be capable of causing * + * inadvertent overflow or underflow of these counters. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ipca_u { + bdrkreg_t ii_ipca_regval; + struct { + bdrkreg_t i_wid : 4; + bdrkreg_t i_adjust : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_field : 2; + bdrkreg_t i_rsvd : 54; + } ii_ipca_fld_s; +} ii_ipca_u_t; + +#else + +typedef union ii_ipca_u { + bdrkreg_t ii_ipca_regval; + struct { + bdrkreg_t i_rsvd : 54; + bdrkreg_t i_field : 2; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_adjust : 1; + bdrkreg_t i_wid : 4; + } ii_ipca_fld_s; +} ii_ipca_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte0_u { + bdrkreg_t ii_iprte0_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte0_fld_s; +} ii_iprte0_u_t; + +#else + +typedef union ii_iprte0_u { + bdrkreg_t ii_iprte0_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte0_fld_s; +} ii_iprte0_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte1_u { + bdrkreg_t ii_iprte1_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte1_fld_s; +} ii_iprte1_u_t; + +#else + +typedef union ii_iprte1_u { + bdrkreg_t ii_iprte1_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte1_fld_s; +} ii_iprte1_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte2_u { + bdrkreg_t ii_iprte2_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte2_fld_s; +} ii_iprte2_u_t; + +#else + +typedef union ii_iprte2_u { + bdrkreg_t ii_iprte2_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte2_fld_s; +} ii_iprte2_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte3_u { + bdrkreg_t ii_iprte3_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte3_fld_s; +} ii_iprte3_u_t; + +#else + +typedef union ii_iprte3_u { + bdrkreg_t ii_iprte3_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte3_fld_s; +} ii_iprte3_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte4_u { + bdrkreg_t ii_iprte4_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte4_fld_s; +} ii_iprte4_u_t; + +#else + +typedef union ii_iprte4_u { + bdrkreg_t ii_iprte4_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte4_fld_s; +} ii_iprte4_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte5_u { + bdrkreg_t ii_iprte5_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte5_fld_s; +} ii_iprte5_u_t; + +#else + +typedef union ii_iprte5_u { + bdrkreg_t ii_iprte5_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte5_fld_s; +} ii_iprte5_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte6_u { + bdrkreg_t ii_iprte6_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte6_fld_s; +} ii_iprte6_u_t; + +#else + +typedef union ii_iprte6_u { + bdrkreg_t ii_iprte6_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte6_fld_s; +} ii_iprte6_u_t; + +#endif + + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iprte7_u { + bdrkreg_t ii_iprte7_regval; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } ii_iprte7_fld_s; +} ii_iprte7_u_t; + +#else + +typedef union ii_iprte7_u { + bdrkreg_t ii_iprte7_regval; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } ii_iprte7_fld_s; +} ii_iprte7_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: Bedrock_II contains a feature which did not exist in * + * the Hub which automatically cleans up after a Read Response * + * timeout, including deallocation of the IPRTE and recovery of IBuf * + * space. The inclusion of this register in Bedrock is for backward * + * compatibility * + * A write to this register causes an entry from the table of * + * outstanding PIO Read Requests to be freed and returned to the * + * stack of free entries. This register is used in handling the * + * timeout errors that result in a PIO Reply never returning from * + * Crosstalk. * + * Note that this register does not affect the contents of the IPRTE * + * registers. The Valid bits in those registers have to be * + * specifically turned off by software. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ipdr_u { + bdrkreg_t ii_ipdr_regval; + struct { + bdrkreg_t i_te : 3; + bdrkreg_t i_rsvd_1 : 1; + bdrkreg_t i_pnd : 1; + bdrkreg_t i_init_rpcnt : 1; + bdrkreg_t i_rsvd : 58; + } ii_ipdr_fld_s; +} ii_ipdr_u_t; + +#else + +typedef union ii_ipdr_u { + bdrkreg_t ii_ipdr_regval; + struct { + bdrkreg_t i_rsvd : 58; + bdrkreg_t i_init_rpcnt : 1; + bdrkreg_t i_pnd : 1; + bdrkreg_t i_rsvd_1 : 1; + bdrkreg_t i_te : 3; + } ii_ipdr_fld_s; +} ii_ipdr_u_t; + +#endif + + + + +/************************************************************************ + * * + * A write to this register causes a CRB entry to be returned to the * + * queue of free CRBs. The entry should have previously been cleared * + * (mark bit) via backdoor access to the pertinent CRB entry. This * + * register is used in the last step of handling the errors that are * + * captured and marked in CRB entries. Briefly: 1) first error for * + * DMA write from a particular device, and first error for a * + * particular BTE stream, lead to a marked CRB entry, and processor * + * interrupt, 2) software reads the error information captured in the * + * CRB entry, and presumably takes some corrective action, 3) * + * software clears the mark bit, and finally 4) software writes to * + * the ICDR register to return the CRB entry to the list of free CRB * + * entries. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icdr_u { + bdrkreg_t ii_icdr_regval; + struct { + bdrkreg_t i_crb_num : 4; + bdrkreg_t i_pnd : 1; + bdrkreg_t i_rsvd : 59; + } ii_icdr_fld_s; +} ii_icdr_u_t; + +#else + +typedef union ii_icdr_u { + bdrkreg_t ii_icdr_regval; + struct { + bdrkreg_t i_rsvd : 59; + bdrkreg_t i_pnd : 1; + bdrkreg_t i_crb_num : 4; + } ii_icdr_fld_s; +} ii_icdr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register provides debug access to two FIFOs inside of II. * + * Both IOQ_MAX* fields of this register contain the instantaneous * + * depth (in units of the number of available entries) of the * + * associated IOQ FIFO. A read of this register will return the * + * number of free entries on each FIFO at the time of the read. So * + * when a FIFO is idle, the associated field contains the maximum * + * depth of the FIFO. This register is writable for debug reasons * + * and is intended to be written with the maximum desired FIFO depth * + * while the FIFO is idle. Software must assure that II is idle when * + * this register is written. If there are any active entries in any * + * of these FIFOs when this register is written, the results are * + * undefined. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ifdr_u { + bdrkreg_t ii_ifdr_regval; + struct { + bdrkreg_t i_ioq_max_rq : 7; + bdrkreg_t i_set_ioq_rq : 1; + bdrkreg_t i_ioq_max_rp : 7; + bdrkreg_t i_set_ioq_rp : 1; + bdrkreg_t i_rsvd : 48; + } ii_ifdr_fld_s; +} ii_ifdr_u_t; + +#else + +typedef union ii_ifdr_u { + bdrkreg_t ii_ifdr_regval; + struct { + bdrkreg_t i_rsvd : 48; + bdrkreg_t i_set_ioq_rp : 1; + bdrkreg_t i_ioq_max_rp : 7; + bdrkreg_t i_set_ioq_rq : 1; + bdrkreg_t i_ioq_max_rq : 7; + } ii_ifdr_fld_s; +} ii_ifdr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register allows the II to become sluggish in removing * + * messages from its inbound queue (IIQ). This will cause messages to * + * back up in either virtual channel. Disabling the "molasses" mode * + * subsequently allows the II to be tested under stress. In the * + * sluggish ("Molasses") mode, the localized effects of congestion * + * can be observed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iiap_u { + bdrkreg_t ii_iiap_regval; + struct { + bdrkreg_t i_rq_mls : 6; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_rp_mls : 6; + bdrkreg_t i_rsvd : 50; + } ii_iiap_fld_s; +} ii_iiap_u_t; + +#else + +typedef union ii_iiap_u { + bdrkreg_t ii_iiap_regval; + struct { + bdrkreg_t i_rsvd : 50; + bdrkreg_t i_rp_mls : 6; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_rq_mls : 6; + } ii_iiap_fld_s; +} ii_iiap_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register allows several parameters of CRB operation to be * + * set. Note that writing to this register can have catastrophic side * + * effects, if the CRB is not quiescent, i.e. if the CRB is * + * processing protocol messages when the write occurs. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icmr_u { + bdrkreg_t ii_icmr_regval; + struct { + bdrkreg_t i_sp_msg : 1; + bdrkreg_t i_rd_hdr : 1; + bdrkreg_t i_rsvd_4 : 2; + bdrkreg_t i_c_cnt : 4; + bdrkreg_t i_rsvd_3 : 4; + bdrkreg_t i_clr_rqpd : 1; + bdrkreg_t i_clr_rppd : 1; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_fc_cnt : 4; + bdrkreg_t i_crb_vld : 15; + bdrkreg_t i_crb_mark : 15; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_precise : 1; + bdrkreg_t i_rsvd : 11; + } ii_icmr_fld_s; +} ii_icmr_u_t; + +#else + +typedef union ii_icmr_u { + bdrkreg_t ii_icmr_regval; + struct { + bdrkreg_t i_rsvd : 11; + bdrkreg_t i_precise : 1; + bdrkreg_t i_rsvd_1 : 2; + bdrkreg_t i_crb_mark : 15; + bdrkreg_t i_crb_vld : 15; + bdrkreg_t i_fc_cnt : 4; + bdrkreg_t i_rsvd_2 : 2; + bdrkreg_t i_clr_rppd : 1; + bdrkreg_t i_clr_rqpd : 1; + bdrkreg_t i_rsvd_3 : 4; + bdrkreg_t i_c_cnt : 4; + bdrkreg_t i_rsvd_4 : 2; + bdrkreg_t i_rd_hdr : 1; + bdrkreg_t i_sp_msg : 1; + } ii_icmr_fld_s; +} ii_icmr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register allows control of the table portion of the CRB * + * logic via software. Control operations from this register have * + * priority over all incoming Crosstalk or BTE requests. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_iccr_u { + bdrkreg_t ii_iccr_regval; + struct { + bdrkreg_t i_crb_num : 4; + bdrkreg_t i_rsvd_1 : 4; + bdrkreg_t i_cmd : 8; + bdrkreg_t i_pending : 1; + bdrkreg_t i_rsvd : 47; + } ii_iccr_fld_s; +} ii_iccr_u_t; + +#else + +typedef union ii_iccr_u { + bdrkreg_t ii_iccr_regval; + struct { + bdrkreg_t i_rsvd : 47; + bdrkreg_t i_pending : 1; + bdrkreg_t i_cmd : 8; + bdrkreg_t i_rsvd_1 : 4; + bdrkreg_t i_crb_num : 4; + } ii_iccr_fld_s; +} ii_iccr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register allows the maximum timeout value to be programmed. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icto_u { + bdrkreg_t ii_icto_regval; + struct { + bdrkreg_t i_timeout : 8; + bdrkreg_t i_rsvd : 56; + } ii_icto_fld_s; +} ii_icto_u_t; + +#else + +typedef union ii_icto_u { + bdrkreg_t ii_icto_regval; + struct { + bdrkreg_t i_rsvd : 56; + bdrkreg_t i_timeout : 8; + } ii_icto_fld_s; +} ii_icto_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register allows the timeout prescalar to be programmed. An * + * internal counter is associated with this register. When the * + * internal counter reaches the value of the PRESCALE field, the * + * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * + * field). The internal counter resets to zero, and then continues * + * counting. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ictp_u { + bdrkreg_t ii_ictp_regval; + struct { + bdrkreg_t i_prescale : 24; + bdrkreg_t i_rsvd : 40; + } ii_ictp_fld_s; +} ii_ictp_u_t; + +#else + +typedef union ii_ictp_u { + bdrkreg_t ii_ictp_regval; + struct { + bdrkreg_t i_rsvd : 40; + bdrkreg_t i_prescale : 24; + } ii_ictp_fld_s; +} ii_ictp_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, four * + * registers (_A to _D) are required to read and write each entry. * + * The CRB Entry registers can be conceptualized as rows and columns * + * (illustrated in the table above). Each row contains the 4 * + * registers required for a single CRB Entry. The first doubleword * + * (column) for each entry is labeled A, and the second doubleword * + * (higher address) is labeled B, the third doubleword is labeled C, * + * and the fourth doubleword is labeled D. All CRB entries have their * + * addresses on a quarter cacheline aligned boundary. * + * Upon reset, only the following fields are initialized: valid * + * (VLD), priority count, timeout, timeout valid, and context valid. * + * All other bits should be cleared by software before use (after * + * recovering any potential error state from before the reset). * + * The following four tables summarize the format for the four * + * registers that are used for each ICRB# Entry. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icrb0_a_u { + bdrkreg_t ii_icrb0_a_regval; + struct { + bdrkreg_t ia_iow : 1; + bdrkreg_t ia_vld : 1; + bdrkreg_t ia_addr : 38; + bdrkreg_t ia_tnum : 5; + bdrkreg_t ia_sidn : 4; + bdrkreg_t ia_xt_err : 1; + bdrkreg_t ia_mark : 1; + bdrkreg_t ia_ln_uce : 1; + bdrkreg_t ia_errcode : 3; + bdrkreg_t ia_error : 1; + bdrkreg_t ia_stall__bte_1 : 1; + bdrkreg_t ia_stall__bte_0 : 1; + bdrkreg_t ia_rsvd : 6; + } ii_icrb0_a_fld_s; +} ii_icrb0_a_u_t; + +#else + +typedef union ii_icrb0_a_u { + bdrkreg_t ii_icrb0_a_regval; + struct { + bdrkreg_t ia_rsvd : 6; + bdrkreg_t ia_stall__bte_0 : 1; + bdrkreg_t ia_stall__bte_1 : 1; + bdrkreg_t ia_error : 1; + bdrkreg_t ia_errcode : 3; + bdrkreg_t ia_ln_uce : 1; + bdrkreg_t ia_mark : 1; + bdrkreg_t ia_xt_err : 1; + bdrkreg_t ia_sidn : 4; + bdrkreg_t ia_tnum : 5; + bdrkreg_t ia_addr : 38; + bdrkreg_t ia_vld : 1; + bdrkreg_t ia_iow : 1; + } ii_icrb0_a_fld_s; +} ii_icrb0_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, four * + * registers (_A to _D) are required to read and write each entry. * + * * + ************************************************************************/ + + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icrb0_b_u { + bdrkreg_t ii_icrb0_b_regval; + struct { + bdrkreg_t ib_stall__intr : 1; + bdrkreg_t ib_stall_ib : 1; + bdrkreg_t ib_intvn : 1; + bdrkreg_t ib_wb : 1; + bdrkreg_t ib_hold : 1; + bdrkreg_t ib_ack : 1; + bdrkreg_t ib_resp : 1; + bdrkreg_t ib_ack_cnt : 11; + bdrkreg_t ib_rsvd_1 : 7; + bdrkreg_t ib_exc : 5; + bdrkreg_t ib_init : 3; + bdrkreg_t ib_imsg : 8; + bdrkreg_t ib_imsgtype : 2; + bdrkreg_t ib_use_old : 1; + bdrkreg_t ib_source : 12; + bdrkreg_t ib_size : 2; + bdrkreg_t ib_ct : 1; + bdrkreg_t ib_bte_num : 1; + bdrkreg_t ib_rsvd : 4; + } ii_icrb0_b_fld_s; +} ii_icrb0_b_u_t; + +#else + +typedef union ii_icrb0_b_u { + bdrkreg_t ii_icrb0_b_regval; + struct { + bdrkreg_t ib_rsvd : 4; + bdrkreg_t ib_bte_num : 1; + bdrkreg_t ib_ct : 1; + bdrkreg_t ib_size : 2; + bdrkreg_t ib_source : 12; + bdrkreg_t ib_use_old : 1; + bdrkreg_t ib_imsgtype : 2; + bdrkreg_t ib_imsg : 8; + bdrkreg_t ib_init : 3; + bdrkreg_t ib_exc : 5; + bdrkreg_t ib_rsvd_1 : 7; + bdrkreg_t ib_ack_cnt : 11; + bdrkreg_t ib_resp : 1; + bdrkreg_t ib_ack : 1; + bdrkreg_t ib_hold : 1; + bdrkreg_t ib_wb : 1; + bdrkreg_t ib_intvn : 1; + bdrkreg_t ib_stall_ib : 1; + bdrkreg_t ib_stall__intr : 1; + } ii_icrb0_b_fld_s; +} ii_icrb0_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, four * + * registers (_A to _D) are required to read and write each entry. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icrb0_c_u { + bdrkreg_t ii_icrb0_c_regval; + struct { + bdrkreg_t ic_gbr : 1; + bdrkreg_t ic_resprqd : 1; + bdrkreg_t ic_bo : 1; + bdrkreg_t ic_suppl : 12; + bdrkreg_t ic_pa_be : 34; + bdrkreg_t ic_bte_op : 1; + bdrkreg_t ic_pr_psc : 4; + bdrkreg_t ic_pr_cnt : 4; + bdrkreg_t ic_sleep : 1; + bdrkreg_t ic_rsvd : 5; + } ii_icrb0_c_fld_s; +} ii_icrb0_c_u_t; + +#else + +typedef union ii_icrb0_c_u { + bdrkreg_t ii_icrb0_c_regval; + struct { + bdrkreg_t ic_rsvd : 5; + bdrkreg_t ic_sleep : 1; + bdrkreg_t ic_pr_cnt : 4; + bdrkreg_t ic_pr_psc : 4; + bdrkreg_t ic_bte_op : 1; + bdrkreg_t ic_pa_be : 34; + bdrkreg_t ic_suppl : 12; + bdrkreg_t ic_bo : 1; + bdrkreg_t ic_resprqd : 1; + bdrkreg_t ic_gbr : 1; + } ii_icrb0_c_fld_s; +} ii_icrb0_c_u_t; + +#endif + + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, four * + * registers (_A to _D) are required to read and write each entry. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icrb0_d_u { + bdrkreg_t ii_icrb0_d_regval; + struct { + bdrkreg_t id_timeout : 8; + bdrkreg_t id_context : 15; + bdrkreg_t id_rsvd_1 : 1; + bdrkreg_t id_tvld : 1; + bdrkreg_t id_cvld : 1; + bdrkreg_t id_rsvd : 38; + } ii_icrb0_d_fld_s; +} ii_icrb0_d_u_t; + +#else + +typedef union ii_icrb0_d_u { + bdrkreg_t ii_icrb0_d_regval; + struct { + bdrkreg_t id_rsvd : 38; + bdrkreg_t id_cvld : 1; + bdrkreg_t id_tvld : 1; + bdrkreg_t id_rsvd_1 : 1; + bdrkreg_t id_context : 15; + bdrkreg_t id_timeout : 8; + } ii_icrb0_d_fld_s; +} ii_icrb0_d_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the lower 64 bits of the header of the * + * spurious message captured by II. Valid when the SP_MSG bit in ICMR * + * register is set. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icsml_u { + bdrkreg_t ii_icsml_regval; + struct { + bdrkreg_t i_tt_addr : 38; + bdrkreg_t i_tt_ack_cnt : 11; + bdrkreg_t i_newsuppl_ex : 11; + bdrkreg_t i_reserved : 3; + bdrkreg_t i_overflow : 1; + } ii_icsml_fld_s; +} ii_icsml_u_t; + +#else + +typedef union ii_icsml_u { + bdrkreg_t ii_icsml_regval; + struct { + bdrkreg_t i_overflow : 1; + bdrkreg_t i_reserved : 3; + bdrkreg_t i_newsuppl_ex : 11; + bdrkreg_t i_tt_ack_cnt : 11; + bdrkreg_t i_tt_addr : 38; + } ii_icsml_fld_s; +} ii_icsml_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the microscopic state, all the inputs to * + * the protocol table, captured with the spurious message. Valid when * + * the SP_MSG bit in the ICMR register is set. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_icsmh_u { + bdrkreg_t ii_icsmh_regval; + struct { + bdrkreg_t i_tt_vld : 1; + bdrkreg_t i_xerr : 1; + bdrkreg_t i_ft_cwact_o : 1; + bdrkreg_t i_ft_wact_o : 1; + bdrkreg_t i_ft_active_o : 1; + bdrkreg_t i_sync : 1; + bdrkreg_t i_mnusg : 1; + bdrkreg_t i_mnusz : 1; + bdrkreg_t i_plusz : 1; + bdrkreg_t i_plusg : 1; + bdrkreg_t i_tt_exc : 5; + bdrkreg_t i_tt_wb : 1; + bdrkreg_t i_tt_hold : 1; + bdrkreg_t i_tt_ack : 1; + bdrkreg_t i_tt_resp : 1; + bdrkreg_t i_tt_intvn : 1; + bdrkreg_t i_g_stall_bte1 : 1; + bdrkreg_t i_g_stall_bte0 : 1; + bdrkreg_t i_g_stall_il : 1; + bdrkreg_t i_g_stall_ib : 1; + bdrkreg_t i_tt_imsg : 8; + bdrkreg_t i_tt_imsgtype : 2; + bdrkreg_t i_tt_use_old : 1; + bdrkreg_t i_tt_respreqd : 1; + bdrkreg_t i_tt_bte_num : 1; + bdrkreg_t i_cbn : 1; + bdrkreg_t i_match : 1; + bdrkreg_t i_rpcnt_lt_34 : 1; + bdrkreg_t i_rpcnt_ge_34 : 1; + bdrkreg_t i_rpcnt_lt_18 : 1; + bdrkreg_t i_rpcnt_ge_18 : 1; + bdrkreg_t i_rpcnt_lt_2 : 1; + bdrkreg_t i_rpcnt_ge_2 : 1; + bdrkreg_t i_rqcnt_lt_18 : 1; + bdrkreg_t i_rqcnt_ge_18 : 1; + bdrkreg_t i_rqcnt_lt_2 : 1; + bdrkreg_t i_rqcnt_ge_2 : 1; + bdrkreg_t i_tt_device : 7; + bdrkreg_t i_tt_init : 3; + bdrkreg_t i_reserved : 5; + } ii_icsmh_fld_s; +} ii_icsmh_u_t; + +#else + +typedef union ii_icsmh_u { + bdrkreg_t ii_icsmh_regval; + struct { + bdrkreg_t i_reserved : 5; + bdrkreg_t i_tt_init : 3; + bdrkreg_t i_tt_device : 7; + bdrkreg_t i_rqcnt_ge_2 : 1; + bdrkreg_t i_rqcnt_lt_2 : 1; + bdrkreg_t i_rqcnt_ge_18 : 1; + bdrkreg_t i_rqcnt_lt_18 : 1; + bdrkreg_t i_rpcnt_ge_2 : 1; + bdrkreg_t i_rpcnt_lt_2 : 1; + bdrkreg_t i_rpcnt_ge_18 : 1; + bdrkreg_t i_rpcnt_lt_18 : 1; + bdrkreg_t i_rpcnt_ge_34 : 1; + bdrkreg_t i_rpcnt_lt_34 : 1; + bdrkreg_t i_match : 1; + bdrkreg_t i_cbn : 1; + bdrkreg_t i_tt_bte_num : 1; + bdrkreg_t i_tt_respreqd : 1; + bdrkreg_t i_tt_use_old : 1; + bdrkreg_t i_tt_imsgtype : 2; + bdrkreg_t i_tt_imsg : 8; + bdrkreg_t i_g_stall_ib : 1; + bdrkreg_t i_g_stall_il : 1; + bdrkreg_t i_g_stall_bte0 : 1; + bdrkreg_t i_g_stall_bte1 : 1; + bdrkreg_t i_tt_intvn : 1; + bdrkreg_t i_tt_resp : 1; + bdrkreg_t i_tt_ack : 1; + bdrkreg_t i_tt_hold : 1; + bdrkreg_t i_tt_wb : 1; + bdrkreg_t i_tt_exc : 5; + bdrkreg_t i_plusg : 1; + bdrkreg_t i_plusz : 1; + bdrkreg_t i_mnusz : 1; + bdrkreg_t i_mnusg : 1; + bdrkreg_t i_sync : 1; + bdrkreg_t i_ft_active_o : 1; + bdrkreg_t i_ft_wact_o : 1; + bdrkreg_t i_ft_cwact_o : 1; + bdrkreg_t i_xerr : 1; + bdrkreg_t i_tt_vld : 1; + } ii_icsmh_fld_s; +} ii_icsmh_u_t; + +#endif + + +/************************************************************************ + * * + * The Bedrock DEBUG unit provides a 3-bit selection signal to the * + * II unit, thus allowing a choice of one set of debug signal outputs * + * from a menu of 8 options. Each option is limited to 32 bits in * + * size. There are more signals of interest than can be accommodated * + * in this 8*32 framework, so the IDBSS register has been defined to * + * extend the range of choices available. For each menu option * + * available to the DEBUG unit, the II provides a "submenu" of * + * several options. The value of the SUBMENU field in the IDBSS * + * register selects the desired submenu. Hence, the particular debug * + * signals provided by the II are determined by the 3-bit selection * + * signal from the DEBUG unit and the value of the SUBMENU field * + * within the IDBSS register. For a detailed description of the * + * available menus and submenus for II debug signals, refer to the * + * documentation in ii_interface.doc.. * + * * + ************************************************************************/ + + + + +#ifdef LIITLE_ENDIAN + +typedef union ii_idbss_u { + bdrkreg_t ii_idbss_regval; + struct { + bdrkreg_t i_submenu : 3; + bdrkreg_t i_rsvd : 61; + } ii_idbss_fld_s; +} ii_idbss_u_t; + +#else + +typedef union ii_idbss_u { + bdrkreg_t ii_idbss_regval; + struct { + bdrkreg_t i_rsvd : 61; + bdrkreg_t i_submenu : 3; + } ii_idbss_fld_s; +} ii_idbss_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register is used to set up the length for a * + * transfer and then to monitor the progress of that transfer. This * + * register needs to be initialized before a transfer is started. A * + * legitimate write to this register will set the Busy bit, clear the * + * Error bit, and initialize the length to the value desired. * + * While the transfer is in progress, hardware will decrement the * + * length field with each successful block that is copied. Once the * + * transfer completes, hardware will clear the Busy bit. The length * + * field will also contain the number of cache lines left to be * + * transferred. * + * * + ************************************************************************/ + + + + +#ifdef LIITLE_ENDIAN + +typedef union ii_ibls0_u { + bdrkreg_t ii_ibls0_regval; + struct { + bdrkreg_t i_length : 16; + bdrkreg_t i_error : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_busy : 1; + bdrkreg_t i_rsvd : 43; + } ii_ibls0_fld_s; +} ii_ibls0_u_t; + +#else + +typedef union ii_ibls0_u { + bdrkreg_t ii_ibls0_regval; + struct { + bdrkreg_t i_rsvd : 43; + bdrkreg_t i_busy : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_error : 1; + bdrkreg_t i_length : 16; + } ii_ibls0_fld_s; +} ii_ibls0_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibsa0_u { + bdrkreg_t ii_ibsa0_regval; + struct { + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd : 24; + } ii_ibsa0_fld_s; +} ii_ibsa0_u_t; + +#else + +typedef union ii_ibsa0_u { + bdrkreg_t ii_ibsa0_regval; + struct { + bdrkreg_t i_rsvd : 24; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd_1 : 7; + } ii_ibsa0_fld_s; +} ii_ibsa0_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibda0_u { + bdrkreg_t ii_ibda0_regval; + struct { + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd : 24; + } ii_ibda0_fld_s; +} ii_ibda0_u_t; + +#else + +typedef union ii_ibda0_u { + bdrkreg_t ii_ibda0_regval; + struct { + bdrkreg_t i_rsvd : 24; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd_1 : 7; + } ii_ibda0_fld_s; +} ii_ibda0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Writing to this register sets up the attributes of the transfer * + * and initiates the transfer operation. Reading this register has * + * the side effect of terminating any transfer in progress. Note: * + * stopping a transfer midstream could have an adverse impact on the * + * other BTE. If a BTE stream has to be stopped (due to error * + * handling for example), both BTE streams should be stopped and * + * their transfers discarded. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibct0_u { + bdrkreg_t ii_ibct0_regval; + struct { + bdrkreg_t i_zerofill : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_notify : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_poison : 1; + bdrkreg_t i_rsvd : 55; + } ii_ibct0_fld_s; +} ii_ibct0_u_t; + +#else + +typedef union ii_ibct0_u { + bdrkreg_t ii_ibct0_regval; + struct { + bdrkreg_t i_rsvd : 55; + bdrkreg_t i_poison : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_notify : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_zerofill : 1; + } ii_ibct0_fld_s; +} ii_ibct0_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the address to which the WINV is sent. * + * This address has to be cache line aligned. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibna0_u { + bdrkreg_t ii_ibna0_regval; + struct { + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd : 24; + } ii_ibna0_fld_s; +} ii_ibna0_u_t; + +#else + +typedef union ii_ibna0_u { + bdrkreg_t ii_ibna0_regval; + struct { + bdrkreg_t i_rsvd : 24; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd_1 : 7; + } ii_ibna0_fld_s; +} ii_ibna0_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the programmable level as well as the node * + * ID and PI unit of the processor to which the interrupt will be * + * sent. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibia0_u { + bdrkreg_t ii_ibia0_regval; + struct { + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_node_id : 8; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_level : 7; + bdrkreg_t i_rsvd : 41; + } ii_ibia0_fld_s; +} ii_ibia0_u_t; + +#else + +typedef union ii_ibia0_u { + bdrkreg_t ii_ibia0_regval; + struct { + bdrkreg_t i_rsvd : 41; + bdrkreg_t i_level : 7; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_node_id : 8; + bdrkreg_t i_pi_id : 1; + } ii_ibia0_fld_s; +} ii_ibia0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register is used to set up the length for a * + * transfer and then to monitor the progress of that transfer. This * + * register needs to be initialized before a transfer is started. A * + * legitimate write to this register will set the Busy bit, clear the * + * Error bit, and initialize the length to the value desired. * + * While the transfer is in progress, hardware will decrement the * + * length field with each successful block that is copied. Once the * + * transfer completes, hardware will clear the Busy bit. The length * + * field will also contain the number of cache lines left to be * + * transferred. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibls1_u { + bdrkreg_t ii_ibls1_regval; + struct { + bdrkreg_t i_length : 16; + bdrkreg_t i_error : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_busy : 1; + bdrkreg_t i_rsvd : 43; + } ii_ibls1_fld_s; +} ii_ibls1_u_t; + +#else + +typedef union ii_ibls1_u { + bdrkreg_t ii_ibls1_regval; + struct { + bdrkreg_t i_rsvd : 43; + bdrkreg_t i_busy : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_error : 1; + bdrkreg_t i_length : 16; + } ii_ibls1_fld_s; +} ii_ibls1_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibsa1_u { + bdrkreg_t ii_ibsa1_regval; + struct { + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd : 24; + } ii_ibsa1_fld_s; +} ii_ibsa1_u_t; + +#else + +typedef union ii_ibsa1_u { + bdrkreg_t ii_ibsa1_regval; + struct { + bdrkreg_t i_rsvd : 24; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd_1 : 7; + } ii_ibsa1_fld_s; +} ii_ibsa1_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibda1_u { + bdrkreg_t ii_ibda1_regval; + struct { + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd : 24; + } ii_ibda1_fld_s; +} ii_ibda1_u_t; + +#else + +typedef union ii_ibda1_u { + bdrkreg_t ii_ibda1_regval; + struct { + bdrkreg_t i_rsvd : 24; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd_1 : 7; + } ii_ibda1_fld_s; +} ii_ibda1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Writing to this register sets up the attributes of the transfer * + * and initiates the transfer operation. Reading this register has * + * the side effect of terminating any transfer in progress. Note: * + * stopping a transfer midstream could have an adverse impact on the * + * other BTE. If a BTE stream has to be stopped (due to error * + * handling for example), both BTE streams should be stopped and * + * their transfers discarded. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibct1_u { + bdrkreg_t ii_ibct1_regval; + struct { + bdrkreg_t i_zerofill : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_notify : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_poison : 1; + bdrkreg_t i_rsvd : 55; + } ii_ibct1_fld_s; +} ii_ibct1_u_t; + +#else + +typedef union ii_ibct1_u { + bdrkreg_t ii_ibct1_regval; + struct { + bdrkreg_t i_rsvd : 55; + bdrkreg_t i_poison : 1; + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_notify : 1; + bdrkreg_t i_rsvd_2 : 3; + bdrkreg_t i_zerofill : 1; + } ii_ibct1_fld_s; +} ii_ibct1_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the address to which the WINV is sent. * + * This address has to be cache line aligned. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibna1_u { + bdrkreg_t ii_ibna1_regval; + struct { + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd : 24; + } ii_ibna1_fld_s; +} ii_ibna1_u_t; + +#else + +typedef union ii_ibna1_u { + bdrkreg_t ii_ibna1_regval; + struct { + bdrkreg_t i_rsvd : 24; + bdrkreg_t i_addr : 33; + bdrkreg_t i_rsvd_1 : 7; + } ii_ibna1_fld_s; +} ii_ibna1_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the programmable level as well as the node * + * ID and PI unit of the processor to which the interrupt will be * + * sent. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ibia1_u { + bdrkreg_t ii_ibia1_regval; + struct { + bdrkreg_t i_pi_id : 1; + bdrkreg_t i_node_id : 8; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_level : 7; + bdrkreg_t i_rsvd : 41; + } ii_ibia1_fld_s; +} ii_ibia1_u_t; + +#else + +typedef union ii_ibia1_u { + bdrkreg_t ii_ibia1_regval; + struct { + bdrkreg_t i_rsvd : 41; + bdrkreg_t i_level : 7; + bdrkreg_t i_rsvd_1 : 7; + bdrkreg_t i_node_id : 8; + bdrkreg_t i_pi_id : 1; + } ii_ibia1_fld_s; +} ii_ibia1_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register defines the resources that feed information into * + * the two performance counters located in the IO Performance * + * Profiling Register. There are 17 different quantities that can be * + * measured. Given these 17 different options, the two performance * + * counters have 15 of them in common; menu selections 0 through 0xE * + * are identical for each performance counter. As for the other two * + * options, one is available from one performance counter and the * + * other is available from the other performance counter. Hence, the * + * II supports all 17*16=272 possible combinations of quantities to * + * measure. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ipcr_u { + bdrkreg_t ii_ipcr_regval; + struct { + bdrkreg_t i_ippr0_c : 4; + bdrkreg_t i_ippr1_c : 4; + bdrkreg_t i_icct : 8; + bdrkreg_t i_rsvd : 48; + } ii_ipcr_fld_s; +} ii_ipcr_u_t; + +#else + +typedef union ii_ipcr_u { + bdrkreg_t ii_ipcr_regval; + struct { + bdrkreg_t i_rsvd : 48; + bdrkreg_t i_icct : 8; + bdrkreg_t i_ippr1_c : 4; + bdrkreg_t i_ippr0_c : 4; + } ii_ipcr_fld_s; +} ii_ipcr_u_t; + +#endif + + + + +/************************************************************************ + * * + * * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ii_ippr_u { + bdrkreg_t ii_ippr_regval; + struct { + bdrkreg_t i_ippr0 : 32; + bdrkreg_t i_ippr1 : 32; + } ii_ippr_fld_s; +} ii_ippr_u_t; + +#else + +typedef union ii_ippr_u { + bdrkreg_t ii_ippr_regval; + struct { + bdrkreg_t i_ippr1 : 32; + bdrkreg_t i_ippr0 : 32; + } ii_ippr_fld_s; +} ii_ippr_u_t; + +#endif + + + + + + +#endif /* _LANGUAGE_C */ + +/************************************************************************ + * * + * The following defines which were not formed into structures are * + * probably indentical to another register, and the name of the * + * register is provided against each of these registers. This * + * information needs to be checked carefully * + * * + * IIO_ICRB1_A IIO_ICRB0_A * + * IIO_ICRB1_B IIO_ICRB0_B * + * IIO_ICRB1_C IIO_ICRB0_C * + * IIO_ICRB1_D IIO_ICRB0_D * + * IIO_ICRB2_A IIO_ICRB0_A * + * IIO_ICRB2_B IIO_ICRB0_B * + * IIO_ICRB2_C IIO_ICRB0_C * + * IIO_ICRB2_D IIO_ICRB0_D * + * IIO_ICRB3_A IIO_ICRB0_A * + * IIO_ICRB3_B IIO_ICRB0_B * + * IIO_ICRB3_C IIO_ICRB0_C * + * IIO_ICRB3_D IIO_ICRB0_D * + * IIO_ICRB4_A IIO_ICRB0_A * + * IIO_ICRB4_B IIO_ICRB0_B * + * IIO_ICRB4_C IIO_ICRB0_C * + * IIO_ICRB4_D IIO_ICRB0_D * + * IIO_ICRB5_A IIO_ICRB0_A * + * IIO_ICRB5_B IIO_ICRB0_B * + * IIO_ICRB5_C IIO_ICRB0_C * + * IIO_ICRB5_D IIO_ICRB0_D * + * IIO_ICRB6_A IIO_ICRB0_A * + * IIO_ICRB6_B IIO_ICRB0_B * + * IIO_ICRB6_C IIO_ICRB0_C * + * IIO_ICRB6_D IIO_ICRB0_D * + * IIO_ICRB7_A IIO_ICRB0_A * + * IIO_ICRB7_B IIO_ICRB0_B * + * IIO_ICRB7_C IIO_ICRB0_C * + * IIO_ICRB7_D IIO_ICRB0_D * + * IIO_ICRB8_A IIO_ICRB0_A * + * IIO_ICRB8_B IIO_ICRB0_B * + * IIO_ICRB8_C IIO_ICRB0_C * + * IIO_ICRB8_D IIO_ICRB0_D * + * IIO_ICRB9_A IIO_ICRB0_A * + * IIO_ICRB9_B IIO_ICRB0_B * + * IIO_ICRB9_C IIO_ICRB0_C * + * IIO_ICRB9_D IIO_ICRB0_D * + * IIO_ICRBA_A IIO_ICRB0_A * + * IIO_ICRBA_B IIO_ICRB0_B * + * IIO_ICRBA_C IIO_ICRB0_C * + * IIO_ICRBA_D IIO_ICRB0_D * + * IIO_ICRBB_A IIO_ICRB0_A * + * IIO_ICRBB_B IIO_ICRB0_B * + * IIO_ICRBB_C IIO_ICRB0_C * + * IIO_ICRBB_D IIO_ICRB0_D * + * IIO_ICRBC_A IIO_ICRB0_A * + * IIO_ICRBC_B IIO_ICRB0_B * + * IIO_ICRBC_C IIO_ICRB0_C * + * IIO_ICRBC_D IIO_ICRB0_D * + * IIO_ICRBD_A IIO_ICRB0_A * + * IIO_ICRBD_B IIO_ICRB0_B * + * IIO_ICRBD_C IIO_ICRB0_C * + * IIO_ICRBD_D IIO_ICRB0_D * + * IIO_ICRBE_A IIO_ICRB0_A * + * IIO_ICRBE_B IIO_ICRB0_B * + * IIO_ICRBE_C IIO_ICRB0_C * + * IIO_ICRBE_D IIO_ICRB0_D * + * * + ************************************************************************/ + + +/************************************************************************ + * * + * MAKE ALL ADDITIONS AFTER THIS LINE * + * * + ************************************************************************/ + + + + + +#endif /* _ASM_SN_SN1_HUBIO_H */ diff --git a/include/asm-ia64/sn/sn1/hubio_next.h b/include/asm-ia64/sn/sn1/hubio_next.h new file mode 100644 index 000000000..52c0eab54 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubio_next.h @@ -0,0 +1,714 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBIO_NEXT_H +#define _ASM_SN_SN1_HUBIO_NEXT_H + +/* + * Slightly friendlier names for some common registers. + */ +#define IIO_WIDGET IIO_WID /* Widget identification */ +#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ +#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ +#define IIO_PROTECT IIO_ILAPR /* IO interface protection */ +#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ +#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ +#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ +#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ +#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ +#define IIO_LLP_LOG IIO_ILLR /* LLP log */ +#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ +#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ +#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ +#define IIO_IGFX_0 IIO_IGFX0 +#define IIO_IGFX_1 IIO_IGFX1 +#define IIO_IBCT_0 IIO_IBCT0 +#define IIO_IBCT_1 IIO_IBCT1 +#define IIO_IBLS_0 IIO_IBLS0 +#define IIO_IBLS_1 IIO_IBLS1 +#define IIO_IBSA_0 IIO_IBSA0 +#define IIO_IBSA_1 IIO_IBSA1 +#define IIO_IBDA_0 IIO_IBDA0 +#define IIO_IBDA_1 IIO_IBDA1 +#define IIO_IBNA_0 IIO_IBNA0 +#define IIO_IBNA_1 IIO_IBNA1 +#define IIO_IBIA_0 IIO_IBIA0 +#define IIO_IBIA_1 IIO_IBIA1 +#define IIO_IOPRB_0 IIO_IPRB0 +#define IIO_PRTE_0 IIO_IPRTE0 /* PIO Read address table entry 0 */ +#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x))) + +#define IIO_LLP_CSR_IS_UP 0x00002000 +#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 +#define IIO_LLP_CSR_LLP_STAT_SHFT 12 + +#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */ +#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ + +/* key to IIO_PROTECT_OVRRD */ +#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ + +/* BTE register names */ +#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ +#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ +#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ +#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ +#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ +#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ +#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ +#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */ + +/* BTE register offsets from base */ +#define BTEOFF_STAT 0 +#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) +#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) +#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) +#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) +#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) + + +/* names used in hub_diags.c; carried over from SN0 */ +#define IIO_BASE_BTE0 IIO_IBLS_0 +#define IIO_BASE_BTE1 IIO_IBLS_1 +#if 0 +#define IIO_BASE IIO_WID +#define IIO_BASE_PERF IIO_IPCR /* IO Performance Control */ +#define IIO_PERF_CNT IIO_IPPR /* IO Performance Profiling */ +#endif + + +/* GFX Flow Control Node/Widget Register */ +#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ +#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1) +#define IIO_IGFX_W_NUM_SHIFT 0 +#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */ +#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1) +#define IIO_IGFX_PI_NUM_SHIFT 4 +#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */ +#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1) +#define IIO_IGFX_N_NUM_SHIFT 5 +#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */ +#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1) +#define IIO_IGFX_P_NUM_SHIFT 16 +#define IIO_IGFX_INIT(widget, pi, node, cpu) (\ + (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ + (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \ + (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ + (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) + + +/* Scratch registers (all bits available) */ +#define IIO_SCRATCH_REG0 IIO_ISCR0 +#define IIO_SCRATCH_REG1 IIO_ISCR1 +#define IIO_SCRATCH_MASK 0xffffffffffffffff + +#define IIO_SCRATCH_BIT0_0 0x0000000000000001 +#define IIO_SCRATCH_BIT0_1 0x0000000000000002 +#define IIO_SCRATCH_BIT0_2 0x0000000000000004 +#define IIO_SCRATCH_BIT0_3 0x0000000000000008 +#define IIO_SCRATCH_BIT0_4 0x0000000000000010 +#define IIO_SCRATCH_BIT0_5 0x0000000000000020 +#define IIO_SCRATCH_BIT0_6 0x0000000000000040 +#define IIO_SCRATCH_BIT0_7 0x0000000000000080 +#define IIO_SCRATCH_BIT0_8 0x0000000000000100 +#define IIO_SCRATCH_BIT0_9 0x0000000000000200 +#define IIO_SCRATCH_BIT0_A 0x0000000000000400 + +#define IIO_SCRATCH_BIT1_0 0x0000000000000001 +#define IIO_SCRATCH_BIT1_1 0x0000000000000002 +/* IO Translation Table Entries */ +#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ + /* Hw manuals number them 1..7! */ +/* + * IIO_IMEM Register fields. + */ +#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */ +#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */ +#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */ + +/* + * As a permanent workaround for a bug in the PI side of the hub, we've + * redefined big window 7 as small window 0. + XXX does this still apply for SN1?? + */ +#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1 + +/* + * Use the top big window as a surrogate for the first small window + */ +#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW + +#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ + +#define ILCSR_WARM_RESET 0x100 + +/* + * CRB manipulation macros + * The CRB macros are slightly complicated, since there are up to + * four registers associated with each CRB entry. + */ +#define IIO_NUM_CRBS 15 /* Number of CRBs */ +#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */ +#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ +#define IIO_ICRB_OFFSET 8 +#define IIO_ICRB_0 IIO_ICRB0_A +#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ +/* XXX - This is now tuneable: + #define IIO_FIRST_PC_ENTRY 12 + */ + +#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x))) +#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) +#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET) +#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) + +#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) + +/* + * values for "ecode" field + */ +#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ +#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ +#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access + * e.g. WINV to a Read only line. */ +#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ +#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ +#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ +#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ +#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ + +/* + * Number of credits Hub widget has while sending req/response to + * xbow. + * Value of 3 is required by Xbow 1.1 + * We may be able to increase this to 4 with Xbow 1.2. + */ +#define HUBII_XBOW_CREDIT 3 +#define HUBII_XBOW_REV2_CREDIT 4 + +/************************************************************************* + + Some of the IIO field masks and shifts are defined here. + This is in order to maintain compatibility in SN0 and SN1 code + +**************************************************************************/ + +/* + * ICMR register fields + * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not + * present in Bedrock) + */ + +#define IIO_ICMR_CRB_VLD_SHFT 20 +#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) + +#define IIO_ICMR_FC_CNT_SHFT 16 +#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) + +#define IIO_ICMR_C_CNT_SHFT 4 +#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) + +#define IIO_ICMR_PRECISE (1UL << 52) +#define IIO_ICMR_CLR_RPPD (1UL << 13) +#define IIO_ICMR_CLR_RQPD (1UL << 12) + +/* + * IIO PIO Deallocation register field masks : (IIO_IPDR) + XXX present but not needed in bedrock? See the manual. + */ +#define IIO_IPDR_PND (1 << 4) + +/* + * IIO CRB deallocation register field masks: (IIO_ICDR) + */ +#define IIO_ICDR_PND (1 << 4) + +/* + * IO BTE Length/Status (IIO_IBLS) register bit field definitions + */ +#define IBLS_BUSY (0x1 << 20) +#define IBLS_ERROR_SHFT 16 +#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT) +#define IBLS_LENGTH_MASK 0xffff + +/* + * IO BTE Control/Terminate register (IBCT) register bit field definitions + */ +#define IBCT_POISON (0x1 << 8) +#define IBCT_NOTIFY (0x1 << 4) +#define IBCT_ZFIL_MODE (0x1 << 0) + +/* + * IO Error Clear register bit field definitions + */ +#define IECLR_PI1_FWD_INT (1 << 31) /* clear PI1_FORWARD_INT in iidsr */ +#define IECLR_PI0_FWD_INT (1 << 30) /* clear PI0_FORWARD_INT in iidsr */ +#define IECLR_SPUR_RD_HDR (1 << 29) /* clear valid bit in ixss reg */ +#define IECLR_BTE1 (1 << 18) /* clear bte error 1 */ +#define IECLR_BTE0 (1 << 17) /* clear bte error 0 */ +#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */ +#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */ +#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */ +#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */ +#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */ +#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */ +#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */ +#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */ +#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */ +#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */ + +/* + * IIO CRB control register Fields: IIO_ICCR + */ +#define IIO_ICCR_PENDING (0x10000) +#define IIO_ICCR_CMD_MASK (0xFF) +#define IIO_ICCR_CMD_SHFT (7) +#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ +#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ +#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ +#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory + * via a WB + */ +#define IIO_ICCR_CMD_FLUSH (0x800) + +/* + * + * CRB Register description. + * + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * + * Many of the fields in CRB are status bits used by hardware + * for implementation of the protocol. It's very dangerous to + * mess around with the CRB registers. + * + * It's OK to read the CRB registers and try to make sense out of the + * fields in CRB. + * + * Updating CRB requires all activities in Hub IIO to be quiesced. + * otherwise, a write to CRB could corrupt other CRB entries. + * CRBs are here only as a back door peek to hub IIO's status. + * Quiescing implies no dmas no PIOs + * either directly from the cpu or from sn0net. + * this is not something that can be done easily. So, AVOID updating + * CRBs. + */ + +#ifdef _LANGUAGE_C + +/* + * Easy access macros for CRBs, all 4 registers (A-D) + */ +typedef ii_icrb0_a_u_t icrba_t; /* what it was called on SN0/hub */ +#define a_error ii_icrb0_a_fld_s.ia_error +#define a_ecode ii_icrb0_a_fld_s.ia_errcode +#define a_lnetuce ii_icrb0_a_fld_s.ia_ln_uce +#define a_mark ii_icrb0_a_fld_s.ia_mark +#define a_xerr ii_icrb0_a_fld_s.ia_xt_err +#define a_sidn ii_icrb0_a_fld_s.ia_sidn +#define a_tnum ii_icrb0_a_fld_s.ia_tnum +#define a_addr ii_icrb0_a_fld_s.ia_addr +#define a_valid ii_icrb0_a_fld_s.ia_vld +#define a_iow ii_icrb0_a_fld_s.ia_iow +#define a_regvalue ii_icrb0_a_regval + +typedef ii_icrb0_b_u_t icrbb_t; +#define b_btenum ii_icrb0_b_fld_s.ib_bte_num +#define b_cohtrans ii_icrb0_b_fld_s.ib_ct +#define b_xtsize ii_icrb0_b_fld_s.ib_size +#define b_source ii_icrb0_b_fld_s.ib_source +#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype +#define b_imsg ii_icrb0_b_fld_s.ib_imsg +#define b_initiator ii_icrb0_b_fld_s.ib_init +#define b_regvalue ii_icrb0_b_regval + +typedef ii_icrb0_c_u_t icrbc_t; +#define c_pricnt ii_icrb0_c_fld_s.ic_pr_cnt +#define c_pripsc ii_icrb0_c_fld_s.ic_pr_psc +#define c_bteop ii_icrb0_c_fld_s.ic_bte_op +#define c_bteaddr ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ +#define c_benable ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ +#define c_suppl ii_icrb0_c_fld_s.ic_suppl +#define c_barrop ii_icrb0_c_fld_s.ic_bo +#define c_doresp ii_icrb0_c_fld_s.ic_resprqd +#define c_gbr ii_icrb0_c_fld_s.ic_gbr +#define c_regvalue ii_icrb0_c_regval + +typedef ii_icrb0_d_u_t icrbd_t; +#define icrbd_ctxtvld ii_icrb0_d_fld_s.id_cvld +#define icrbd_toutvld ii_icrb0_d_fld_s.id_tvld +#define icrbd_context ii_icrb0_d_fld_s.id_context +#define d_regvalue ii_icrb0_d_regval + +#endif /* LANGUAGE_C */ + +/* Number of widgets supported by hub */ +#define HUB_NUM_WIDGET 9 +#define HUB_WIDGET_ID_MIN 0x8 +#define HUB_WIDGET_ID_MAX 0xf + +#define HUB_WIDGET_PART_NUM 0xc110 +#define MAX_HUBS_PER_XBOW 2 + +#ifdef _LANGUAGE_C +/* A few more #defines for backwards compatibility */ +#define iprb_t ii_iprb0_u_t +#define iprb_regval ii_iprb0_regval +#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt +#define iprb_error ii_iprb0_fld_s.i_error +#define iprb_ff ii_iprb0_fld_s.i_f +#define iprb_mode ii_iprb0_fld_s.i_m +#define iprb_bnakctr ii_iprb0_fld_s.i_nb +#define iprb_anakctr ii_iprb0_fld_s.i_na +#define iprb_xtalkctr ii_iprb0_fld_s.i_c +#endif + +#define LNK_STAT_WORKING 0x2 + +#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ +#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ +#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */ +#define IIO_WSTAT_TXRETRY_SHFT (16) +#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ + IIO_WSTAT_TXRETRY_MASK) + +/* Number of II perf. counters we can multiplex at once */ + +#define IO_PERF_SETS 32 + +#ifdef BRINGUP +#if __KERNEL__ +#if _LANGUAGE_C +/* XXX moved over from SN/SN0/hubio.h -- each should be checked for SN1 */ +#include <asm/sn/alenlist.h> +#include <asm/sn/dmamap.h> +#include <asm/sn/iobus.h> +#include <asm/sn/xtalk/xtalk.h> + +/* Bit for the widget in inbound access register */ +#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) +/* Bit for the widget in outbound access register */ +#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) + +/* NOTE: The following define assumes that we are going to get + * widget numbers from 8 thru F and the device numbers within + * widget from 0 thru 7. + */ +#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) + +/* IO Interrupt Destination Register */ +#define IIO_IIDSR_SENT_SHIFT 28 +#define IIO_IIDSR_SENT_MASK 0x10000000 +#define IIO_IIDSR_ENB_SHIFT 24 +#define IIO_IIDSR_ENB_MASK 0x01000000 +#define IIO_IIDSR_NODE_SHIFT 8 +#define IIO_IIDSR_NODE_MASK 0x0000ff00 +#define IIO_IIDSR_PI_ID_SHIFT 8 +#define IIO_IIDSR_PI_ID_MASK 0x00000010 +#define IIO_IIDSR_LVL_SHIFT 0 +#define IIO_IIDSR_LVL_MASK 0x0000007f + +/* Xtalk timeout threshhold register (IIO_IXTT) */ +#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ +#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) +#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ +#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) +#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ +#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) + +/* + * The IO LLP control status register and widget control register + */ + +#ifdef LITTLE_ENDIAN + +typedef union hubii_wcr_u { + uint64_t wcr_reg_value; + struct { + uint64_t wcr_widget_id: 4, /* LLP crossbar credit */ + wcr_tag_mode: 1, /* Tag mode */ + wcr_rsvd1: 8, /* Reserved */ + wcr_xbar_crd: 3, /* LLP crossbar credit */ + wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ + wcr_dir_con: 1, /* widget direct connect */ + wcr_e_thresh: 5, /* elasticity threshold */ + wcr_rsvd: 41; /* unused */ + } wcr_fields_s; +} hubii_wcr_t; + +#else + +typedef union hubii_wcr_u { + uint64_t wcr_reg_value; + struct { + uint64_t wcr_rsvd: 41, /* unused */ + wcr_e_thresh: 5, /* elasticity threshold */ + wcr_dir_con: 1, /* widget direct connect */ + wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ + wcr_xbar_crd: 3, /* LLP crossbar credit */ + wcr_rsvd1: 8, /* Reserved */ + wcr_tag_mode: 1, /* Tag mode */ + wcr_widget_id: 4; /* LLP crossbar credit */ + } wcr_fields_s; +} hubii_wcr_t; + +#endif + +#define iwcr_dir_con wcr_fields_s.wcr_dir_con + +/* The structures below are defined to extract and modify the ii +performance registers */ + +/* io_perf_sel allows the caller to specify what tests will be + performed */ +#ifdef LITTLE_ENDIAN + +typedef union io_perf_sel { + uint64_t perf_sel_reg; + struct { + uint64_t perf_ippr0 : 4, + perf_ippr1 : 4, + perf_icct : 8, + perf_rsvd : 48; + } perf_sel_bits; +} io_perf_sel_t; + +#else + +typedef union io_perf_sel { + uint64_t perf_sel_reg; + struct { + uint64_t perf_rsvd : 48, + perf_icct : 8, + perf_ippr1 : 4, + perf_ippr0 : 4; + } perf_sel_bits; +} io_perf_sel_t; + +#endif + +/* io_perf_cnt is to extract the count from the hub registers. Due to + hardware problems there is only one counter, not two. */ + +#ifdef LITTLE_ENDIAN + +typedef union io_perf_cnt { + uint64_t perf_cnt; + struct { + uint64_t perf_cnt : 20, + perf_rsvd2 : 12, + perf_rsvd1 : 32; + } perf_cnt_bits; + +} io_perf_cnt_t; + +#else + +typedef union io_perf_cnt { + uint64_t perf_cnt; + struct { + uint64_t perf_rsvd1 : 32, + perf_rsvd2 : 12, + perf_cnt : 20; + } perf_cnt_bits; + +} io_perf_cnt_t; + +#endif + +#ifdef LITTLE_ENDIAN + +typedef union iprte_a { + bdrkreg_t entry; + struct { + bdrkreg_t i_rsvd_1 : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_init : 3; + bdrkreg_t i_source : 8; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_widget : 4; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_vld : 1; + } iprte_fields; +} iprte_a_t; + +#else + +typedef union iprte_a { + bdrkreg_t entry; + struct { + bdrkreg_t i_vld : 1; + bdrkreg_t i_to_cnt : 5; + bdrkreg_t i_widget : 4; + bdrkreg_t i_rsvd : 2; + bdrkreg_t i_source : 8; + bdrkreg_t i_init : 3; + bdrkreg_t i_addr : 38; + bdrkreg_t i_rsvd_1 : 3; + } iprte_fields; +} iprte_a_t; + +#endif + +/* PIO MANAGEMENT */ +typedef struct hub_piomap_s *hub_piomap_t; + +extern hub_piomap_t +hub_piomap_alloc(devfs_handle_t dev, /* set up mapping for this device */ + device_desc_t dev_desc, /* device descriptor */ + iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ + size_t byte_count, + size_t byte_count_max, /* maximum size of a mapping */ + unsigned flags); /* defined in sys/pio.h */ + +extern void hub_piomap_free(hub_piomap_t hub_piomap); + +extern caddr_t +hub_piomap_addr(hub_piomap_t hub_piomap, /* mapping resources */ + iopaddr_t xtalk_addr, /* map for this xtalk addr */ + size_t byte_count); /* map this many bytes */ + +extern void +hub_piomap_done(hub_piomap_t hub_piomap); + +extern caddr_t +hub_piotrans_addr( devfs_handle_t dev, /* translate to this device */ + device_desc_t dev_desc, /* device descriptor */ + iopaddr_t xtalk_addr, /* Crosstalk address */ + size_t byte_count, /* map this many bytes */ + unsigned flags); /* (currently unused) */ + +/* DMA MANAGEMENT */ +typedef struct hub_dmamap_s *hub_dmamap_t; + +extern hub_dmamap_t +hub_dmamap_alloc( devfs_handle_t dev, /* set up mappings for dev */ + device_desc_t dev_desc, /* device descriptor */ + size_t byte_count_max, /* max size of a mapping */ + unsigned flags); /* defined in dma.h */ + +extern void +hub_dmamap_free(hub_dmamap_t dmamap); + +extern iopaddr_t +hub_dmamap_addr( hub_dmamap_t dmamap, /* use mapping resources */ + paddr_t paddr, /* map for this address */ + size_t byte_count); /* map this many bytes */ + +extern alenlist_t +hub_dmamap_list( hub_dmamap_t dmamap, /* use mapping resources */ + alenlist_t alenlist, /* map this Addr/Length List */ + unsigned flags); + +extern void +hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */ + +extern iopaddr_t +hub_dmatrans_addr( devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + paddr_t paddr, /* system physical address */ + size_t byte_count, /* length */ + unsigned flags); /* defined in dma.h */ + +extern alenlist_t +hub_dmatrans_list( devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + alenlist_t palenlist, /* system addr/length list */ + unsigned flags); /* defined in dma.h */ + +extern void +hub_dmamap_drain( hub_dmamap_t map); + +extern void +hub_dmaaddr_drain( devfs_handle_t vhdl, + paddr_t addr, + size_t bytes); + +extern void +hub_dmalist_drain( devfs_handle_t vhdl, + alenlist_t list); + + +/* INTERRUPT MANAGEMENT */ +typedef struct hub_intr_s *hub_intr_t; + +extern hub_intr_t +hub_intr_alloc( devfs_handle_t dev, /* which device */ + device_desc_t dev_desc, /* device descriptor */ + devfs_handle_t owner_dev); /* owner of this interrupt */ + +extern void +hub_intr_free(hub_intr_t intr_hdl); + +extern int +hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ + intr_func_t intr_func, /* xtalk intr handler */ + void *intr_arg, /* arg to intr handler */ + xtalk_intr_setfunc_t setfunc, + /* func to set intr hw */ + void *setfunc_arg, /* arg to setfunc */ + void *thread); /* intr thread to use */ + +extern void +hub_intr_disconnect(hub_intr_t intr_hdl); + +extern devfs_handle_t +hub_intr_cpu_get(hub_intr_t intr_hdl); + +/* CONFIGURATION MANAGEMENT */ + +extern void +hub_provider_startup(devfs_handle_t hub); + +extern void +hub_provider_shutdown(devfs_handle_t hub); + +#define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */ +#define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */ + +/* Flags that make sense to hub_widget_flags_set */ +#define HUB_WIDGET_FLAGS ( \ + HUB_PIO_CONVEYOR | \ + HUB_PIO_FIRE_N_FORGET \ + ) + + +typedef int hub_widget_flags_t; + +/* Set the PIO mode for a widget. These two functions perform the + * same operation, but hub_device_flags_set() takes a hardware graph + * vertex while hub_widget_flags_set() takes a nasid and widget + * number. In most cases, hub_device_flags_set() should be used. + */ +extern int hub_widget_flags_set(nasid_t nasid, + xwidgetnum_t widget_num, + hub_widget_flags_t flags); + +/* Depending on the flags set take the appropriate actions */ +extern int hub_device_flags_set(devfs_handle_t widget_dev, + hub_widget_flags_t flags); + + +/* Error Handling. */ +extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *); +extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t, + int, paddr_t, caddr_t, ioerror_mode_t); +extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t); +extern int hub_error_devenable(devfs_handle_t, int, int); +extern void hub_widgetdev_enable(devfs_handle_t, int); +extern void hub_widgetdev_shutdown(devfs_handle_t, int); +extern int hub_dma_enabled(devfs_handle_t); + +#endif /* _LANGUAGE_C */ +#endif /* _KERNEL */ +#endif /* BRINGUP */ +#endif /* _ASM_SN_SN1_HUBIO_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hublb.h b/include/asm-ia64/sn/sn1/hublb.h new file mode 100644 index 000000000..692eeab44 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hublb.h @@ -0,0 +1,1608 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +/************************************************************************ + * * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * + * * + * This file is created by an automated script. Any (minimal) changes * + * made manually to this file should be made with care. * + * * + * MAKE ALL ADDITIONS TO THE END OF THIS FILE * + * * + ************************************************************************/ + + +#ifndef _ASM_SN_SN1_HUBLB_H +#define _ASM_SN_SN1_HUBLB_H + + +#define LB_REV_ID 0x00600000 /* + * Bedrock Revision + * and ID + */ + + + +#define LB_CPU_PERMISSION 0x00604000 /* + * CPU PIO access + * permission bits + */ + + + +#define LB_CPU_PERM_OVRRD 0x00604008 /* + * CPU PIO access + * permission bit + * override + */ + + + +#define LB_IO_PERMISSION 0x00604010 /* + * IO PIO access + * permission bits + */ + + + +#define LB_SOFT_RESET 0x00604018 /* + * Soft reset the + * Bedrock chip + */ + + + +#define LB_REGION_PRESENT 0x00604020 /* + * Regions Present for + * Invalidates + */ + + + +#define LB_NODES_ABSENT 0x00604028 /* + * Nodes Absent for + * Invalidates + */ + + + +#define LB_MICROLAN_CTL 0x00604030 /* + * Microlan Control + * (NIC) + */ + + + +#define LB_ERROR_BITS 0x00604040 /* + * Local Block error + * bits + */ + + + +#define LB_ERROR_MASK_CLR 0x00604048 /* + * Bit mask write to + * clear error bits + */ + + + +#define LB_ERROR_HDR1 0x00604050 /* + * Source, Suppl and + * Cmd fields + */ + + + +#define LB_ERROR_HDR2 0x00604058 /* + * Address field from + * first error + */ + + + +#define LB_ERROR_DATA 0x00604060 /* + * Data flit (if any) + * from first error + */ + + + +#define LB_DEBUG_SELECT 0x00604100 /* + * Choice of debug + * signals from chip + */ + + + +#define LB_DEBUG_PINS 0x00604108 /* + * Value on the chip's + * debug pins + */ + + + +#define LB_RT_LOCAL_CTRL 0x00604200 /* + * Local generation of + * real-time clock + */ + + + +#define LB_RT_FILTER_CTRL 0x00604208 /* + * Control of + * filtering of global + * clock + */ + + + +#define LB_SCRATCH_REG0 0x00608000 /* Scratch Register 0 */ + + + +#define LB_SCRATCH_REG1 0x00608008 /* Scratch Register 1 */ + + + +#define LB_SCRATCH_REG2 0x00608010 /* Scratch Register 2 */ + + + +#define LB_SCRATCH_REG3 0x00608018 /* Scratch Register 3 */ + + + +#define LB_SCRATCH_REG4 0x00608020 /* Scratch Register 4 */ + + + +#define LB_SCRATCH_REG0_WZ 0x00608040 /* + * Scratch Register 0 + * (WZ alias) + */ + + + +#define LB_SCRATCH_REG1_WZ 0x00608048 /* + * Scratch Register 1 + * (WZ alias) + */ + + + +#define LB_SCRATCH_REG2_WZ 0x00608050 /* + * Scratch Register 2 + * (WZ alias) + */ + + + +#define LB_SCRATCH_REG3_RZ 0x00608058 /* + * Scratch Register 3 + * (RZ alias) + */ + + + +#define LB_SCRATCH_REG4_RZ 0x00608060 /* + * Scratch Register 4 + * (RZ alias) + */ + + + +#define LB_VECTOR_PARMS 0x0060C000 /* + * Vector PIO + * parameters + */ + + + +#define LB_VECTOR_ROUTE 0x0060C008 /* + * Vector PIO Vector + * Route + */ + + + +#define LB_VECTOR_DATA 0x0060C010 /* + * Vector PIO Write + * Data + */ + + + +#define LB_VECTOR_STATUS 0x0060C020 /* + * Vector PIO Return + * Status + */ + + + +#define LB_VECTOR_RETURN 0x0060C028 /* + * Vector PIO Return + * Route + */ + + + +#define LB_VECTOR_READ_DATA 0x0060C030 /* + * Vector PIO Read + * Data + */ + + + +#define LB_VECTOR_STATUS_CLEAR 0x0060C038 /* + * Clear Vector PIO + * Return Status + */ + + + + + +#ifdef _LANGUAGE_C + +/************************************************************************ + * * + * Description: This register contains information that allows * + * exploratory software to probe for chip type. This is also the * + * register that sets this node's ID and the size of each region * + * (which affects the maximum possible system size). IBM assigns the * + * values for the REVISION, PART_NUMBER and MANUFACTURER fields, in * + * accordance with the IEEE 1149.1 standard; SGI is not at liberty to * + * unilaterally change the values of these fields. * + * . * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_rev_id_u { + bdrkreg_t lb_rev_id_regval; + struct { + bdrkreg_t ri_reserved_2 : 1; + bdrkreg_t ri_manufacturer : 11; + bdrkreg_t ri_part_number : 16; + bdrkreg_t ri_revision : 4; + bdrkreg_t ri_node_id : 8; + bdrkreg_t ri_reserved_1 : 6; + bdrkreg_t ri_region_size : 2; + bdrkreg_t ri_reserved : 16; + } lb_rev_id_fld_s; +} lb_rev_id_u_t; + +#else + +typedef union lb_rev_id_u { + bdrkreg_t lb_rev_id_regval; + struct { + bdrkreg_t ri_reserved : 16; + bdrkreg_t ri_region_size : 2; + bdrkreg_t ri_reserved_1 : 6; + bdrkreg_t ri_node_id : 8; + bdrkreg_t ri_revision : 4; + bdrkreg_t ri_part_number : 16; + bdrkreg_t ri_manufacturer : 11; + bdrkreg_t ri_reserved_2 : 1; + } lb_rev_id_fld_s; +} lb_rev_id_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the PI-access-rights bit-vector for the * + * LB, NI, XB and MD portions of the Bedrock local register space. If * + * a bit in the bit-vector is set, the region corresponding to that * + * bit has read/write permission on the LB, NI, XB and MD local * + * registers. If the bit is clear, that region has no write access to * + * the local registers and no read access if the read will cause any * + * state change. If a write or a read with side effects is attempted * + * by a PI in a region for which access is restricted, the LB will * + * not perform the operation and will send back a reply which * + * indicates an error. * + * * + ************************************************************************/ + + + + +typedef union lb_cpu_permission_u { + bdrkreg_t lb_cpu_permission_regval; + struct { + bdrkreg_t cp_cpu_access : 64; + } lb_cpu_permission_fld_s; +} lb_cpu_permission_u_t; + + + + +/************************************************************************ + * * + * A write to this register of the 64-bit value "SGIrules" will * + * cause the bit in the LB_CPU_PROTECT register corresponding to the * + * region of the requester to be set. * + * * + ************************************************************************/ + + + + +typedef union lb_cpu_perm_ovrrd_u { + bdrkreg_t lb_cpu_perm_ovrrd_regval; + struct { + bdrkreg_t cpo_cpu_perm_ovr : 64; + } lb_cpu_perm_ovrrd_fld_s; +} lb_cpu_perm_ovrrd_u_t; + + + + +/************************************************************************ + * * + * This register contains the II-access-rights bit-vector for the * + * LB, NI, XB and MD portions of the Bedrock local register space. If * + * a bit in the bit-vector is set, the region corresponding to that * + * bit has read/write permission on the LB, NI, XB and MD local * + * registers. If the bit is clear, then that region has no write * + * access to the local registers and no read access if the read * + * results in any state change. If a write or a read with side * + * effects is attempted by an II in a region for which access is * + * restricted, the LB will not perform the operation and will send * + * back a reply which indicates an error. * + * * + ************************************************************************/ + + + + +typedef union lb_io_permission_u { + bdrkreg_t lb_io_permission_regval; + struct { + bdrkreg_t ip_io_permission : 64; + } lb_io_permission_fld_s; +} lb_io_permission_u_t; + + + + +/************************************************************************ + * * + * A write to this bit resets the Bedrock chip with a soft reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_soft_reset_u { + bdrkreg_t lb_soft_reset_regval; + struct { + bdrkreg_t sr_soft_reset : 1; + bdrkreg_t sr_reserved : 63; + } lb_soft_reset_fld_s; +} lb_soft_reset_u_t; + +#else + +typedef union lb_soft_reset_u { + bdrkreg_t lb_soft_reset_regval; + struct { + bdrkreg_t sr_reserved : 63; + bdrkreg_t sr_soft_reset : 1; + } lb_soft_reset_fld_s; +} lb_soft_reset_u_t; + +#endif + + + +/************************************************************************ + * * + * This register indicates which regions are present and capable of * + * receiving an invalidate (INVAL) request. The LB samples this * + * register at the start of processing each LINVAL. When an LINVAL * + * indicates that a particular PI unit might hold a shared copy of a * + * cache block but this PI is in a region which is not present (i.e., * + * its bit in LB_REGION_PRESENT is clear), then the LB sends an IVACK * + * reply packet on behalf of this PI. The REGION_SIZE field in the * + * LB_REV_ID register determines the number of nodes per region (and * + * hence, the number of PI units which share a common bit in the * + * LB_REGION_PRESENT register). * + * * + ************************************************************************/ + + + + +typedef union lb_region_present_u { + bdrkreg_t lb_region_present_regval; + struct { + bdrkreg_t rp_present_bits : 64; + } lb_region_present_fld_s; +} lb_region_present_u_t; + + + + +/************************************************************************ + * * + * Description: This register indicates which nodes are absent and * + * not capable of receiving an invalidate (INVAL) request. The LB * + * samples this register at the start of processing each LINVAL. When * + * an LINVAL indicates that a particular PI unit might hold a shared * + * copy of a cache block but this PI unit's node is not present * + * (i.e., its node ID is listed in the LB_NODES_ABSENT register), * + * then the LB sends an IVACK reply packet on behalf of this PI. * + * * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_nodes_absent_u { + bdrkreg_t lb_nodes_absent_regval; + struct { + bdrkreg_t na_node_0 : 8; + bdrkreg_t na_reserved_3 : 7; + bdrkreg_t na_node_0_valid : 1; + bdrkreg_t na_node_1 : 8; + bdrkreg_t na_reserved_2 : 7; + bdrkreg_t na_node_1_valid : 1; + bdrkreg_t na_node_2 : 8; + bdrkreg_t na_reserved_1 : 7; + bdrkreg_t na_node_2_valid : 1; + bdrkreg_t na_node_3 : 8; + bdrkreg_t na_reserved : 7; + bdrkreg_t na_node_3_valid : 1; + } lb_nodes_absent_fld_s; +} lb_nodes_absent_u_t; + +#else + +typedef union lb_nodes_absent_u { + bdrkreg_t lb_nodes_absent_regval; + struct { + bdrkreg_t na_node_3_valid : 1; + bdrkreg_t na_reserved : 7; + bdrkreg_t na_node_3 : 8; + bdrkreg_t na_node_2_valid : 1; + bdrkreg_t na_reserved_1 : 7; + bdrkreg_t na_node_2 : 8; + bdrkreg_t na_node_1_valid : 1; + bdrkreg_t na_reserved_2 : 7; + bdrkreg_t na_node_1 : 8; + bdrkreg_t na_node_0_valid : 1; + bdrkreg_t na_reserved_3 : 7; + bdrkreg_t na_node_0 : 8; + } lb_nodes_absent_fld_s; +} lb_nodes_absent_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register provides access to the Number-In-a-Can add-only * + * serial PROM that is used to store node board serial number and * + * configuration information. (Refer to NIC datasheet Dallas 1990A * + * that is viewable at * + * URL::http://www.dalsemi.com/DocControl/PDFs/pdfindex.html). Data * + * comes from this interface LSB first. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_microlan_ctl_u { + bdrkreg_t lb_microlan_ctl_regval; + struct { + bdrkreg_t mc_rd_data : 1; + bdrkreg_t mc_done : 1; + bdrkreg_t mc_sample : 8; + bdrkreg_t mc_pulse : 10; + bdrkreg_t mc_clkdiv_phi0 : 7; + bdrkreg_t mc_clkdiv_phi1 : 7; + bdrkreg_t mc_reserved : 30; + } lb_microlan_ctl_fld_s; +} lb_microlan_ctl_u_t; + +#else + +typedef union lb_microlan_ctl_u { + bdrkreg_t lb_microlan_ctl_regval; + struct { + bdrkreg_t mc_reserved : 30; + bdrkreg_t mc_clkdiv_phi1 : 7; + bdrkreg_t mc_clkdiv_phi0 : 7; + bdrkreg_t mc_pulse : 10; + bdrkreg_t mc_sample : 8; + bdrkreg_t mc_done : 1; + bdrkreg_t mc_rd_data : 1; + } lb_microlan_ctl_fld_s; +} lb_microlan_ctl_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register contains the LB error status bits. * + * Whenever a particular type of error occurs, the LB sets its bit in * + * this register so that software will be aware that such an event * + * has happened. Reads from this register are non-destructive and the * + * contents of this register remain intact across reset operations. * + * Whenever any of these bits is set, the LB will assert its * + * interrupt request output signals that go to the PI units. * + * Software can simulate the occurrence of an error by first writing * + * appropriate values into the LB_ERROR_HDR1, LB_ERROR_HDR2 and * + * LB_ERROR_DATA registers, and then writing to the LB_ERROR_BITS * + * register to set the error bits in a particular way. Setting one or * + * more error bits will cause the LB to interrupt a processor and * + * invoke error-handling software. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_error_bits_u { + bdrkreg_t lb_error_bits_regval; + struct { + bdrkreg_t eb_rq_bad_cmd : 1; + bdrkreg_t eb_rp_bad_cmd : 1; + bdrkreg_t eb_rq_short : 1; + bdrkreg_t eb_rp_short : 1; + bdrkreg_t eb_rq_long : 1; + bdrkreg_t eb_rp_long : 1; + bdrkreg_t eb_rq_bad_data : 1; + bdrkreg_t eb_rp_bad_data : 1; + bdrkreg_t eb_rq_bad_addr : 1; + bdrkreg_t eb_rq_bad_linval : 1; + bdrkreg_t eb_gclk_drop : 1; + bdrkreg_t eb_reserved : 53; + } lb_error_bits_fld_s; +} lb_error_bits_u_t; + +#else + +typedef union lb_error_bits_u { + bdrkreg_t lb_error_bits_regval; + struct { + bdrkreg_t eb_reserved : 53; + bdrkreg_t eb_gclk_drop : 1; + bdrkreg_t eb_rq_bad_linval : 1; + bdrkreg_t eb_rq_bad_addr : 1; + bdrkreg_t eb_rp_bad_data : 1; + bdrkreg_t eb_rq_bad_data : 1; + bdrkreg_t eb_rp_long : 1; + bdrkreg_t eb_rq_long : 1; + bdrkreg_t eb_rp_short : 1; + bdrkreg_t eb_rq_short : 1; + bdrkreg_t eb_rp_bad_cmd : 1; + bdrkreg_t eb_rq_bad_cmd : 1; + } lb_error_bits_fld_s; +} lb_error_bits_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register lets software clear some of the bits in the * + * LB_ERROR_BITS register without affecting other bits. Essentially, * + * it provides bit mask functionality. When software writes to the * + * LB_ERROR_MASK_CLR register, the bits which are set in the data * + * value indicate which bits are to be cleared in LB_ERROR_BITS. If a * + * bit is clear in the data value written to the LB_ERROR_MASK_CLR * + * register, then its corresponding bit in the LB_ERROR_BITS register * + * is not affected. Hence, software can atomically clear any subset * + * of the error bits in the LB_ERROR_BITS register. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_error_mask_clr_u { + bdrkreg_t lb_error_mask_clr_regval; + struct { + bdrkreg_t emc_clr_rq_bad_cmd : 1; + bdrkreg_t emc_clr_rp_bad_cmd : 1; + bdrkreg_t emc_clr_rq_short : 1; + bdrkreg_t emc_clr_rp_short : 1; + bdrkreg_t emc_clr_rq_long : 1; + bdrkreg_t emc_clr_rp_long : 1; + bdrkreg_t emc_clr_rq_bad_data : 1; + bdrkreg_t emc_clr_rp_bad_data : 1; + bdrkreg_t emc_clr_rq_bad_addr : 1; + bdrkreg_t emc_clr_rq_bad_linval : 1; + bdrkreg_t emc_clr_gclk_drop : 1; + bdrkreg_t emc_reserved : 53; + } lb_error_mask_clr_fld_s; +} lb_error_mask_clr_u_t; + +#else + +typedef union lb_error_mask_clr_u { + bdrkreg_t lb_error_mask_clr_regval; + struct { + bdrkreg_t emc_reserved : 53; + bdrkreg_t emc_clr_gclk_drop : 1; + bdrkreg_t emc_clr_rq_bad_linval : 1; + bdrkreg_t emc_clr_rq_bad_addr : 1; + bdrkreg_t emc_clr_rp_bad_data : 1; + bdrkreg_t emc_clr_rq_bad_data : 1; + bdrkreg_t emc_clr_rp_long : 1; + bdrkreg_t emc_clr_rq_long : 1; + bdrkreg_t emc_clr_rp_short : 1; + bdrkreg_t emc_clr_rq_short : 1; + bdrkreg_t emc_clr_rp_bad_cmd : 1; + bdrkreg_t emc_clr_rq_bad_cmd : 1; + } lb_error_mask_clr_fld_s; +} lb_error_mask_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * If the LB detects an error when VALID==0 in the LB_ERROR_HDR1 * + * register, then it saves the contents of the offending packet's * + * header flit in the LB_ERROR_HDR1 and LB_ERROR_HDR2 registers, sets * + * the VALID bit in LB_ERROR_HDR1 and clears the OVERRUN bit in * + * LB_ERROR_HDR1 (and it will also set the corresponding bit in the * + * LB_ERROR_BITS register). The ERR_TYPE field indicates specifically * + * what kind of error occurred. Its encoding corresponds to the bit * + * positions in the LB_ERROR_BITS register (e.g., ERR_TYPE==5 * + * indicates a RP_LONG error). If an error (of any type except * + * GCLK_DROP) subsequently happens while VALID==1, then the LB sets * + * the OVERRUN bit in LB_ERROR_HDR1. This register is not relevant * + * when a GCLK_DROP error occurs; the LB does not even attempt to * + * change the ERR_TYPE, VALID or OVERRUN field when a GCLK_DROP error * + * happens. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_error_hdr1_u { + bdrkreg_t lb_error_hdr1_regval; + struct { + bdrkreg_t eh_command : 7; + bdrkreg_t eh_reserved_5 : 1; + bdrkreg_t eh_suppl : 11; + bdrkreg_t eh_reserved_4 : 1; + bdrkreg_t eh_source : 11; + bdrkreg_t eh_reserved_3 : 1; + bdrkreg_t eh_err_type : 4; + bdrkreg_t eh_reserved_2 : 4; + bdrkreg_t eh_overrun : 1; + bdrkreg_t eh_reserved_1 : 3; + bdrkreg_t eh_valid : 1; + bdrkreg_t eh_reserved : 19; + } lb_error_hdr1_fld_s; +} lb_error_hdr1_u_t; + +#else + +typedef union lb_error_hdr1_u { + bdrkreg_t lb_error_hdr1_regval; + struct { + bdrkreg_t eh_reserved : 19; + bdrkreg_t eh_valid : 1; + bdrkreg_t eh_reserved_1 : 3; + bdrkreg_t eh_overrun : 1; + bdrkreg_t eh_reserved_2 : 4; + bdrkreg_t eh_err_type : 4; + bdrkreg_t eh_reserved_3 : 1; + bdrkreg_t eh_source : 11; + bdrkreg_t eh_reserved_4 : 1; + bdrkreg_t eh_suppl : 11; + bdrkreg_t eh_reserved_5 : 1; + bdrkreg_t eh_command : 7; + } lb_error_hdr1_fld_s; +} lb_error_hdr1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contents of the Address field from header flit of first packet * + * that causes an error. This register is not relevant when a * + * GCLK_DROP error occurs. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_error_hdr2_u { + bdrkreg_t lb_error_hdr2_regval; + struct { + bdrkreg_t eh_address : 38; + bdrkreg_t eh_reserved : 26; + } lb_error_hdr2_fld_s; +} lb_error_hdr2_u_t; + +#else + +typedef union lb_error_hdr2_u { + bdrkreg_t lb_error_hdr2_regval; + struct { + bdrkreg_t eh_reserved : 26; + bdrkreg_t eh_address : 38; + } lb_error_hdr2_fld_s; +} lb_error_hdr2_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register accompanies the LB_ERROR_HDR1 and * + * LB_ERROR_HDR2 registers. The LB updates the value in this * + * register when an incoming packet with a data flit causes an error * + * while VALID==0 in the LB_ERROR_HDR1 register. This register * + * retains the contents of the data flit from the incoming packet * + * that caused the error. This register is relevant for the following * + * types of errors: * + * <UL > * + * <UL > * + * <UL > * + * <UL > * + * <UL > * + * <LI >RQ_BAD_LINVAL for a LINVAL request. * + * <LI >RQ_BAD_ADDR for a normal or vector PIO request. * + * <LI >RP_BAD_DATA for a vector PIO reply. * + * <LI >RQ_BAD DATA for an incoming request with data. * + * <LI >RP_LONG for a vector PIO reply. * + * <LI >RQ_LONG for an incoming request with expected data. * + * <BLOCKQUOTE > * + * In the case of RQ_BAD_LINVAL, the register retains the 64-bit data * + * value that followed the header flit. In the case of RQ_BAD_ADDR * + * or RQ_BAD_DATA, the register retains the incoming packet's 64-bit * + * data value (i.e., 2nd flit in the packet for a normal PIO write or * + * an LINVAL, 3rd flit for a vector PIO read or write). In the case * + * of RP_BAD_DATA, the register retains the 64-bit data value in the * + * 3rd flit of the packet. When a RP_LONG or RQ_LONG error occurs, * + * the LB loads the LB_ERROR_DATA register with the contents of the * + * expected data flit (i.e., the 3rd flit in the packet for a vector * + * PIO request or reply, the 2nd flit for other packets), if any. The * + * contents of the LB_ERROR_DATA register are undefined after a * + * RP_SHORT, RQ_SHORT, RP_BAD_CMD or RQ_BAD_CMD error. The contents * + * of the LB_ERROR_DATA register are also undefined after an incoming * + * normal PIO read request which encounters a RQ_LONG error. * + * * + ************************************************************************/ + + + + +typedef union lb_error_data_u { + bdrkreg_t lb_error_data_regval; + struct { + bdrkreg_t ed_data : 64; + } lb_error_data_fld_s; +} lb_error_data_u_t; + + + + +/************************************************************************ + * * + * This register enables software to control what internal Bedrock * + * signals are visible on the chip's debug pins. The LB provides the * + * 6-bit value in this register to Bedrock's DEBUG unit. The JTAG * + * unit provides a similar 6-bit selection input to the DEBUG unit, * + * along with another signal that tells the DEBUG unit whether to use * + * the selection signal from the LB or the JTAG unit. For a * + * description of the menu of choices for debug signals, refer to the * + * documentation for the DEBUG unit. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_debug_select_u { + bdrkreg_t lb_debug_select_regval; + struct { + bdrkreg_t ds_debug_sel : 6; + bdrkreg_t ds_reserved : 58; + } lb_debug_select_fld_s; +} lb_debug_select_u_t; + +#else + +typedef union lb_debug_select_u { + bdrkreg_t lb_debug_select_regval; + struct { + bdrkreg_t ds_reserved : 58; + bdrkreg_t ds_debug_sel : 6; + } lb_debug_select_fld_s; +} lb_debug_select_u_t; + +#endif + + + + +/************************************************************************ + * * + * A PIO read from this register returns the 32-bit value that is * + * currently on the Bedrock chip's debug pins. This register allows * + * software to observe debug pin output values which do not change * + * frequently (i.e., they remain constant over a period of many * + * cycles). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_debug_pins_u { + bdrkreg_t lb_debug_pins_regval; + struct { + bdrkreg_t dp_debug_pins : 32; + bdrkreg_t dp_reserved : 32; + } lb_debug_pins_fld_s; +} lb_debug_pins_u_t; + +#else + +typedef union lb_debug_pins_u { + bdrkreg_t lb_debug_pins_regval; + struct { + bdrkreg_t dp_reserved : 32; + bdrkreg_t dp_debug_pins : 32; + } lb_debug_pins_fld_s; +} lb_debug_pins_u_t; + +#endif + + + + +/************************************************************************ + * * + * The LB unit provides the PI0 and PI1 units with a real-time clock * + * signal. The LB can generate this signal itself, based on the * + * Bedrock chip's system clock which the LB receives as an input. * + * Alternatively, the LB can filter a global clock signal which it * + * receives as an input and provide the filtered version to PI0 and * + * PI1. The user can program the LB_RT_LOCAL_CTRL register to choose * + * the source of the real-time clock. If the user chooses to generate * + * the real-time clock internally within the LB, then the user can * + * specify the period for the real-time clock signal. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_rt_local_ctrl_u { + bdrkreg_t lb_rt_local_ctrl_regval; + struct { + bdrkreg_t rlc_gclk_enable : 1; + bdrkreg_t rlc_reserved_4 : 3; + bdrkreg_t rlc_max_count : 10; + bdrkreg_t rlc_reserved_3 : 2; + bdrkreg_t rlc_gclk_counter : 10; + bdrkreg_t rlc_reserved_2 : 2; + bdrkreg_t rlc_gclk : 1; + bdrkreg_t rlc_reserved_1 : 3; + bdrkreg_t rlc_use_internal : 1; + bdrkreg_t rlc_reserved : 31; + } lb_rt_local_ctrl_fld_s; +} lb_rt_local_ctrl_u_t; + +#else + +typedef union lb_rt_local_ctrl_u { + bdrkreg_t lb_rt_local_ctrl_regval; + struct { + bdrkreg_t rlc_reserved : 31; + bdrkreg_t rlc_use_internal : 1; + bdrkreg_t rlc_reserved_1 : 3; + bdrkreg_t rlc_gclk : 1; + bdrkreg_t rlc_reserved_2 : 2; + bdrkreg_t rlc_gclk_counter : 10; + bdrkreg_t rlc_reserved_3 : 2; + bdrkreg_t rlc_max_count : 10; + bdrkreg_t rlc_reserved_4 : 3; + bdrkreg_t rlc_gclk_enable : 1; + } lb_rt_local_ctrl_fld_s; +} lb_rt_local_ctrl_u_t; + +#endif + + + + +/************************************************************************ + * * + * When the value of the USE_INTERNAL field in the LB_RT_LOCAL_CTRL * + * register is 0, the LB filters an incoming global clock signal and * + * provides the result to PI0 and PI1 for their real-time clock * + * inputs. The LB can perform either simple filtering or complex * + * filtering, depending on the value of the MASK_ENABLE bit. For the * + * simple filtering option, the LB merely removes glitches from the * + * incoming global clock; if the global clock goes high (or low) for * + * only a single cycle, the LB considers it to be a glitch and does * + * not pass it through to PI0 and PI1. For the complex filtering * + * option, the LB expects positive edges on the incoming global clock * + * to be spaced at fairly regular intervals and it looks for them at * + * these times; the LB keeps track of unexpected or missing positive * + * edges, and it generates an edge itself whenever the incoming * + * global clock apparently misses an edge. For each filtering option, * + * the real-time clock which the LB provides to PI0 and PI1 is not * + * necessarily a square wave; when a positive edge happens, the * + * real-time clock stays high for (2*MAX_COUNT+1-OFFSET)/2 cycles of * + * the LB's system clock, and then is low until the next positive * + * edge. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_rt_filter_ctrl_u { + bdrkreg_t lb_rt_filter_ctrl_regval; + struct { + bdrkreg_t rfc_offset : 5; + bdrkreg_t rfc_reserved_4 : 3; + bdrkreg_t rfc_mask_counter : 12; + bdrkreg_t rfc_mask_enable : 1; + bdrkreg_t rfc_reserved_3 : 3; + bdrkreg_t rfc_dropout_counter : 10; + bdrkreg_t rfc_reserved_2 : 2; + bdrkreg_t rfc_dropout_thresh : 10; + bdrkreg_t rfc_reserved_1 : 2; + bdrkreg_t rfc_error_counter : 10; + bdrkreg_t rfc_reserved : 6; + } lb_rt_filter_ctrl_fld_s; +} lb_rt_filter_ctrl_u_t; + +#else + +typedef union lb_rt_filter_ctrl_u { + bdrkreg_t lb_rt_filter_ctrl_regval; + struct { + bdrkreg_t rfc_reserved : 6; + bdrkreg_t rfc_error_counter : 10; + bdrkreg_t rfc_reserved_1 : 2; + bdrkreg_t rfc_dropout_thresh : 10; + bdrkreg_t rfc_reserved_2 : 2; + bdrkreg_t rfc_dropout_counter : 10; + bdrkreg_t rfc_reserved_3 : 3; + bdrkreg_t rfc_mask_enable : 1; + bdrkreg_t rfc_mask_counter : 12; + bdrkreg_t rfc_reserved_4 : 3; + bdrkreg_t rfc_offset : 5; + } lb_rt_filter_ctrl_fld_s; +} lb_rt_filter_ctrl_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is a scratch register that is reset to 0x0. At the * + * normal address, the register is a simple storage location. At the * + * Write-If-Zero address, the register accepts a new value from a * + * write operation only if the current value is zero. * + * * + ************************************************************************/ + + + + +typedef union lb_scratch_reg0_u { + bdrkreg_t lb_scratch_reg0_regval; + struct { + bdrkreg_t sr_scratch_bits : 64; + } lb_scratch_reg0_fld_s; +} lb_scratch_reg0_u_t; + + + + +/************************************************************************ + * * + * These registers are scratch registers that are not reset. At a * + * register's normal address, it is a simple storage location. At a * + * register's Write-If-Zero address, it accepts a new value from a * + * write operation only if the current value is zero. * + * * + ************************************************************************/ + + + + +typedef union lb_scratch_reg1_u { + bdrkreg_t lb_scratch_reg1_regval; + struct { + bdrkreg_t sr_scratch_bits : 64; + } lb_scratch_reg1_fld_s; +} lb_scratch_reg1_u_t; + + + + +/************************************************************************ + * * + * These registers are scratch registers that are not reset. At a * + * register's normal address, it is a simple storage location. At a * + * register's Write-If-Zero address, it accepts a new value from a * + * write operation only if the current value is zero. * + * * + ************************************************************************/ + + + + +typedef union lb_scratch_reg2_u { + bdrkreg_t lb_scratch_reg2_regval; + struct { + bdrkreg_t sr_scratch_bits : 64; + } lb_scratch_reg2_fld_s; +} lb_scratch_reg2_u_t; + + + + +/************************************************************************ + * * + * These one-bit registers are scratch registers. At a register's * + * normal address, it is a simple storage location. At a register's * + * Read-Set-If-Zero address, it returns the original contents and * + * sets the bit if the original value is zero. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_scratch_reg3_u { + bdrkreg_t lb_scratch_reg3_regval; + struct { + bdrkreg_t sr_scratch_bit : 1; + bdrkreg_t sr_reserved : 63; + } lb_scratch_reg3_fld_s; +} lb_scratch_reg3_u_t; + +#else + +typedef union lb_scratch_reg3_u { + bdrkreg_t lb_scratch_reg3_regval; + struct { + bdrkreg_t sr_reserved : 63; + bdrkreg_t sr_scratch_bit : 1; + } lb_scratch_reg3_fld_s; +} lb_scratch_reg3_u_t; + +#endif + + + + +/************************************************************************ + * * + * These one-bit registers are scratch registers. At a register's * + * normal address, it is a simple storage location. At a register's * + * Read-Set-If-Zero address, it returns the original contents and * + * sets the bit if the original value is zero. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_scratch_reg4_u { + bdrkreg_t lb_scratch_reg4_regval; + struct { + bdrkreg_t sr_scratch_bit : 1; + bdrkreg_t sr_reserved : 63; + } lb_scratch_reg4_fld_s; +} lb_scratch_reg4_u_t; + +#else + +typedef union lb_scratch_reg4_u { + bdrkreg_t lb_scratch_reg4_regval; + struct { + bdrkreg_t sr_reserved : 63; + bdrkreg_t sr_scratch_bit : 1; + } lb_scratch_reg4_fld_s; +} lb_scratch_reg4_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is a scratch register that is reset to 0x0. At the * + * normal address, the register is a simple storage location. At the * + * Write-If-Zero address, the register accepts a new value from a * + * write operation only if the current value is zero. * + * * + ************************************************************************/ + + + + +typedef union lb_scratch_reg0_wz_u { + bdrkreg_t lb_scratch_reg0_wz_regval; + struct { + bdrkreg_t srw_scratch_bits : 64; + } lb_scratch_reg0_wz_fld_s; +} lb_scratch_reg0_wz_u_t; + + + + +/************************************************************************ + * * + * These registers are scratch registers that are not reset. At a * + * register's normal address, it is a simple storage location. At a * + * register's Write-If-Zero address, it accepts a new value from a * + * write operation only if the current value is zero. * + * * + ************************************************************************/ + + + + +typedef union lb_scratch_reg1_wz_u { + bdrkreg_t lb_scratch_reg1_wz_regval; + struct { + bdrkreg_t srw_scratch_bits : 64; + } lb_scratch_reg1_wz_fld_s; +} lb_scratch_reg1_wz_u_t; + + + + +/************************************************************************ + * * + * These registers are scratch registers that are not reset. At a * + * register's normal address, it is a simple storage location. At a * + * register's Write-If-Zero address, it accepts a new value from a * + * write operation only if the current value is zero. * + * * + ************************************************************************/ + + + + +typedef union lb_scratch_reg2_wz_u { + bdrkreg_t lb_scratch_reg2_wz_regval; + struct { + bdrkreg_t srw_scratch_bits : 64; + } lb_scratch_reg2_wz_fld_s; +} lb_scratch_reg2_wz_u_t; + + + + +/************************************************************************ + * * + * These one-bit registers are scratch registers. At a register's * + * normal address, it is a simple storage location. At a register's * + * Read-Set-If-Zero address, it returns the original contents and * + * sets the bit if the original value is zero. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_scratch_reg3_rz_u { + bdrkreg_t lb_scratch_reg3_rz_regval; + struct { + bdrkreg_t srr_scratch_bit : 1; + bdrkreg_t srr_reserved : 63; + } lb_scratch_reg3_rz_fld_s; +} lb_scratch_reg3_rz_u_t; + +#else + +typedef union lb_scratch_reg3_rz_u { + bdrkreg_t lb_scratch_reg3_rz_regval; + struct { + bdrkreg_t srr_reserved : 63; + bdrkreg_t srr_scratch_bit : 1; + } lb_scratch_reg3_rz_fld_s; +} lb_scratch_reg3_rz_u_t; + +#endif + + + + +/************************************************************************ + * * + * These one-bit registers are scratch registers. At a register's * + * normal address, it is a simple storage location. At a register's * + * Read-Set-If-Zero address, it returns the original contents and * + * sets the bit if the original value is zero. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_scratch_reg4_rz_u { + bdrkreg_t lb_scratch_reg4_rz_regval; + struct { + bdrkreg_t srr_scratch_bit : 1; + bdrkreg_t srr_reserved : 63; + } lb_scratch_reg4_rz_fld_s; +} lb_scratch_reg4_rz_u_t; + +#else + +typedef union lb_scratch_reg4_rz_u { + bdrkreg_t lb_scratch_reg4_rz_regval; + struct { + bdrkreg_t srr_reserved : 63; + bdrkreg_t srr_scratch_bit : 1; + } lb_scratch_reg4_rz_fld_s; +} lb_scratch_reg4_rz_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register contains vector PIO parameters. A * + * write to this register triggers the LB to send out a vector PIO * + * request packet. Immediately after servicing a write request to the * + * LB_VECTOR_PARMS register, the LB sends back a reply (i.e., the LB * + * doesn't wait for the vector PIO operation to finish first). Three * + * LB registers provide the contents for an outgoing vector PIO * + * request packet. Software should wait until the BUSY bit in * + * LB_VECTOR_PARMS is clear and then initialize all three of these * + * registers before initiating a vector PIO operation. The three * + * vector PIO registers are: * + * LB_VECTOR_ROUTE * + * LB_VECTOR_DATA * + * LB_VECTOR_PARMS (should be written last) * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_vector_parms_u { + bdrkreg_t lb_vector_parms_regval; + struct { + bdrkreg_t vp_type : 1; + bdrkreg_t vp_reserved_2 : 2; + bdrkreg_t vp_address : 21; + bdrkreg_t vp_reserved_1 : 8; + bdrkreg_t vp_write_id : 8; + bdrkreg_t vp_pio_id : 11; + bdrkreg_t vp_reserved : 12; + bdrkreg_t vp_busy : 1; + } lb_vector_parms_fld_s; +} lb_vector_parms_u_t; + +#else + +typedef union lb_vector_parms_u { + bdrkreg_t lb_vector_parms_regval; + struct { + bdrkreg_t vp_busy : 1; + bdrkreg_t vp_reserved : 12; + bdrkreg_t vp_pio_id : 11; + bdrkreg_t vp_write_id : 8; + bdrkreg_t vp_reserved_1 : 8; + bdrkreg_t vp_address : 21; + bdrkreg_t vp_reserved_2 : 2; + bdrkreg_t vp_type : 1; + } lb_vector_parms_fld_s; +} lb_vector_parms_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the vector PIO route. This is one of the 3 * + * vector PIO control registers. * + * * + ************************************************************************/ + + + + +typedef union lb_vector_route_u { + bdrkreg_t lb_vector_route_regval; + struct { + bdrkreg_t vr_vector : 64; + } lb_vector_route_fld_s; +} lb_vector_route_u_t; + + + + +/************************************************************************ + * * + * This register contains the vector PIO write data. This is one of * + * the 3 vector PIO control registers. The contents of this register * + * also provide the data value to be sent in outgoing vector PIO read * + * requests and vector PIO write replies. * + * * + ************************************************************************/ + + + + +typedef union lb_vector_data_u { + bdrkreg_t lb_vector_data_regval; + struct { + bdrkreg_t vd_write_data : 64; + } lb_vector_data_fld_s; +} lb_vector_data_u_t; + + + + +/************************************************************************ + * * + * Description: This register contains the vector PIO return status. * + * Software should clear this register before launching a vector PIO * + * request from the LB. The LB will not modify this register's value * + * if an incoming reply packet encounters any kind of error. If an * + * incoming reply packet does not encounter an error but the * + * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit * + * and leaves the other fields unchanged. The LB updates the values * + * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if * + * an incoming vector PIO reply packet does not encounter an error * + * and the STATUS_VALID bit is clear; at the same time, the LB sets * + * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and * + * LB_VECTOR_READ_DATA registers. * + * * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_vector_status_u { + bdrkreg_t lb_vector_status_regval; + struct { + bdrkreg_t vs_type : 3; + bdrkreg_t vs_address : 21; + bdrkreg_t vs_reserved : 8; + bdrkreg_t vs_write_id : 8; + bdrkreg_t vs_pio_id : 11; + bdrkreg_t vs_source : 11; + bdrkreg_t vs_overrun : 1; + bdrkreg_t vs_status_valid : 1; + } lb_vector_status_fld_s; +} lb_vector_status_u_t; + +#else + +typedef union lb_vector_status_u { + bdrkreg_t lb_vector_status_regval; + struct { + bdrkreg_t vs_status_valid : 1; + bdrkreg_t vs_overrun : 1; + bdrkreg_t vs_source : 11; + bdrkreg_t vs_pio_id : 11; + bdrkreg_t vs_write_id : 8; + bdrkreg_t vs_reserved : 8; + bdrkreg_t vs_address : 21; + bdrkreg_t vs_type : 3; + } lb_vector_status_fld_s; +} lb_vector_status_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the return vector PIO route. The LB will * + * not modify this register's value if an incoming reply packet * + * encounters any kind of error. The LB also will not modify this * + * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS * + * register is set when it receives an incoming vector PIO reply. The * + * LB stores an incoming vector PIO reply packet's vector route flit * + * in this register only if the packet does not encounter an error * + * and the STATUS_VALID bit is clear. * + * * + ************************************************************************/ + + + + +typedef union lb_vector_return_u { + bdrkreg_t lb_vector_return_regval; + struct { + bdrkreg_t vr_return_vector : 64; + } lb_vector_return_fld_s; +} lb_vector_return_u_t; + + + + +/************************************************************************ + * * + * This register contains the vector PIO read data, if any. The LB * + * will not modify this register's value if an incoming reply packet * + * encounters any kind of error. The LB also will not modify this * + * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS * + * register is set when it receives an incoming vector PIO reply. The * + * LB stores an incoming vector PIO reply packet's data flit in this * + * register only if the packet does not encounter an error and the * + * STATUS_VALID bit is clear. * + * * + ************************************************************************/ + + + + +typedef union lb_vector_read_data_u { + bdrkreg_t lb_vector_read_data_regval; + struct { + bdrkreg_t vrd_read_data : 64; + } lb_vector_read_data_fld_s; +} lb_vector_read_data_u_t; + + + + +/************************************************************************ + * * + * Description: This register contains the vector PIO return status. * + * Software should clear this register before launching a vector PIO * + * request from the LB. The LB will not modify this register's value * + * if an incoming reply packet encounters any kind of error. If an * + * incoming reply packet does not encounter an error but the * + * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit * + * and leaves the other fields unchanged. The LB updates the values * + * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if * + * an incoming vector PIO reply packet does not encounter an error * + * and the STATUS_VALID bit is clear; at the same time, the LB sets * + * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and * + * LB_VECTOR_READ_DATA registers. * + * * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union lb_vector_status_clear_u { + bdrkreg_t lb_vector_status_clear_regval; + struct { + bdrkreg_t vsc_type : 3; + bdrkreg_t vsc_address : 21; + bdrkreg_t vsc_reserved : 8; + bdrkreg_t vsc_write_id : 8; + bdrkreg_t vsc_pio_id : 11; + bdrkreg_t vsc_source : 11; + bdrkreg_t vsc_overrun : 1; + bdrkreg_t vsc_status_valid : 1; + } lb_vector_status_clear_fld_s; +} lb_vector_status_clear_u_t; + +#else + +typedef union lb_vector_status_clear_u { + bdrkreg_t lb_vector_status_clear_regval; + struct { + bdrkreg_t vsc_status_valid : 1; + bdrkreg_t vsc_overrun : 1; + bdrkreg_t vsc_source : 11; + bdrkreg_t vsc_pio_id : 11; + bdrkreg_t vsc_write_id : 8; + bdrkreg_t vsc_reserved : 8; + bdrkreg_t vsc_address : 21; + bdrkreg_t vsc_type : 3; + } lb_vector_status_clear_fld_s; +} lb_vector_status_clear_u_t; + +#endif + + + + + + +#endif /* _LANGUAGE_C */ + +/************************************************************************ + * * + * MAKE ALL ADDITIONS AFTER THIS LINE * + * * + ************************************************************************/ + + + + + +#endif /* _ASM_SN_SN1_HUBLB_H */ diff --git a/include/asm-ia64/sn/sn1/hublb_next.h b/include/asm-ia64/sn/sn1/hublb_next.h new file mode 100644 index 000000000..a0c8430f1 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hublb_next.h @@ -0,0 +1,110 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBLB_NEXT_H +#define _ASM_SN_SN1_HUBLB_NEXT_H + +/********************************************************************** + + This contains some mask and shift values for LB defined as required + for compatibility. + + **********************************************************************/ + +#define LRI_SYSTEM_SIZE_SHFT 46 +#define LRI_SYSTEM_SIZE_MASK (UINT64_CAST 0x3 << LRI_SYSTEM_SIZE_SHFT) +#define LRI_NODEID_SHFT 32 +#define LRI_NODEID_MASK (UINT64_CAST 0xff << LRI_NODEID_SHFT)/* Node ID */ +#define LRI_CHIPID_SHFT 12 +#define LRI_CHIPID_MASK (UINT64_CAST 0xffff << LRI_CHIPID_SHFT) /* should be 0x3012 */ +#define LRI_REV_SHFT 28 +#define LRI_REV_MASK (UINT64_CAST 0xf << LRI_REV_SHFT)/* Chip revision */ + +/* Values for LRI_SYSTEM_SIZE */ +#define SYSTEM_SIZE_INVALID 0x3 +#define SYSTEM_SIZE_NMODE 0x2 +#define SYSTEM_SIZE_COARSE 0x1 +#define SYSTEM_SIZE_SMALL 0x0 + +/* In fine mode, each node is a region. In coarse mode, there are + * 2 nodes per region. In N-mode, there are 4 nodes per region. */ +#define NASID_TO_FINEREG_SHFT 0 +#define NASID_TO_COARSEREG_SHFT 1 +#define NASID_TO_NMODEREG_SHFT 2 + +#define LR_LOCALRESET (UINT64_CAST 1) +/* + * LB_VECTOR_PARMS mask and shift definitions. + * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS. + */ + +#define LVP_BUSY (UINT64_CAST 1 << 63) +#define LVP_PIOID_SHFT 40 +#define LVP_PIOID_MASK (UINT64_CAST 0x7ff << 40) +#define LVP_WRITEID_SHFT 32 +#define LVP_WRITEID_MASK (UINT64_CAST 0xff << 32) +#define LVP_ADDRESS_MASK (UINT64_CAST 0xfffff8) /* Bits 23:3 */ +#define LVP_TYPE_SHFT 0 +#define LVP_TYPE_MASK (UINT64_CAST 0x3) + +/* LB_VECTOR_STATUS mask and shift definitions */ + +#define LVS_VALID (UINT64_CAST 1 << 63) +#define LVS_OVERRUN (UINT64_CAST 1 << 62) +#define LVS_TARGET_SHFT 51 +#define LVS_TARGET_MASK (UINT64_CAST 0x7ff << 51) +#define LVS_PIOID_SHFT 40 +#define LVS_PIOID_MASK (UINT64_CAST 0x7ff << 40) +#define LVS_WRITEID_SHFT 32 +#define LVS_WRITEID_MASK (UINT64_CAST 0xff << 32) +#define LVS_ADDRESS_MASK (UINT64_CAST 0xfffff8) /* Bits 23:3 */ +#define LVS_TYPE_SHFT 0 +#define LVS_TYPE_MASK (UINT64_CAST 0x7) +#define LVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */ + +/* LB_RT_LOCAL_CTRL mask and shift definitions */ + +#define LRLC_USE_INT_SHFT 32 +#define LRLC_USE_INT_MASK (UINT64_CAST 1 << 32) +#define LRLC_USE_INT (UINT64_CAST 1 << 32) +#define LRLC_GCLK_SHFT 28 +#define LRLC_GCLK_MASK (UINT64_CAST 1 << 28) +#define LRLC_GCLK (UINT64_CAST 1 << 28) +#define LRLC_GCLK_COUNT_SHFT 16 +#define LRLC_GCLK_COUNT_MASK (UINT64_CAST 0x3ff << 16) +#define LRLC_MAX_COUNT_SHFT 4 +#define LRLC_MAX_COUNT_MASK (UINT64_CAST 0x3ff << 4) +#define LRLC_GCLK_EN_SHFT 0 +#define LRLC_GCLK_EN_MASK (UINT64_CAST 1) +#define LRLC_GCLK_EN (UINT64_CAST 1) + +/* LB_NODES_ABSENT mask and shift definitions */ +#define LNA_VALID_SHFT 15 +#define LNA_VALID_MASK (UINT64_CAST 1 << LNA_VALID_SHFT) +#define LNA_VALID (UINT64_CAST 1 << LNA_VALID_SHFT) +#define LNA_NODE_SHFT 0 +#define LNA_NODE_MASK (UINT64_CAST 0xff << LNA_NODE_SHFT) + +/* LB_NODES_ABSENT has 4 identical sub-registers, on 16-bit boundaries */ +#define LNA_ENTRY_SHFT 16 +#define LNA_MAX_ENTRIES 4 +#define LNA_ADD(_reg, _n) ((_reg) = (_reg) << LNA_ENTRY_SHFT | \ + LNA_VALID | (_n) << LNA_NODE_SHFT) + +#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */ +#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */ +#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */ +/* XXX IP35 doesn't support vector exchange: scr. regs. do locks directly */ +#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */ +#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */ +#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */ +#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */ +#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */ + +#endif /* _ASM_SN_SN1_HUBLB_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubmd.h b/include/asm-ia64/sn/sn1/hubmd.h new file mode 100644 index 000000000..0f5bada86 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubmd.h @@ -0,0 +1,2477 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBMD_H +#define _ASM_SN_SN1_HUBMD_H + + +/************************************************************************ + * * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * + * * + * This file is created by an automated script. Any (minimal) changes * + * made manually to this file should be made with care. * + * * + * MAKE ALL ADDITIONS TO THE END OF THIS FILE * + * * + ************************************************************************/ + + +#define MD_CURRENT_CELL 0x00780000 /* + * BDDIR, LREG, LBOOT, + * RREG, RBOOT + * protection and mask + * for using Local + * Access protection. + */ + + + +#define MD_MEMORY_CONFIG 0x00780008 /* + * Memory/Directory + * DIMM control + */ + + + +#define MD_ARBITRATION_CONTROL 0x00780010 /* + * Arbitration + * Parameters + */ + + + +#define MD_MIG_CONFIG 0x00780018 /* + * Page Migration + * control + */ + + + +#define MD_FANDOP_CAC_STAT0 0x00780020 /* + * Fetch-and-op cache + * 0 status + */ + + + +#define MD_FANDOP_CAC_STAT1 0x00780028 /* + * Fetch-and-op cache + * 1 status + */ + + + +#define MD_MISC0_ERROR 0x00780040 /* + * Miscellaneous MD + * error + */ + + + +#define MD_MISC1_ERROR 0x00780048 /* + * Miscellaneous MD + * error + */ + + + +#define MD_MISC1_ERROR_CLR 0x00780058 /* + * Miscellaneous MD + * error clear + */ + + + +#define MD_OUTGOING_RP_QUEUE_SIZE 0x00780060 /* + * MD outgoing reply + * queues sizing + */ + + + +#define MD_PERF_SEL0 0x00790000 /* + * Selects events + * monitored by + * MD_PERF_CNT0 + */ + + + +#define MD_PERF_SEL1 0x00790008 /* + * Selects events + * monitored by + * MD_PERF_CNT1 + */ + + + +#define MD_PERF_CNT0 0x00790010 /* + * Performance counter + * 0 + */ + + + +#define MD_PERF_CNT1 0x00790018 /* + * Performance counter + * 1 + */ + + + +#define MD_REFRESH_CONTROL 0x007A0000 /* + * Memory/Directory + * refresh control + */ + + + +#define MD_JUNK_BUS_TIMING 0x007A0008 /* Junk Bus Timing */ + + + +#define MD_LED0 0x007A0010 /* Reads of 8-bit LED0 */ + + + +#define MD_LED1 0x007A0018 /* Reads of 8-bit LED1 */ + + + +#define MD_LED2 0x007A0020 /* Reads of 8-bit LED2 */ + + + +#define MD_LED3 0x007A0028 /* Reads of 8-bit LED3 */ + + + +#define MD_BIST_CTL 0x007A0030 /* + * BIST general + * control + */ + + + +#define MD_BIST_DATA 0x007A0038 /* + * BIST initial data + * pattern and + * variation control + */ + + + +#define MD_BIST_AB_ERR_ADDR 0x007A0040 /* BIST error address */ + + + +#define MD_BIST_STATUS 0x007A0048 /* BIST status */ + + + +#define MD_IB_DEBUG 0x007A0060 /* IB debug select */ + + + +#define MD_DIR_CONFIG 0x007C0000 /* + * Directory mode + * control + */ + + + +#define MD_DIR_ERROR 0x007C0010 /* + * Directory DIMM + * error + */ + + + +#define MD_DIR_ERROR_CLR 0x007C0018 /* + * Directory DIMM + * error clear + */ + + + +#define MD_PROTOCOL_ERROR 0x007C0020 /* + * Directory protocol + * error + */ + + + +#define MD_PROTOCOL_ERR_CLR 0x007C0028 /* + * Directory protocol + * error clear + */ + + + +#define MD_MIG_CANDIDATE 0x007C0030 /* + * Page migration + * candidate + */ + + + +#define MD_MIG_CANDIDATE_CLR 0x007C0038 /* + * Page migration + * candidate clear + */ + + + +#define MD_MIG_DIFF_THRESH 0x007C0040 /* + * Page migration + * count difference + * threshold + */ + + + +#define MD_MIG_VALUE_THRESH 0x007C0048 /* + * Page migration + * count absolute + * threshold + */ + + + +#define MD_OUTGOING_RQ_QUEUE_SIZE 0x007C0050 /* + * MD outgoing request + * queues sizing + */ + + + +#define MD_BIST_DB_ERR_DATA 0x007C0058 /* + * BIST directory + * error data + */ + + + +#define MD_DB_DEBUG 0x007C0060 /* DB debug select */ + + + +#define MD_MB_ECC_CONFIG 0x007E0000 /* + * Data ECC + * Configuration + */ + + + +#define MD_MEM_ERROR 0x007E0010 /* Memory DIMM error */ + + + +#define MD_MEM_ERROR_CLR 0x007E0018 /* + * Memory DIMM error + * clear + */ + + + +#define MD_BIST_MB_ERR_DATA_0 0x007E0020 /* + * BIST memory error + * data + */ + + + +#define MD_BIST_MB_ERR_DATA_1 0x007E0028 /* + * BIST memory error + * data + */ + + + +#define MD_BIST_MB_ERR_DATA_2 0x007E0030 /* + * BIST memory error + * data + */ + + + +#define MD_BIST_MB_ERR_DATA_3 0x007E0038 /* + * BIST memory error + * data + */ + + + +#define MD_MB_DEBUG 0x007E0040 /* MB debug select */ + + + + + +#ifdef _LANGUAGE_C + +/************************************************************************ + * * + * Description: This register shows which regions are in the current * + * cell. If a region has its bit set in this register, then it uses * + * the Local Access protection in the directory instead of the * + * separate per-region protection (which would cause a small * + * performance penalty). In addition, writeback and write reply * + * commands from outside the current cell will always check the * + * directory protection before writing data to memory. Writeback and * + * write reply commands from inside the current cell will write * + * memory regardless of the protection value. * + * This register is also used as the access-rights bit-vector for * + * most of the ASIC-special (HSpec) portion of the address space. It * + * covers the BDDIR, LREG, LBOOT, RREG, and RBOOT spaces. It does not * + * cover the UALIAS and BDECC spaces, as they are covered by the * + * protection in the directory. If a bit in the bit-vector is set, * + * the region corresponding to that bit has read/write permission on * + * these spaces. If the bit is clear, then that region has read-only * + * access to these spaces (except for LREG/RREG which have no access * + * when the bit is clear). * + * The granularity of a region is set by the REGION_SIZE register in * + * the NI local register space. * + * NOTE: This means that no processor outside the current cell can * + * write into the BDDIR, LREG, LBOOT, RREG, or RBOOT spaces. * + * * + ************************************************************************/ + + + + +typedef union md_current_cell_u { + bdrkreg_t md_current_cell_regval; + struct { + bdrkreg_t cc_hspec_prot : 64; + } md_current_cell_fld_s; +} md_current_cell_u_t; + + + + +/************************************************************************ + * * + * Description: This register contains three sets of information. * + * The first set describes the size and configuration of DIMMs that * + * are plugged into a system, the second set controls which set of * + * protection checks are performed on each access and the third set * + * controls various DDR SDRAM timing parameters. * + * In order to config a DIMM bank, three fields must be initialized: * + * BANK_SIZE, DRAM_WIDTH, and BANK_ENABLE. The BANK_SIZE field sets * + * the address range that the MD unit will accept for that DIMM bank. * + * All addresses larger than the specified size will return errors on * + * access. In order to read from a DIMM bank, Bedrock must know * + * whether or not the bank contains x4 or x8/x16 DRAM. The operating * + * system must query the System Controller for this information and * + * then set the DRAM_WIDTH field accordingly. The BANK_ENABLE field * + * can be used to individually enable the two physical banks located * + * on each DIMM bank. * + * The contents of this register are preserved through soft-resets. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_memory_config_u { + bdrkreg_t md_memory_config_regval; + struct { + bdrkreg_t mc_dimm0_bank_enable : 2; + bdrkreg_t mc_reserved_7 : 1; + bdrkreg_t mc_dimm0_dram_width : 1; + bdrkreg_t mc_dimm0_bank_size : 4; + bdrkreg_t mc_dimm1_bank_enable : 2; + bdrkreg_t mc_reserved_6 : 1; + bdrkreg_t mc_dimm1_dram_width : 1; + bdrkreg_t mc_dimm1_bank_size : 4; + bdrkreg_t mc_dimm2_bank_enable : 2; + bdrkreg_t mc_reserved_5 : 1; + bdrkreg_t mc_dimm2_dram_width : 1; + bdrkreg_t mc_dimm2_bank_size : 4; + bdrkreg_t mc_dimm3_bank_enable : 2; + bdrkreg_t mc_reserved_4 : 1; + bdrkreg_t mc_dimm3_dram_width : 1; + bdrkreg_t mc_dimm3_bank_size : 4; + bdrkreg_t mc_dimm0_sel : 2; + bdrkreg_t mc_reserved_3 : 10; + bdrkreg_t mc_cc_enable : 1; + bdrkreg_t mc_io_prot_en : 1; + bdrkreg_t mc_io_prot_ignore : 1; + bdrkreg_t mc_cpu_prot_ignore : 1; + bdrkreg_t mc_db_neg_edge : 1; + bdrkreg_t mc_phase_delay : 1; + bdrkreg_t mc_delay_mux_sel : 2; + bdrkreg_t mc_sample_time : 2; + bdrkreg_t mc_reserved_2 : 2; + bdrkreg_t mc_mb_neg_edge : 3; + bdrkreg_t mc_reserved_1 : 1; + bdrkreg_t mc_rcd_config : 1; + bdrkreg_t mc_rp_config : 1; + bdrkreg_t mc_reserved : 2; + } md_memory_config_fld_s; +} md_memory_config_u_t; + +#else + +typedef union md_memory_config_u { + bdrkreg_t md_memory_config_regval; + struct { + bdrkreg_t mc_reserved : 2; + bdrkreg_t mc_rp_config : 1; + bdrkreg_t mc_rcd_config : 1; + bdrkreg_t mc_reserved_1 : 1; + bdrkreg_t mc_mb_neg_edge : 3; + bdrkreg_t mc_reserved_2 : 2; + bdrkreg_t mc_sample_time : 2; + bdrkreg_t mc_delay_mux_sel : 2; + bdrkreg_t mc_phase_delay : 1; + bdrkreg_t mc_db_neg_edge : 1; + bdrkreg_t mc_cpu_prot_ignore : 1; + bdrkreg_t mc_io_prot_ignore : 1; + bdrkreg_t mc_io_prot_en : 1; + bdrkreg_t mc_cc_enable : 1; + bdrkreg_t mc_reserved_3 : 10; + bdrkreg_t mc_dimm0_sel : 2; + bdrkreg_t mc_dimm3_bank_size : 4; + bdrkreg_t mc_dimm3_dram_width : 1; + bdrkreg_t mc_reserved_4 : 1; + bdrkreg_t mc_dimm3_bank_enable : 2; + bdrkreg_t mc_dimm2_bank_size : 4; + bdrkreg_t mc_dimm2_dram_width : 1; + bdrkreg_t mc_reserved_5 : 1; + bdrkreg_t mc_dimm2_bank_enable : 2; + bdrkreg_t mc_dimm1_bank_size : 4; + bdrkreg_t mc_dimm1_dram_width : 1; + bdrkreg_t mc_reserved_6 : 1; + bdrkreg_t mc_dimm1_bank_enable : 2; + bdrkreg_t mc_dimm0_bank_size : 4; + bdrkreg_t mc_dimm0_dram_width : 1; + bdrkreg_t mc_reserved_7 : 1; + bdrkreg_t mc_dimm0_bank_enable : 2; + } md_memory_config_fld_s; +} md_memory_config_u_t; + +#endif + + + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_arbitration_control_u { + bdrkreg_t md_arbitration_control_regval; + struct { + bdrkreg_t ac_reply_guar : 4; + bdrkreg_t ac_write_guar : 4; + bdrkreg_t ac_reserved : 56; + } md_arbitration_control_fld_s; +} md_arbitration_control_u_t; + +#else + +typedef union md_arbitration_control_u { + bdrkreg_t md_arbitration_control_regval; + struct { + bdrkreg_t ac_reserved : 56; + bdrkreg_t ac_write_guar : 4; + bdrkreg_t ac_reply_guar : 4; + } md_arbitration_control_fld_s; +} md_arbitration_control_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains page migration control fields. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mig_config_u { + bdrkreg_t md_mig_config_regval; + struct { + bdrkreg_t mc_mig_interval : 10; + bdrkreg_t mc_reserved_2 : 6; + bdrkreg_t mc_mig_node_mask : 8; + bdrkreg_t mc_reserved_1 : 8; + bdrkreg_t mc_mig_enable : 1; + bdrkreg_t mc_reserved : 31; + } md_mig_config_fld_s; +} md_mig_config_u_t; + +#else + +typedef union md_mig_config_u { + bdrkreg_t md_mig_config_regval; + struct { + bdrkreg_t mc_reserved : 31; + bdrkreg_t mc_mig_enable : 1; + bdrkreg_t mc_reserved_1 : 8; + bdrkreg_t mc_mig_node_mask : 8; + bdrkreg_t mc_reserved_2 : 6; + bdrkreg_t mc_mig_interval : 10; + } md_mig_config_fld_s; +} md_mig_config_u_t; + +#endif + + + + +/************************************************************************ + * * + * Each register contains the valid bit and address of the entry in * + * the fetch-and-op for cache 0 (or 1). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_fandop_cac_stat0_u { + bdrkreg_t md_fandop_cac_stat0_regval; + struct { + bdrkreg_t fcs_reserved_1 : 6; + bdrkreg_t fcs_addr : 27; + bdrkreg_t fcs_reserved : 30; + bdrkreg_t fcs_valid : 1; + } md_fandop_cac_stat0_fld_s; +} md_fandop_cac_stat0_u_t; + +#else + +typedef union md_fandop_cac_stat0_u { + bdrkreg_t md_fandop_cac_stat0_regval; + struct { + bdrkreg_t fcs_valid : 1; + bdrkreg_t fcs_reserved : 30; + bdrkreg_t fcs_addr : 27; + bdrkreg_t fcs_reserved_1 : 6; + } md_fandop_cac_stat0_fld_s; +} md_fandop_cac_stat0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Each register contains the valid bit and address of the entry in * + * the fetch-and-op for cache 0 (or 1). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_fandop_cac_stat1_u { + bdrkreg_t md_fandop_cac_stat1_regval; + struct { + bdrkreg_t fcs_reserved_1 : 6; + bdrkreg_t fcs_addr : 27; + bdrkreg_t fcs_reserved : 30; + bdrkreg_t fcs_valid : 1; + } md_fandop_cac_stat1_fld_s; +} md_fandop_cac_stat1_u_t; + +#else + +typedef union md_fandop_cac_stat1_u { + bdrkreg_t md_fandop_cac_stat1_regval; + struct { + bdrkreg_t fcs_valid : 1; + bdrkreg_t fcs_reserved : 30; + bdrkreg_t fcs_addr : 27; + bdrkreg_t fcs_reserved_1 : 6; + } md_fandop_cac_stat1_fld_s; +} md_fandop_cac_stat1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: Contains a number of fields to capture various * + * random memory/directory errors. For each 2-bit field, the LSB * + * indicates that additional information has been captured for the * + * error and the MSB indicates overrun, thus: * + * x1: bits 51...0 of this register contain additional information * + * for the message that caused this error * + * 1x: overrun occurred * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_misc0_error_u { + bdrkreg_t md_misc0_error_regval; + struct { + bdrkreg_t me_command : 7; + bdrkreg_t me_reserved_4 : 1; + bdrkreg_t me_source : 11; + bdrkreg_t me_reserved_3 : 1; + bdrkreg_t me_suppl : 11; + bdrkreg_t me_reserved_2 : 1; + bdrkreg_t me_virtual_channel : 2; + bdrkreg_t me_reserved_1 : 2; + bdrkreg_t me_tail : 1; + bdrkreg_t me_reserved : 11; + bdrkreg_t me_xb_error : 4; + bdrkreg_t me_bad_partial_data : 2; + bdrkreg_t me_missing_dv : 2; + bdrkreg_t me_short_pack : 2; + bdrkreg_t me_long_pack : 2; + bdrkreg_t me_ill_msg : 2; + bdrkreg_t me_ill_revision : 2; + } md_misc0_error_fld_s; +} md_misc0_error_u_t; + +#else + +typedef union md_misc0_error_u { + bdrkreg_t md_misc0_error_regval; + struct { + bdrkreg_t me_ill_revision : 2; + bdrkreg_t me_ill_msg : 2; + bdrkreg_t me_long_pack : 2; + bdrkreg_t me_short_pack : 2; + bdrkreg_t me_missing_dv : 2; + bdrkreg_t me_bad_partial_data : 2; + bdrkreg_t me_xb_error : 4; + bdrkreg_t me_reserved : 11; + bdrkreg_t me_tail : 1; + bdrkreg_t me_reserved_1 : 2; + bdrkreg_t me_virtual_channel : 2; + bdrkreg_t me_reserved_2 : 1; + bdrkreg_t me_suppl : 11; + bdrkreg_t me_reserved_3 : 1; + bdrkreg_t me_source : 11; + bdrkreg_t me_reserved_4 : 1; + bdrkreg_t me_command : 7; + } md_misc0_error_fld_s; +} md_misc0_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Address for error captured in MISC0_ERROR. Error valid bits are * + * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be * + * read sequentially without missing any errors). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_misc1_error_u { + bdrkreg_t md_misc1_error_regval; + struct { + bdrkreg_t me_reserved_1 : 3; + bdrkreg_t me_address : 38; + bdrkreg_t me_reserved : 7; + bdrkreg_t me_xb_error : 4; + bdrkreg_t me_bad_partial_data : 2; + bdrkreg_t me_missing_dv : 2; + bdrkreg_t me_short_pack : 2; + bdrkreg_t me_long_pack : 2; + bdrkreg_t me_ill_msg : 2; + bdrkreg_t me_ill_revision : 2; + } md_misc1_error_fld_s; +} md_misc1_error_u_t; + +#else + +typedef union md_misc1_error_u { + bdrkreg_t md_misc1_error_regval; + struct { + bdrkreg_t me_ill_revision : 2; + bdrkreg_t me_ill_msg : 2; + bdrkreg_t me_long_pack : 2; + bdrkreg_t me_short_pack : 2; + bdrkreg_t me_missing_dv : 2; + bdrkreg_t me_bad_partial_data : 2; + bdrkreg_t me_xb_error : 4; + bdrkreg_t me_reserved : 7; + bdrkreg_t me_address : 38; + bdrkreg_t me_reserved_1 : 3; + } md_misc1_error_fld_s; +} md_misc1_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Address for error captured in MISC0_ERROR. Error valid bits are * + * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be * + * read sequentially without missing any errors). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_misc1_error_clr_u { + bdrkreg_t md_misc1_error_clr_regval; + struct { + bdrkreg_t mec_reserved_1 : 3; + bdrkreg_t mec_address : 38; + bdrkreg_t mec_reserved : 7; + bdrkreg_t mec_xb_error : 4; + bdrkreg_t mec_bad_partial_data : 2; + bdrkreg_t mec_missing_dv : 2; + bdrkreg_t mec_short_pack : 2; + bdrkreg_t mec_long_pack : 2; + bdrkreg_t mec_ill_msg : 2; + bdrkreg_t mec_ill_revision : 2; + } md_misc1_error_clr_fld_s; +} md_misc1_error_clr_u_t; + +#else + +typedef union md_misc1_error_clr_u { + bdrkreg_t md_misc1_error_clr_regval; + struct { + bdrkreg_t mec_ill_revision : 2; + bdrkreg_t mec_ill_msg : 2; + bdrkreg_t mec_long_pack : 2; + bdrkreg_t mec_short_pack : 2; + bdrkreg_t mec_missing_dv : 2; + bdrkreg_t mec_bad_partial_data : 2; + bdrkreg_t mec_xb_error : 4; + bdrkreg_t mec_reserved : 7; + bdrkreg_t mec_address : 38; + bdrkreg_t mec_reserved_1 : 3; + } md_misc1_error_clr_fld_s; +} md_misc1_error_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: The MD no longer allows for arbitrarily sizing the * + * reply queues, so all of the fields in this register are read-only * + * and contain the reset default value of 12 for the MOQHs (for * + * headers) and 24 for the MOQDs (for data). * + * Reading from this register returns the values currently held in * + * the MD's credit counters. Writing to the register resets the * + * counters to the default reset values specified in the table below. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_outgoing_rp_queue_size_u { + bdrkreg_t md_outgoing_rp_queue_size_regval; + struct { + bdrkreg_t orqs_reserved_6 : 8; + bdrkreg_t orqs_moqh_p0_rp_size : 4; + bdrkreg_t orqs_reserved_5 : 4; + bdrkreg_t orqs_moqh_p1_rp_size : 4; + bdrkreg_t orqs_reserved_4 : 4; + bdrkreg_t orqs_moqh_np_rp_size : 4; + bdrkreg_t orqs_reserved_3 : 4; + bdrkreg_t orqs_moqd_pi0_rp_size : 5; + bdrkreg_t orqs_reserved_2 : 3; + bdrkreg_t orqs_moqd_pi1_rp_size : 5; + bdrkreg_t orqs_reserved_1 : 3; + bdrkreg_t orqs_moqd_np_rp_size : 5; + bdrkreg_t orqs_reserved : 11; + } md_outgoing_rp_queue_size_fld_s; +} md_outgoing_rp_queue_size_u_t; + +#else + +typedef union md_outgoing_rp_queue_size_u { + bdrkreg_t md_outgoing_rp_queue_size_regval; + struct { + bdrkreg_t orqs_reserved : 11; + bdrkreg_t orqs_moqd_np_rp_size : 5; + bdrkreg_t orqs_reserved_1 : 3; + bdrkreg_t orqs_moqd_pi1_rp_size : 5; + bdrkreg_t orqs_reserved_2 : 3; + bdrkreg_t orqs_moqd_pi0_rp_size : 5; + bdrkreg_t orqs_reserved_3 : 4; + bdrkreg_t orqs_moqh_np_rp_size : 4; + bdrkreg_t orqs_reserved_4 : 4; + bdrkreg_t orqs_moqh_p1_rp_size : 4; + bdrkreg_t orqs_reserved_5 : 4; + bdrkreg_t orqs_moqh_p0_rp_size : 4; + bdrkreg_t orqs_reserved_6 : 8; + } md_outgoing_rp_queue_size_fld_s; +} md_outgoing_rp_queue_size_u_t; + +#endif + + + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_perf_sel0_u { + bdrkreg_t md_perf_sel0_regval; + struct { + bdrkreg_t ps_cnt_mode : 2; + bdrkreg_t ps_reserved_2 : 2; + bdrkreg_t ps_activity : 4; + bdrkreg_t ps_source : 7; + bdrkreg_t ps_reserved_1 : 1; + bdrkreg_t ps_channel : 4; + bdrkreg_t ps_command : 40; + bdrkreg_t ps_reserved : 3; + bdrkreg_t ps_interrupt : 1; + } md_perf_sel0_fld_s; +} md_perf_sel0_u_t; + +#else + +typedef union md_perf_sel0_u { + bdrkreg_t md_perf_sel0_regval; + struct { + bdrkreg_t ps_interrupt : 1; + bdrkreg_t ps_reserved : 3; + bdrkreg_t ps_command : 40; + bdrkreg_t ps_channel : 4; + bdrkreg_t ps_reserved_1 : 1; + bdrkreg_t ps_source : 7; + bdrkreg_t ps_activity : 4; + bdrkreg_t ps_reserved_2 : 2; + bdrkreg_t ps_cnt_mode : 2; + } md_perf_sel0_fld_s; +} md_perf_sel0_u_t; + +#endif + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_perf_sel1_u { + bdrkreg_t md_perf_sel1_regval; + struct { + bdrkreg_t ps_cnt_mode : 2; + bdrkreg_t ps_reserved_2 : 2; + bdrkreg_t ps_activity : 4; + bdrkreg_t ps_source : 7; + bdrkreg_t ps_reserved_1 : 1; + bdrkreg_t ps_channel : 4; + bdrkreg_t ps_command : 40; + bdrkreg_t ps_reserved : 3; + bdrkreg_t ps_interrupt : 1; + } md_perf_sel1_fld_s; +} md_perf_sel1_u_t; + +#else + +typedef union md_perf_sel1_u { + bdrkreg_t md_perf_sel1_regval; + struct { + bdrkreg_t ps_interrupt : 1; + bdrkreg_t ps_reserved : 3; + bdrkreg_t ps_command : 40; + bdrkreg_t ps_channel : 4; + bdrkreg_t ps_reserved_1 : 1; + bdrkreg_t ps_source : 7; + bdrkreg_t ps_activity : 4; + bdrkreg_t ps_reserved_2 : 2; + bdrkreg_t ps_cnt_mode : 2; + } md_perf_sel1_fld_s; +} md_perf_sel1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Performance counter. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_perf_cnt0_u { + bdrkreg_t md_perf_cnt0_regval; + struct { + bdrkreg_t pc_perf_cnt : 41; + bdrkreg_t pc_reserved : 23; + } md_perf_cnt0_fld_s; +} md_perf_cnt0_u_t; + +#else + +typedef union md_perf_cnt0_u { + bdrkreg_t md_perf_cnt0_regval; + struct { + bdrkreg_t pc_reserved : 23; + bdrkreg_t pc_perf_cnt : 41; + } md_perf_cnt0_fld_s; +} md_perf_cnt0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Performance counter. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_perf_cnt1_u { + bdrkreg_t md_perf_cnt1_regval; + struct { + bdrkreg_t pc_perf_cnt : 41; + bdrkreg_t pc_reserved : 23; + } md_perf_cnt1_fld_s; +} md_perf_cnt1_u_t; + +#else + +typedef union md_perf_cnt1_u { + bdrkreg_t md_perf_cnt1_regval; + struct { + bdrkreg_t pc_reserved : 23; + bdrkreg_t pc_perf_cnt : 41; + } md_perf_cnt1_fld_s; +} md_perf_cnt1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register contains the control for * + * memory/directory refresh. Once the MEMORY_CONFIG register contains * + * the correct DIMM information, the hardware takes care of * + * refreshing all the banks in the system. Therefore, the value in * + * the counter threshold is corresponds exactly to the refresh value * + * required by the SDRAM parts (expressed in Bedrock clock cycles). * + * The refresh will execute whenever there is a free cycle and there * + * are still banks that have not been refreshed in the current * + * window. If the window expires with banks still waiting to be * + * refreshed, all other transactions are halted until the banks are * + * refreshed. * + * The upper order bit contains an enable, which may be needed for * + * correct initialization of the DIMMs (according to the specs, the * + * first operation to the DIMMs should be a mode register write, not * + * a refresh, so this bit is cleared on reset) and is also useful for * + * diagnostic purposes. * + * For the SDRAM parts used by Bedrock, 4096 refreshes need to be * + * issued during every 64 ms window, resulting in a refresh threshold * + * of 3125 Bedrock cycles. * + * The ENABLE and CNT_THRESH fields of this register are preserved * + * through soft-resets. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_refresh_control_u { + bdrkreg_t md_refresh_control_regval; + struct { + bdrkreg_t rc_cnt_thresh : 12; + bdrkreg_t rc_counter : 12; + bdrkreg_t rc_reserved : 39; + bdrkreg_t rc_enable : 1; + } md_refresh_control_fld_s; +} md_refresh_control_u_t; + +#else + +typedef union md_refresh_control_u { + bdrkreg_t md_refresh_control_regval; + struct { + bdrkreg_t rc_enable : 1; + bdrkreg_t rc_reserved : 39; + bdrkreg_t rc_counter : 12; + bdrkreg_t rc_cnt_thresh : 12; + } md_refresh_control_fld_s; +} md_refresh_control_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register controls the read and write timing for Flash PROM, * + * UART and Synergy junk bus devices. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_junk_bus_timing_u { + bdrkreg_t md_junk_bus_timing_regval; + struct { + bdrkreg_t jbt_fprom_setup_hold : 8; + bdrkreg_t jbt_fprom_enable : 8; + bdrkreg_t jbt_uart_setup_hold : 8; + bdrkreg_t jbt_uart_enable : 8; + bdrkreg_t jbt_synergy_setup_hold : 8; + bdrkreg_t jbt_synergy_enable : 8; + bdrkreg_t jbt_reserved : 16; + } md_junk_bus_timing_fld_s; +} md_junk_bus_timing_u_t; + +#else + +typedef union md_junk_bus_timing_u { + bdrkreg_t md_junk_bus_timing_regval; + struct { + bdrkreg_t jbt_reserved : 16; + bdrkreg_t jbt_synergy_enable : 8; + bdrkreg_t jbt_synergy_setup_hold : 8; + bdrkreg_t jbt_uart_enable : 8; + bdrkreg_t jbt_uart_setup_hold : 8; + bdrkreg_t jbt_fprom_enable : 8; + bdrkreg_t jbt_fprom_setup_hold : 8; + } md_junk_bus_timing_fld_s; +} md_junk_bus_timing_u_t; + +#endif + + + + +/************************************************************************ + * * + * Each of these addresses allows the value on one 8-bit bank of * + * LEDs to be read. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_led0_u { + bdrkreg_t md_led0_regval; + struct { + bdrkreg_t l_data : 8; + bdrkreg_t l_reserved : 56; + } md_led0_fld_s; +} md_led0_u_t; + +#else + +typedef union md_led0_u { + bdrkreg_t md_led0_regval; + struct { + bdrkreg_t l_reserved : 56; + bdrkreg_t l_data : 8; + } md_led0_fld_s; +} md_led0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Each of these addresses allows the value on one 8-bit bank of * + * LEDs to be read. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_led1_u { + bdrkreg_t md_led1_regval; + struct { + bdrkreg_t l_data : 8; + bdrkreg_t l_reserved : 56; + } md_led1_fld_s; +} md_led1_u_t; + +#else + +typedef union md_led1_u { + bdrkreg_t md_led1_regval; + struct { + bdrkreg_t l_reserved : 56; + bdrkreg_t l_data : 8; + } md_led1_fld_s; +} md_led1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Each of these addresses allows the value on one 8-bit bank of * + * LEDs to be read. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_led2_u { + bdrkreg_t md_led2_regval; + struct { + bdrkreg_t l_data : 8; + bdrkreg_t l_reserved : 56; + } md_led2_fld_s; +} md_led2_u_t; + +#else + +typedef union md_led2_u { + bdrkreg_t md_led2_regval; + struct { + bdrkreg_t l_reserved : 56; + bdrkreg_t l_data : 8; + } md_led2_fld_s; +} md_led2_u_t; + +#endif + + + + +/************************************************************************ + * * + * Each of these addresses allows the value on one 8-bit bank of * + * LEDs to be read. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_led3_u { + bdrkreg_t md_led3_regval; + struct { + bdrkreg_t l_data : 8; + bdrkreg_t l_reserved : 56; + } md_led3_fld_s; +} md_led3_u_t; + +#else + +typedef union md_led3_u { + bdrkreg_t md_led3_regval; + struct { + bdrkreg_t l_reserved : 56; + bdrkreg_t l_data : 8; + } md_led3_fld_s; +} md_led3_u_t; + +#endif + + + + +/************************************************************************ + * * + * Core control for the BIST function. Start and stop BIST at any * + * time. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_ctl_u { + bdrkreg_t md_bist_ctl_regval; + struct { + bdrkreg_t bc_bist_start : 1; + bdrkreg_t bc_bist_stop : 1; + bdrkreg_t bc_bist_reset : 1; + bdrkreg_t bc_reserved_1 : 1; + bdrkreg_t bc_bank_num : 1; + bdrkreg_t bc_dimm_num : 2; + bdrkreg_t bc_reserved : 57; + } md_bist_ctl_fld_s; +} md_bist_ctl_u_t; + +#else + +typedef union md_bist_ctl_u { + bdrkreg_t md_bist_ctl_regval; + struct { + bdrkreg_t bc_reserved : 57; + bdrkreg_t bc_dimm_num : 2; + bdrkreg_t bc_bank_num : 1; + bdrkreg_t bc_reserved_1 : 1; + bdrkreg_t bc_bist_reset : 1; + bdrkreg_t bc_bist_stop : 1; + bdrkreg_t bc_bist_start : 1; + } md_bist_ctl_fld_s; +} md_bist_ctl_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contain the initial BIST data nibble and the 4-bit data control * + * field.. * + * * + ************************************************************************/ + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_data_u { + bdrkreg_t md_bist_data_regval; + struct { + bdrkreg_t bd_bist_data : 4; + bdrkreg_t bd_bist_nibble : 1; + bdrkreg_t bd_bist_byte : 1; + bdrkreg_t bd_bist_cycle : 1; + bdrkreg_t bd_bist_write : 1; + bdrkreg_t bd_reserved : 56; + } md_bist_data_fld_s; +} md_bist_data_u_t; + +#else + +typedef union md_bist_data_u { + bdrkreg_t md_bist_data_regval; + struct { + bdrkreg_t bd_reserved : 56; + bdrkreg_t bd_bist_write : 1; + bdrkreg_t bd_bist_cycle : 1; + bdrkreg_t bd_bist_byte : 1; + bdrkreg_t bd_bist_nibble : 1; + bdrkreg_t bd_bist_data : 4; + } md_bist_data_fld_s; +} md_bist_data_u_t; + +#endif + + + + +/************************************************************************ + * * + * Captures the BIST error address and indicates whether it is an MB * + * error or DB error. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_ab_err_addr_u { + bdrkreg_t md_bist_ab_err_addr_regval; + struct { + bdrkreg_t baea_be_db_cas_addr : 15; + bdrkreg_t baea_reserved_3 : 1; + bdrkreg_t baea_be_mb_cas_addr : 15; + bdrkreg_t baea_reserved_2 : 1; + bdrkreg_t baea_be_ras_addr : 15; + bdrkreg_t baea_reserved_1 : 1; + bdrkreg_t baea_bist_mb_error : 1; + bdrkreg_t baea_bist_db_error : 1; + bdrkreg_t baea_reserved : 14; + } md_bist_ab_err_addr_fld_s; +} md_bist_ab_err_addr_u_t; + +#else + +typedef union md_bist_ab_err_addr_u { + bdrkreg_t md_bist_ab_err_addr_regval; + struct { + bdrkreg_t baea_reserved : 14; + bdrkreg_t baea_bist_db_error : 1; + bdrkreg_t baea_bist_mb_error : 1; + bdrkreg_t baea_reserved_1 : 1; + bdrkreg_t baea_be_ras_addr : 15; + bdrkreg_t baea_reserved_2 : 1; + bdrkreg_t baea_be_mb_cas_addr : 15; + bdrkreg_t baea_reserved_3 : 1; + bdrkreg_t baea_be_db_cas_addr : 15; + } md_bist_ab_err_addr_fld_s; +} md_bist_ab_err_addr_u_t; + +#endif + + + +/************************************************************************ + * * + * Contains information on BIST progress and memory bank currently * + * under BIST. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_status_u { + bdrkreg_t md_bist_status_regval; + struct { + bdrkreg_t bs_bist_passed : 1; + bdrkreg_t bs_bist_done : 1; + bdrkreg_t bs_reserved : 62; + } md_bist_status_fld_s; +} md_bist_status_u_t; + +#else + +typedef union md_bist_status_u { + bdrkreg_t md_bist_status_regval; + struct { + bdrkreg_t bs_reserved : 62; + bdrkreg_t bs_bist_done : 1; + bdrkreg_t bs_bist_passed : 1; + } md_bist_status_fld_s; +} md_bist_status_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains 3 bits that allow the selection of IB debug information * + * at the debug port (see design specification for available debug * + * information). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_ib_debug_u { + bdrkreg_t md_ib_debug_regval; + struct { + bdrkreg_t id_ib_debug_sel : 2; + bdrkreg_t id_reserved : 62; + } md_ib_debug_fld_s; +} md_ib_debug_u_t; + +#else + +typedef union md_ib_debug_u { + bdrkreg_t md_ib_debug_regval; + struct { + bdrkreg_t id_reserved : 62; + bdrkreg_t id_ib_debug_sel : 2; + } md_ib_debug_fld_s; +} md_ib_debug_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains the directory specific mode bits. The contents of this * + * register are preserved through soft-resets. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_dir_config_u { + bdrkreg_t md_dir_config_regval; + struct { + bdrkreg_t dc_dir_flavor : 1; + bdrkreg_t dc_ignore_dir_ecc : 1; + bdrkreg_t dc_reserved : 62; + } md_dir_config_fld_s; +} md_dir_config_u_t; + +#else + +typedef union md_dir_config_u { + bdrkreg_t md_dir_config_regval; + struct { + bdrkreg_t dc_reserved : 62; + bdrkreg_t dc_ignore_dir_ecc : 1; + bdrkreg_t dc_dir_flavor : 1; + } md_dir_config_fld_s; +} md_dir_config_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: Contains information on uncorrectable and * + * correctable directory ECC errors, along with protection ECC * + * errors. The priority of ECC errors latched is: uncorrectable * + * directory, protection error, correctable directory. Thus the valid * + * bits signal: * + * 1xxx: uncorrectable directory ECC error (UCE) * + * 01xx: access protection double bit error (AE) * + * 001x: correctable directory ECC error (CE) * + * 0001: access protection correctable error (ACE) * + * If the UCE valid bit is set, the address field contains a pointer * + * to the Hspec address of the offending directory entry, the * + * syndrome field contains the bad syndrome, and the UCE overrun bit * + * indicates whether multiple double-bit errors were received. * + * If the UCE valid bit is clear but the AE valid bit is set, the * + * address field contains a pointer to the Hspec address of the * + * offending protection entry, the Bad Protection field contains the * + * 4-bit bad protection value, the PROT_INDEX field shows which of * + * the 8 protection values in the word was bad and the AE overrun bit * + * indicates whether multiple AE errors were received. * + * If the UCE and AE valid bits are clear, but the CE valid bit is * + * set, the address field contains a pointer to the Hspec address of * + * the offending directory entry, the syndrome field contains the bad * + * syndrome, and the CE overrun bit indicates whether multiple * + * single-bit errors were received. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_dir_error_u { + bdrkreg_t md_dir_error_regval; + struct { + bdrkreg_t de_reserved_3 : 3; + bdrkreg_t de_hspec_addr : 30; + bdrkreg_t de_reserved_2 : 7; + bdrkreg_t de_bad_syn : 7; + bdrkreg_t de_reserved_1 : 1; + bdrkreg_t de_bad_protect : 4; + bdrkreg_t de_prot_index : 3; + bdrkreg_t de_reserved : 1; + bdrkreg_t de_ace_overrun : 1; + bdrkreg_t de_ce_overrun : 1; + bdrkreg_t de_ae_overrun : 1; + bdrkreg_t de_uce_overrun : 1; + bdrkreg_t de_ace_valid : 1; + bdrkreg_t de_ce_valid : 1; + bdrkreg_t de_ae_valid : 1; + bdrkreg_t de_uce_valid : 1; + } md_dir_error_fld_s; +} md_dir_error_u_t; + +#else + +typedef union md_dir_error_u { + bdrkreg_t md_dir_error_regval; + struct { + bdrkreg_t de_uce_valid : 1; + bdrkreg_t de_ae_valid : 1; + bdrkreg_t de_ce_valid : 1; + bdrkreg_t de_ace_valid : 1; + bdrkreg_t de_uce_overrun : 1; + bdrkreg_t de_ae_overrun : 1; + bdrkreg_t de_ce_overrun : 1; + bdrkreg_t de_ace_overrun : 1; + bdrkreg_t de_reserved : 1; + bdrkreg_t de_prot_index : 3; + bdrkreg_t de_bad_protect : 4; + bdrkreg_t de_reserved_1 : 1; + bdrkreg_t de_bad_syn : 7; + bdrkreg_t de_reserved_2 : 7; + bdrkreg_t de_hspec_addr : 30; + bdrkreg_t de_reserved_3 : 3; + } md_dir_error_fld_s; +} md_dir_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: Contains information on uncorrectable and * + * correctable directory ECC errors, along with protection ECC * + * errors. The priority of ECC errors latched is: uncorrectable * + * directory, protection error, correctable directory. Thus the valid * + * bits signal: * + * 1xxx: uncorrectable directory ECC error (UCE) * + * 01xx: access protection double bit error (AE) * + * 001x: correctable directory ECC error (CE) * + * 0001: access protection correctable error (ACE) * + * If the UCE valid bit is set, the address field contains a pointer * + * to the Hspec address of the offending directory entry, the * + * syndrome field contains the bad syndrome, and the UCE overrun bit * + * indicates whether multiple double-bit errors were received. * + * If the UCE valid bit is clear but the AE valid bit is set, the * + * address field contains a pointer to the Hspec address of the * + * offending protection entry, the Bad Protection field contains the * + * 4-bit bad protection value, the PROT_INDEX field shows which of * + * the 8 protection values in the word was bad and the AE overrun bit * + * indicates whether multiple AE errors were received. * + * If the UCE and AE valid bits are clear, but the CE valid bit is * + * set, the address field contains a pointer to the Hspec address of * + * the offending directory entry, the syndrome field contains the bad * + * syndrome, and the CE overrun bit indicates whether multiple * + * single-bit errors were received. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_dir_error_clr_u { + bdrkreg_t md_dir_error_clr_regval; + struct { + bdrkreg_t dec_reserved_3 : 3; + bdrkreg_t dec_hspec_addr : 30; + bdrkreg_t dec_reserved_2 : 7; + bdrkreg_t dec_bad_syn : 7; + bdrkreg_t dec_reserved_1 : 1; + bdrkreg_t dec_bad_protect : 4; + bdrkreg_t dec_prot_index : 3; + bdrkreg_t dec_reserved : 1; + bdrkreg_t dec_ace_overrun : 1; + bdrkreg_t dec_ce_overrun : 1; + bdrkreg_t dec_ae_overrun : 1; + bdrkreg_t dec_uce_overrun : 1; + bdrkreg_t dec_ace_valid : 1; + bdrkreg_t dec_ce_valid : 1; + bdrkreg_t dec_ae_valid : 1; + bdrkreg_t dec_uce_valid : 1; + } md_dir_error_clr_fld_s; +} md_dir_error_clr_u_t; + +#else + +typedef union md_dir_error_clr_u { + bdrkreg_t md_dir_error_clr_regval; + struct { + bdrkreg_t dec_uce_valid : 1; + bdrkreg_t dec_ae_valid : 1; + bdrkreg_t dec_ce_valid : 1; + bdrkreg_t dec_ace_valid : 1; + bdrkreg_t dec_uce_overrun : 1; + bdrkreg_t dec_ae_overrun : 1; + bdrkreg_t dec_ce_overrun : 1; + bdrkreg_t dec_ace_overrun : 1; + bdrkreg_t dec_reserved : 1; + bdrkreg_t dec_prot_index : 3; + bdrkreg_t dec_bad_protect : 4; + bdrkreg_t dec_reserved_1 : 1; + bdrkreg_t dec_bad_syn : 7; + bdrkreg_t dec_reserved_2 : 7; + bdrkreg_t dec_hspec_addr : 30; + bdrkreg_t dec_reserved_3 : 3; + } md_dir_error_clr_fld_s; +} md_dir_error_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains information on requests that encounter no valid protocol * + * table entry. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_protocol_error_u { + bdrkreg_t md_protocol_error_regval; + struct { + bdrkreg_t pe_overrun : 1; + bdrkreg_t pe_pointer_me : 1; + bdrkreg_t pe_reserved_1 : 1; + bdrkreg_t pe_address : 30; + bdrkreg_t pe_reserved : 1; + bdrkreg_t pe_ptr1_btmbits : 3; + bdrkreg_t pe_dir_format : 2; + bdrkreg_t pe_dir_state : 3; + bdrkreg_t pe_priority : 1; + bdrkreg_t pe_access : 1; + bdrkreg_t pe_msg_type : 8; + bdrkreg_t pe_initiator : 11; + bdrkreg_t pe_valid : 1; + } md_protocol_error_fld_s; +} md_protocol_error_u_t; + +#else + +typedef union md_protocol_error_u { + bdrkreg_t md_protocol_error_regval; + struct { + bdrkreg_t pe_valid : 1; + bdrkreg_t pe_initiator : 11; + bdrkreg_t pe_msg_type : 8; + bdrkreg_t pe_access : 1; + bdrkreg_t pe_priority : 1; + bdrkreg_t pe_dir_state : 3; + bdrkreg_t pe_dir_format : 2; + bdrkreg_t pe_ptr1_btmbits : 3; + bdrkreg_t pe_reserved : 1; + bdrkreg_t pe_address : 30; + bdrkreg_t pe_reserved_1 : 1; + bdrkreg_t pe_pointer_me : 1; + bdrkreg_t pe_overrun : 1; + } md_protocol_error_fld_s; +} md_protocol_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains information on requests that encounter no valid protocol * + * table entry. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_protocol_err_clr_u { + bdrkreg_t md_protocol_err_clr_regval; + struct { + bdrkreg_t pec_overrun : 1; + bdrkreg_t pec_pointer_me : 1; + bdrkreg_t pec_reserved_1 : 1; + bdrkreg_t pec_address : 30; + bdrkreg_t pec_reserved : 1; + bdrkreg_t pec_ptr1_btmbits : 3; + bdrkreg_t pec_dir_format : 2; + bdrkreg_t pec_dir_state : 3; + bdrkreg_t pec_priority : 1; + bdrkreg_t pec_access : 1; + bdrkreg_t pec_msg_type : 8; + bdrkreg_t pec_initiator : 11; + bdrkreg_t pec_valid : 1; + } md_protocol_err_clr_fld_s; +} md_protocol_err_clr_u_t; + +#else + +typedef union md_protocol_err_clr_u { + bdrkreg_t md_protocol_err_clr_regval; + struct { + bdrkreg_t pec_valid : 1; + bdrkreg_t pec_initiator : 11; + bdrkreg_t pec_msg_type : 8; + bdrkreg_t pec_access : 1; + bdrkreg_t pec_priority : 1; + bdrkreg_t pec_dir_state : 3; + bdrkreg_t pec_dir_format : 2; + bdrkreg_t pec_ptr1_btmbits : 3; + bdrkreg_t pec_reserved : 1; + bdrkreg_t pec_address : 30; + bdrkreg_t pec_reserved_1 : 1; + bdrkreg_t pec_pointer_me : 1; + bdrkreg_t pec_overrun : 1; + } md_protocol_err_clr_fld_s; +} md_protocol_err_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains the address of the page and the requestor which caused a * + * migration threshold to be exceeded. Also contains the type of * + * threshold exceeded and an overrun bit. For Value mode type * + * interrupts, it indicates whether the local or the remote counter * + * triggered the interrupt. Unlike most registers, when the overrun * + * bit is set the register contains information on the most recent * + * (the last) migration candidate. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mig_candidate_u { + bdrkreg_t md_mig_candidate_regval; + struct { + bdrkreg_t mc_address : 21; + bdrkreg_t mc_initiator : 11; + bdrkreg_t mc_overrun : 1; + bdrkreg_t mc_type : 1; + bdrkreg_t mc_local : 1; + bdrkreg_t mc_reserved : 28; + bdrkreg_t mc_valid : 1; + } md_mig_candidate_fld_s; +} md_mig_candidate_u_t; + +#else + +typedef union md_mig_candidate_u { + bdrkreg_t md_mig_candidate_regval; + struct { + bdrkreg_t mc_valid : 1; + bdrkreg_t mc_reserved : 28; + bdrkreg_t mc_local : 1; + bdrkreg_t mc_type : 1; + bdrkreg_t mc_overrun : 1; + bdrkreg_t mc_initiator : 11; + bdrkreg_t mc_address : 21; + } md_mig_candidate_fld_s; +} md_mig_candidate_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains the address of the page and the requestor which caused a * + * migration threshold to be exceeded. Also contains the type of * + * threshold exceeded and an overrun bit. For Value mode type * + * interrupts, it indicates whether the local or the remote counter * + * triggered the interrupt. Unlike most registers, when the overrun * + * bit is set the register contains information on the most recent * + * (the last) migration candidate. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mig_candidate_clr_u { + bdrkreg_t md_mig_candidate_clr_regval; + struct { + bdrkreg_t mcc_address : 21; + bdrkreg_t mcc_initiator : 11; + bdrkreg_t mcc_overrun : 1; + bdrkreg_t mcc_type : 1; + bdrkreg_t mcc_local : 1; + bdrkreg_t mcc_reserved : 28; + bdrkreg_t mcc_valid : 1; + } md_mig_candidate_clr_fld_s; +} md_mig_candidate_clr_u_t; + +#else + +typedef union md_mig_candidate_clr_u { + bdrkreg_t md_mig_candidate_clr_regval; + struct { + bdrkreg_t mcc_valid : 1; + bdrkreg_t mcc_reserved : 28; + bdrkreg_t mcc_local : 1; + bdrkreg_t mcc_type : 1; + bdrkreg_t mcc_overrun : 1; + bdrkreg_t mcc_initiator : 11; + bdrkreg_t mcc_address : 21; + } md_mig_candidate_clr_fld_s; +} md_mig_candidate_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Controls the generation of page-migration interrupts and loading * + * of the MIGRATION_CANDIDATE register for pages which are using the * + * difference between the requestor and home counts. If the * + * difference is greater-than or equal to than the threshold * + * contained in the register, and the valid bit is set, the migration * + * candidate is loaded (and an interrupt generated if enabled by the * + * page migration mode). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mig_diff_thresh_u { + bdrkreg_t md_mig_diff_thresh_regval; + struct { + bdrkreg_t mdt_threshold : 15; + bdrkreg_t mdt_reserved_1 : 17; + bdrkreg_t mdt_th_action : 3; + bdrkreg_t mdt_sat_action : 3; + bdrkreg_t mdt_reserved : 25; + bdrkreg_t mdt_valid : 1; + } md_mig_diff_thresh_fld_s; +} md_mig_diff_thresh_u_t; + +#else + +typedef union md_mig_diff_thresh_u { + bdrkreg_t md_mig_diff_thresh_regval; + struct { + bdrkreg_t mdt_valid : 1; + bdrkreg_t mdt_reserved : 25; + bdrkreg_t mdt_sat_action : 3; + bdrkreg_t mdt_th_action : 3; + bdrkreg_t mdt_reserved_1 : 17; + bdrkreg_t mdt_threshold : 15; + } md_mig_diff_thresh_fld_s; +} md_mig_diff_thresh_u_t; + +#endif + + + + +/************************************************************************ + * * + * Controls the generation of page-migration interrupts and loading * + * of the MIGRATION_CANDIDATE register for pages that are using the * + * absolute value of the requestor count. If the value is * + * greater-than or equal to the threshold contained in the register, * + * and the register valid bit is set, the migration candidate is * + * loaded and an interrupt generated. For the value mode of page * + * migration, there are two variations. In the first variation, * + * interrupts are only generated when the remote counter reaches the * + * threshold, not when the local counter reaches the threshold. In * + * the second mode, both the local counter and the remote counter * + * generate interrupts if they reach the threshold. This second mode * + * is useful for performance monitoring, to track the number of local * + * and remote references to a page. LOCAL_INT determines whether we * + * will generate interrupts when the local counter reaches the * + * threshold. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mig_value_thresh_u { + bdrkreg_t md_mig_value_thresh_regval; + struct { + bdrkreg_t mvt_threshold : 15; + bdrkreg_t mvt_reserved_1 : 17; + bdrkreg_t mvt_th_action : 3; + bdrkreg_t mvt_sat_action : 3; + bdrkreg_t mvt_reserved : 24; + bdrkreg_t mvt_local_int : 1; + bdrkreg_t mvt_valid : 1; + } md_mig_value_thresh_fld_s; +} md_mig_value_thresh_u_t; + +#else + +typedef union md_mig_value_thresh_u { + bdrkreg_t md_mig_value_thresh_regval; + struct { + bdrkreg_t mvt_valid : 1; + bdrkreg_t mvt_local_int : 1; + bdrkreg_t mvt_reserved : 24; + bdrkreg_t mvt_sat_action : 3; + bdrkreg_t mvt_th_action : 3; + bdrkreg_t mvt_reserved_1 : 17; + bdrkreg_t mvt_threshold : 15; + } md_mig_value_thresh_fld_s; +} md_mig_value_thresh_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains the controls for the sizing of the three MOQH request * + * queues. The maximum (and default) value is 4. Queue sizes are in * + * flits. One header equals one flit. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_outgoing_rq_queue_size_u { + bdrkreg_t md_outgoing_rq_queue_size_regval; + struct { + bdrkreg_t orqs_reserved_3 : 8; + bdrkreg_t orqs_moqh_p0_rq_size : 3; + bdrkreg_t orqs_reserved_2 : 5; + bdrkreg_t orqs_moqh_p1_rq_size : 3; + bdrkreg_t orqs_reserved_1 : 5; + bdrkreg_t orqs_moqh_np_rq_size : 3; + bdrkreg_t orqs_reserved : 37; + } md_outgoing_rq_queue_size_fld_s; +} md_outgoing_rq_queue_size_u_t; + +#else + +typedef union md_outgoing_rq_queue_size_u { + bdrkreg_t md_outgoing_rq_queue_size_regval; + struct { + bdrkreg_t orqs_reserved : 37; + bdrkreg_t orqs_moqh_np_rq_size : 3; + bdrkreg_t orqs_reserved_1 : 5; + bdrkreg_t orqs_moqh_p1_rq_size : 3; + bdrkreg_t orqs_reserved_2 : 5; + bdrkreg_t orqs_moqh_p0_rq_size : 3; + bdrkreg_t orqs_reserved_3 : 8; + } md_outgoing_rq_queue_size_fld_s; +} md_outgoing_rq_queue_size_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains the 32-bit directory word failing BIST. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_db_err_data_u { + bdrkreg_t md_bist_db_err_data_regval; + struct { + bdrkreg_t bded_db_er_d : 32; + bdrkreg_t bded_reserved : 32; + } md_bist_db_err_data_fld_s; +} md_bist_db_err_data_u_t; + +#else + +typedef union md_bist_db_err_data_u { + bdrkreg_t md_bist_db_err_data_regval; + struct { + bdrkreg_t bded_reserved : 32; + bdrkreg_t bded_db_er_d : 32; + } md_bist_db_err_data_fld_s; +} md_bist_db_err_data_u_t; + +#endif + + + +/************************************************************************ + * * + * Contains 2 bits that allow the selection of DB debug information * + * at the debug port (see the design specification for descrition of * + * the available debug information). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_db_debug_u { + bdrkreg_t md_db_debug_regval; + struct { + bdrkreg_t dd_db_debug_sel : 2; + bdrkreg_t dd_reserved : 62; + } md_db_debug_fld_s; +} md_db_debug_u_t; + +#else + +typedef union md_db_debug_u { + bdrkreg_t md_db_debug_regval; + struct { + bdrkreg_t dd_reserved : 62; + bdrkreg_t dd_db_debug_sel : 2; + } md_db_debug_fld_s; +} md_db_debug_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains the IgnoreECC bit. When this bit is set, all ECC errors * + * are ignored. ECC bits will still be generated on writebacks. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mb_ecc_config_u { + bdrkreg_t md_mb_ecc_config_regval; + struct { + bdrkreg_t mec_ignore_dataecc : 1; + bdrkreg_t mec_reserved : 63; + } md_mb_ecc_config_fld_s; +} md_mb_ecc_config_u_t; + +#else + +typedef union md_mb_ecc_config_u { + bdrkreg_t md_mb_ecc_config_regval; + struct { + bdrkreg_t mec_reserved : 63; + bdrkreg_t mec_ignore_dataecc : 1; + } md_mb_ecc_config_fld_s; +} md_mb_ecc_config_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: Contains information on read memory errors (both * + * correctable and uncorrectable) and write memory errors (always * + * uncorrectable). The errors are prioritized as follows: * + * highest: uncorrectable read error (READ_UCE) * + * middle: write error (WRITE_UCE) * + * lowest: correctable read error (READ_CE) * + * Each type of error maintains a two-bit valid/overrun field * + * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field * + * corresponds to the valid bit, and bit 1 of each two-bit field * + * corresponds to the overrun bit. * + * The rule for the valid bit is that it gets set whenever that error * + * occurs, regardless of whether a higher priority error has occured. * + * The rule for the overrun bit is that it gets set whenever we are * + * unable to record the address information for this particular * + * error, due to a previous error of the same or higher priority. * + * Note that the syndrome and address information always corresponds * + * to the earliest, highest priority error. * + * Finally, the UCE_DIFF_ADDR bit is set whenever there have been * + * several uncorrectable errors, to different cache line addresses. * + * If all the UCEs were to the same cache line address, then * + * UCE_DIFF_ADDR will be 0. This allows the operating system to * + * detect the case where a UCE error is read exclusively, and then * + * written back by the processor. If the bit is 0, it indicates that * + * no information has been lost about UCEs on other cache lines. In * + * particular, partial writes do a read modify write of the cache * + * line. A UCE read error will be set when the cache line is read, * + * and a UCE write error will occur when the cache line is written * + * back, but the UCE_DIFF_ADDR will not be set. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mem_error_u { + bdrkreg_t md_mem_error_regval; + struct { + bdrkreg_t me_reserved_5 : 3; + bdrkreg_t me_address : 30; + bdrkreg_t me_reserved_4 : 7; + bdrkreg_t me_bad_syn : 8; + bdrkreg_t me_reserved_3 : 4; + bdrkreg_t me_read_ce : 2; + bdrkreg_t me_reserved_2 : 2; + bdrkreg_t me_write_uce : 2; + bdrkreg_t me_reserved_1 : 2; + bdrkreg_t me_read_uce : 2; + bdrkreg_t me_reserved : 1; + bdrkreg_t me_uce_diff_addr : 1; + } md_mem_error_fld_s; +} md_mem_error_u_t; + +#else + +typedef union md_mem_error_u { + bdrkreg_t md_mem_error_regval; + struct { + bdrkreg_t me_uce_diff_addr : 1; + bdrkreg_t me_reserved : 1; + bdrkreg_t me_read_uce : 2; + bdrkreg_t me_reserved_1 : 2; + bdrkreg_t me_write_uce : 2; + bdrkreg_t me_reserved_2 : 2; + bdrkreg_t me_read_ce : 2; + bdrkreg_t me_reserved_3 : 4; + bdrkreg_t me_bad_syn : 8; + bdrkreg_t me_reserved_4 : 7; + bdrkreg_t me_address : 30; + bdrkreg_t me_reserved_5 : 3; + } md_mem_error_fld_s; +} md_mem_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: Contains information on read memory errors (both * + * correctable and uncorrectable) and write memory errors (always * + * uncorrectable). The errors are prioritized as follows: * + * highest: uncorrectable read error (READ_UCE) * + * middle: write error (WRITE_UCE) * + * lowest: correctable read error (READ_CE) * + * Each type of error maintains a two-bit valid/overrun field * + * (READ_UCE, WRITE_UCE, or READ_CE). Bit 0 of each two-bit field * + * corresponds to the valid bit, and bit 1 of each two-bit field * + * corresponds to the overrun bit. * + * The rule for the valid bit is that it gets set whenever that error * + * occurs, regardless of whether a higher priority error has occured. * + * The rule for the overrun bit is that it gets set whenever we are * + * unable to record the address information for this particular * + * error, due to a previous error of the same or higher priority. * + * Note that the syndrome and address information always corresponds * + * to the earliest, highest priority error. * + * Finally, the UCE_DIFF_ADDR bit is set whenever there have been * + * several uncorrectable errors, to different cache line addresses. * + * If all the UCEs were to the same cache line address, then * + * UCE_DIFF_ADDR will be 0. This allows the operating system to * + * detect the case where a UCE error is read exclusively, and then * + * written back by the processor. If the bit is 0, it indicates that * + * no information has been lost about UCEs on other cache lines. In * + * particular, partial writes do a read modify write of the cache * + * line. A UCE read error will be set when the cache line is read, * + * and a UCE write error will occur when the cache line is written * + * back, but the UCE_DIFF_ADDR will not be set. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mem_error_clr_u { + bdrkreg_t md_mem_error_clr_regval; + struct { + bdrkreg_t mec_reserved_5 : 3; + bdrkreg_t mec_address : 30; + bdrkreg_t mec_reserved_4 : 7; + bdrkreg_t mec_bad_syn : 8; + bdrkreg_t mec_reserved_3 : 4; + bdrkreg_t mec_read_ce : 2; + bdrkreg_t mec_reserved_2 : 2; + bdrkreg_t mec_write_uce : 2; + bdrkreg_t mec_reserved_1 : 2; + bdrkreg_t mec_read_uce : 2; + bdrkreg_t mec_reserved : 1; + bdrkreg_t mec_uce_diff_addr : 1; + } md_mem_error_clr_fld_s; +} md_mem_error_clr_u_t; + +#else + +typedef union md_mem_error_clr_u { + bdrkreg_t md_mem_error_clr_regval; + struct { + bdrkreg_t mec_uce_diff_addr : 1; + bdrkreg_t mec_reserved : 1; + bdrkreg_t mec_read_uce : 2; + bdrkreg_t mec_reserved_1 : 2; + bdrkreg_t mec_write_uce : 2; + bdrkreg_t mec_reserved_2 : 2; + bdrkreg_t mec_read_ce : 2; + bdrkreg_t mec_reserved_3 : 4; + bdrkreg_t mec_bad_syn : 8; + bdrkreg_t mec_reserved_4 : 7; + bdrkreg_t mec_address : 30; + bdrkreg_t mec_reserved_5 : 3; + } md_mem_error_clr_fld_s; +} md_mem_error_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains one-quarter of the error memory line failing BIST. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_mb_err_data_0_u { + bdrkreg_t md_bist_mb_err_data_0_regval; + struct { + bdrkreg_t bmed0_mb_er_d : 36; + bdrkreg_t bmed0_reserved : 28; + } md_bist_mb_err_data_0_fld_s; +} md_bist_mb_err_data_0_u_t; + +#else + +typedef union md_bist_mb_err_data_0_u { + bdrkreg_t md_bist_mb_err_data_0_regval; + struct { + bdrkreg_t bmed0_reserved : 28; + bdrkreg_t bmed0_mb_er_d : 36; + } md_bist_mb_err_data_0_fld_s; +} md_bist_mb_err_data_0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains one-quarter of the error memory line failing BIST. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_mb_err_data_1_u { + bdrkreg_t md_bist_mb_err_data_1_regval; + struct { + bdrkreg_t bmed1_mb_er_d : 36; + bdrkreg_t bmed1_reserved : 28; + } md_bist_mb_err_data_1_fld_s; +} md_bist_mb_err_data_1_u_t; + +#else + +typedef union md_bist_mb_err_data_1_u { + bdrkreg_t md_bist_mb_err_data_1_regval; + struct { + bdrkreg_t bmed1_reserved : 28; + bdrkreg_t bmed1_mb_er_d : 36; + } md_bist_mb_err_data_1_fld_s; +} md_bist_mb_err_data_1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains one-quarter of the error memory line failing BIST. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_mb_err_data_2_u { + bdrkreg_t md_bist_mb_err_data_2_regval; + struct { + bdrkreg_t bmed2_mb_er_d : 36; + bdrkreg_t bmed2_reserved : 28; + } md_bist_mb_err_data_2_fld_s; +} md_bist_mb_err_data_2_u_t; + +#else + +typedef union md_bist_mb_err_data_2_u { + bdrkreg_t md_bist_mb_err_data_2_regval; + struct { + bdrkreg_t bmed2_reserved : 28; + bdrkreg_t bmed2_mb_er_d : 36; + } md_bist_mb_err_data_2_fld_s; +} md_bist_mb_err_data_2_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains one-quarter of the error memory line failing BIST. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_bist_mb_err_data_3_u { + bdrkreg_t md_bist_mb_err_data_3_regval; + struct { + bdrkreg_t bmed3_mb_er_d : 36; + bdrkreg_t bmed3_reserved : 28; + } md_bist_mb_err_data_3_fld_s; +} md_bist_mb_err_data_3_u_t; + +#else + +typedef union md_bist_mb_err_data_3_u { + bdrkreg_t md_bist_mb_err_data_3_regval; + struct { + bdrkreg_t bmed3_reserved : 28; + bdrkreg_t bmed3_mb_er_d : 36; + } md_bist_mb_err_data_3_fld_s; +} md_bist_mb_err_data_3_u_t; + +#endif + + + + +/************************************************************************ + * * + * Contains 1 bit that allow the selection of MB debug information * + * at the debug port (see the design specification for the available * + * debug information). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union md_mb_debug_u { + bdrkreg_t md_mb_debug_regval; + struct { + bdrkreg_t md_mb_debug_sel : 1; + bdrkreg_t md_reserved : 63; + } md_mb_debug_fld_s; +} md_mb_debug_u_t; + +#else + +typedef union md_mb_debug_u { + bdrkreg_t md_mb_debug_regval; + struct { + bdrkreg_t md_reserved : 63; + bdrkreg_t md_mb_debug_sel : 1; + } md_mb_debug_fld_s; +} md_mb_debug_u_t; + +#endif + + + + + + +#endif /* _LANGUAGE_C */ + +/************************************************************************ + * * + * MAKE ALL ADDITIONS AFTER THIS LINE * + * * + ************************************************************************/ + + + + +#endif /* _ASM_SN_SN1_HUBMD_H */ diff --git a/include/asm-ia64/sn/sn1/hubmd_next.h b/include/asm-ia64/sn/sn1/hubmd_next.h new file mode 100644 index 000000000..452167d63 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubmd_next.h @@ -0,0 +1,815 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBMD_NEXT_H +#define _ASM_SN_SN1_HUBMD_NEXT_H + +#ifdef BRINGUP +/* XXX moved over from SN/SN0/hubmd.h -- each should be checked for SN1 */ +/* In fact, most of this stuff is wrong. Some is correct, such as + * MD_PAGE_SIZE and MD_PAGE_NUM_SHFT. + */ + +#define MD_PERF_COUNTERS 6 +#define MD_PERF_SETS 6 + +#define MD_SIZE_EMPTY 0 +#define MD_SIZE_64MB 1 +#define MD_SIZE_128MB 2 +#define MD_SIZE_256MB 3 +#define MD_SIZE_512MB 4 +#define MD_SIZE_1GB 5 + +#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x2000000L << (size)) +#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 0x20 << (size)) +#define MD_NUM_ENABLED(_x) ((_x & 0x1) + ((_x >> 1) & 0x1) + \ + ((_x >> 2) & 0x1) + ((_x >> 3) & 0x1)) + + +/* Hardware page size and shift */ + +#define MD_PAGE_SIZE 16384 /* Page size in bytes */ +#define MD_PAGE_NUM_SHFT 14 /* Address to page number shift */ + +#define MMC_IO_PROT (UINT64_CAST 1 << 45) + +/* Register offsets from LOCAL_HUB or REMOTE_HUB */ +#define MD_PERF_SEL 0x210000 /* Select perf monitor events */ + +/* MD_MIG_VALUE_THRESH bit definitions */ + +#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63) +#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff) + +/* MD_MIG_CANDIDATE bit definitions */ + +#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63) +#define MD_MIG_CANDIDATE_VALID_SHFT 63 +#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30) +#define MD_MIG_CANDIDATE_TYPE_SHFT 30 +#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29) +#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29 +#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20) +#define MD_MIG_CANDIDATE_NODEID_SHFT 20 +#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff) + + +/* XXX protection and migration are completely revised on SN1. On + SN0, the reference count and protection fields were accessed in the + same word, but on SN1 they reside at different addresses. The + users of these macros will need to be rewritten. Also, the MD page + size is 16K on SN1 but 4K on SN0. */ + +/* Premium SIMM protection entry shifts and masks. */ + +#define MD_PPROT_SHFT 0 /* Prot. field */ +#define MD_PPROT_MASK 0xf +#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */ +#define MD_PPROT_REFCNT_WIDTH 0x7ffff +#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5) + +#define MD_PPROT_IO_SHFT 8 /* I/O Prot field */ + +/* Standard SIMM protection entry shifts and masks. */ + +#define MD_SPROT_SHFT 0 /* Prot. field */ +#define MD_SPROT_MASK 0xf +#define MD_SPROT_IO_SHFT 8 +#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */ +#define MD_SPROT_REFCNT_WIDTH 0x7ff +#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5) + +/* Migration modes used in protection entries */ + +#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3) +#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3) +#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3) +#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3) + +/* + * Operations on Memory/Directory DIMM control register + */ + +#define DIRTYPE_PREMIUM 1 +#define DIRTYPE_STANDARD 0 + +/* + * Operations on page migration count difference and absolute threshold + * registers + */ + +#define MD_MIG_VALUE_THRESH_GET(region) ( \ + REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \ + MD_MIG_VALUE_THRES_VALUE_MASK) + +#define MD_MIG_VALUE_THRESH_SET(region, value) ( \ + REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ + MD_MIG_VALUE_THRES_VALID_MASK | (value))) + +#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \ + REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \ + REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \ + | MD_MIG_VALUE_THRES_VALID_MASK)) + +/* + * Operations on page migration candidate register + */ + +#define MD_MIG_CANDIDATE_GET(my_region_id) ( \ + REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR)) + +#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK) + +#define MD_MIG_CANDIDATE_NODEID(value) ( \ + ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT) + +#define MD_MIG_CANDIDATE_TYPE(value) ( \ + ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT) + +#define MD_MIG_CANDIDATE_VALID(value) ( \ + ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT) + +/* + * Macros to retrieve fields in the protection entry + */ + +/* for Premium SIMM */ +#define MD_PPROT_REFCNT_GET(value) ( \ + ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT) + +/* for Standard SIMM */ +#define MD_SPROT_REFCNT_GET(value) ( \ + ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT) + +#if _LANGUAGE_C +#ifdef LITTLE_ENDIAN + +typedef union md_perf_sel { + uint64_t perf_sel_reg; + struct { + uint64_t perf_sel : 3, + perf_en : 1, + perf_rsvd : 60; + } perf_sel_bits; +} md_perf_sel_t; + +#else + +typedef union md_perf_sel { + uint64_t perf_sel_reg; + struct { + uint64_t perf_rsvd : 60, + perf_en : 1, + perf_sel : 3; + } perf_sel_bits; +} md_perf_sel_t; + +#endif +#endif /* _LANGUAGE_C */ + +#endif /* BRINGUP */ + +/* Like SN0, SN1 supports a mostly-flat address space with 8 + CPU-visible, evenly spaced, contiguous regions, or "software + banks". On SN1, software bank n begins at addresses n * 1GB, + 0 <= n < 8. + + Physically (and very unlike SN0), each SN1 node board contains 8 + dimm sockets, arranged as 4 "DIMM banks" of 2 dimms each. DIMM + size and width (x4/x8) is assigned per dimm bank. Each DIMM bank + consists of 2 "physical banks", one on the front sides of the 2 + DIMMs and the other on the back sides. Therefore a node has a + total of 8 ( = 4 * 2) physical banks. They are collectively + referred to as "locational banks", since the locational bank number + depends on the physical location of the DIMMs on the board. + + Dimm bank 0, Phys bank 0a (locational bank 0a) + Slot D0 ---------------------------------------------- + Dimm bank 0, Phys bank 1a (locational bank 1a) + + Dimm bank 1, Phys bank 0a (locational bank 2a) + Slot D1 ---------------------------------------------- + Dimm bank 1, Phys bank 1a (locational bank 3a) + + Dimm bank 2, Phys bank 0a (locational bank 4a) + Slot D2 ---------------------------------------------- + Dimm bank 2, Phys bank 1a (locational bank 5a) + + Dimm bank 3, Phys bank 0a (locational bank 6a) + Slot D3 ---------------------------------------------- + Dimm bank 3, Phys bank 1a (locational bank 7a) + + Dimm bank 0, Phys bank 0b (locational bank 0b) + Slot D4 ---------------------------------------------- + Dimm bank 0, Phys bank 1b (locational bank 1b) + + Dimm bank 1, Phys bank 0b (locational bank 2b) + Slot D5 ---------------------------------------------- + Dimm bank 1, Phys bank 1b (locational bank 3b) + + Dimm bank 2, Phys bank 0b (locational bank 4b) + Slot D6 ---------------------------------------------- + Dimm bank 2, Phys bank 1b (locational bank 5b) + + Dimm bank 3, Phys bank 0b (locational bank 6b) + Slot D7 ---------------------------------------------- + Dimm bank 3, Phys bank 1b (locational bank 7b) + + Since bank size is assigned per DIMM bank, each pair of locational + banks must have the same size. However, they may be + enabled/disabled individually. + + The locational banks map to the software banks via the dimm0_sel + field in MD_MEMORY_CONFIG. When the field is 0 (the usual case), + the mapping is direct: eg. locational bank 1 (dimm bank 0, + physical bank 1, which is the back side of the first DIMM pair) + corresponds to software bank 1, at node offset 1GB. More + generally, locational bank = software bank XOR dimm0_sel. + + All the PROM's data structures (promlog variables, klconfig, etc.) + track memory by the locational bank number. The kernel usually + tracks memory by the software bank number. + memsupport.c:slot_psize_compute() performs the mapping. + + (Note: the terms "locational bank" and "software bank" are not + offical in any way, but I've tried to make the PROM use them + consistently -- bjj.) + */ + +#define MD_MEM_BANKS 8 +#define MD_MEM_DIMM_BANKS 4 +#define MD_BANK_SHFT 30 /* log2(1 GB) */ +#define MD_BANK_MASK (UINT64_CAST 0x7 << 30) +#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 1 GB */ +#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) +#define MD_BANK_GET(addr) (((addr) & MD_BANK_MASK) >> MD_BANK_SHFT) +#define MD_BANK_TO_DIMM_BANK(_b) (( (_b) >> 1) & 0x3) +#define MD_BANK_TO_PHYS_BANK(_b) (( (_b) >> 0) & 0x1) +#define MD_DIMM_BANK_GET(addr) MD_BANK_TO_DIMM_BANK(MD_BANK_GET(addr)) +#define MD_PHYS_BANK_GET(addr) MD_BANK_TO_PHYS_BANK(MD_BANK_GET(addr)) + + +/* Split an MD pointer (or message source & suppl. fields) into node, device */ + +#define MD_PTR_NODE_SHFT 3 +#define MD_PTR_DEVICE_MASK 0x7 +#define MD_PTR_SUBNODE0_MASK 0x1 +#define MD_PTR_SUBNODE1_MASK 0x4 + + +/********************************************************************** + + Backdoor protection and page counter structures + +**********************************************************************/ + +/* Protection entries and page counters are interleaved at 4 separate + addresses, 0x10 apart. Software must read/write all four. */ + +#define BD_ITLV_COUNT 4 +#define BD_ITLV_STRIDE 0x10 + +/* Protection entries */ + +/* (these macros work for standard (_rgn < 32) or premium DIMMs) */ +#define MD_PROT_SHFT(_rgn, _io) ((((_rgn) & 0x20) >> 2 | \ + ((_rgn) & 0x01) << 2 | \ + ((_io) & 0x1) << 1) * 8) +#define MD_PROT_MASK(_rgn, _io) (0xff << MD_PROT_SHFT(_rgn, _io)) +#define MD_PROT_GET(_val, _rgn, _io) \ + (((_val) & MD_PROT_MASK(_rgn, _io)) >> MD_PROT_SHFT(_rgn, _io)) + +/* Protection field values */ + +#define MD_PROT_RW (UINT64_CAST 0xff) +#define MD_PROT_RO (UINT64_CAST 0x0f) +#define MD_PROT_NO (UINT64_CAST 0x00) + + + + +/********************************************************************** + + Directory format structures + +***********************************************************************/ + +#ifdef _LANGUAGE_C + +/* Standard Directory Entries */ + +#ifdef LITTLE_ENDIAN + +struct md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ + bdrkreg_t sdp_format : 2; + bdrkreg_t sdp_state : 3; + bdrkreg_t sdp_priority : 3; + bdrkreg_t sdp_pointer1 : 8; + bdrkreg_t sdp_ecc : 6; + bdrkreg_t sdp_locprot : 1; + bdrkreg_t sdp_reserved : 1; + bdrkreg_t sdp_crit_word_off : 3; + bdrkreg_t sdp_pointer2 : 5; + bdrkreg_t sdp_fill : 32; +}; + +#else + +struct md_sdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ + bdrkreg_t sdp_fill : 32; + bdrkreg_t sdp_pointer2 : 5; + bdrkreg_t sdp_crit_word_off : 3; + bdrkreg_t sdp_reserved : 1; + bdrkreg_t sdp_locprot : 1; + bdrkreg_t sdp_ecc : 6; + bdrkreg_t sdp_pointer1 : 8; + bdrkreg_t sdp_priority : 3; + bdrkreg_t sdp_state : 3; + bdrkreg_t sdp_format : 2; +}; + +#endif + +#ifdef LITTLE_ENDIAN + +struct md_sdir_fine_fmt { /* shared (fine) */ + bdrkreg_t sdf_format : 2; + bdrkreg_t sdf_tag1 : 3; + bdrkreg_t sdf_tag2 : 3; + bdrkreg_t sdf_vector1 : 8; + bdrkreg_t sdf_ecc : 6; + bdrkreg_t sdf_locprot : 1; + bdrkreg_t sdf_tag2valid : 1; + bdrkreg_t sdf_vector2 : 8; + bdrkreg_t sdf_fill : 32; +}; + +#else + +struct md_sdir_fine_fmt { /* shared (fine) */ + bdrkreg_t sdf_fill : 32; + bdrkreg_t sdf_vector2 : 8; + bdrkreg_t sdf_tag2valid : 1; + bdrkreg_t sdf_locprot : 1; + bdrkreg_t sdf_ecc : 6; + bdrkreg_t sdf_vector1 : 8; + bdrkreg_t sdf_tag2 : 3; + bdrkreg_t sdf_tag1 : 3; + bdrkreg_t sdf_format : 2; +}; + +#endif + +#ifdef LITTLE_ENDIAN + +struct md_sdir_coarse_fmt { /* shared (coarse) */ + bdrkreg_t sdc_format : 2; + bdrkreg_t sdc_reserved_1 : 6; + bdrkreg_t sdc_vector_a : 8; + bdrkreg_t sdc_ecc : 6; + bdrkreg_t sdc_locprot : 1; + bdrkreg_t sdc_reserved : 1; + bdrkreg_t sdc_vector_b : 8; + bdrkreg_t sdc_fill : 32; +}; + +#else + +struct md_sdir_coarse_fmt { /* shared (coarse) */ + bdrkreg_t sdc_fill : 32; + bdrkreg_t sdc_vector_b : 8; + bdrkreg_t sdc_reserved : 1; + bdrkreg_t sdc_locprot : 1; + bdrkreg_t sdc_ecc : 6; + bdrkreg_t sdc_vector_a : 8; + bdrkreg_t sdc_reserved_1 : 6; + bdrkreg_t sdc_format : 2; +}; + +#endif + +typedef union md_sdir { + /* The 32 bits of standard directory, in bits 31:0 */ + uint64_t sd_val; + struct md_sdir_pointer_fmt sdp_fmt; + struct md_sdir_fine_fmt sdf_fmt; + struct md_sdir_coarse_fmt sdc_fmt; +} md_sdir_t; + + +/* Premium Directory Entries */ + +#ifdef LITTLE_ENDIAN + +struct md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ + bdrkreg_t pdp_format : 2; + bdrkreg_t pdp_state : 3; + bdrkreg_t pdp_priority : 3; + bdrkreg_t pdp_pointer1_a : 8; + bdrkreg_t pdp_reserved_4 : 6; + bdrkreg_t pdp_pointer1_b : 3; + bdrkreg_t pdp_reserved_3 : 7; + bdrkreg_t pdp_ecc_a : 6; + bdrkreg_t pdp_locprot : 1; + bdrkreg_t pdp_reserved_2 : 1; + bdrkreg_t pdp_crit_word_off : 3; + bdrkreg_t pdp_pointer2_a : 5; + bdrkreg_t pdp_ecc_b : 1; + bdrkreg_t pdp_reserved_1 : 5; + bdrkreg_t pdp_pointer2_b : 3; + bdrkreg_t pdp_reserved : 7; +}; + +#else + +struct md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */ + bdrkreg_t pdp_reserved : 7; + bdrkreg_t pdp_pointer2_b : 3; + bdrkreg_t pdp_reserved_1 : 5; + bdrkreg_t pdp_ecc_b : 1; + bdrkreg_t pdp_pointer2_a : 5; + bdrkreg_t pdp_crit_word_off : 3; + bdrkreg_t pdp_reserved_2 : 1; + bdrkreg_t pdp_locprot : 1; + bdrkreg_t pdp_ecc_a : 6; + bdrkreg_t pdp_reserved_3 : 7; + bdrkreg_t pdp_pointer1_b : 3; + bdrkreg_t pdp_reserved_4 : 6; + bdrkreg_t pdp_pointer1_a : 8; + bdrkreg_t pdp_priority : 3; + bdrkreg_t pdp_state : 3; + bdrkreg_t pdp_format : 2; +}; + +#endif + +#ifdef LITTLE_ENDIAN + +struct md_pdir_fine_fmt { /* shared (fine) */ + bdrkreg_t pdf_format : 2; + bdrkreg_t pdf_tag1_a : 3; + bdrkreg_t pdf_tag2_a : 3; + bdrkreg_t pdf_vector1_a : 8; + bdrkreg_t pdf_reserved_1 : 6; + bdrkreg_t pdf_tag1_b : 2; + bdrkreg_t pdf_vector1_b : 8; + bdrkreg_t pdf_ecc_a : 6; + bdrkreg_t pdf_locprot : 1; + bdrkreg_t pdf_tag2valid : 1; + bdrkreg_t pdf_vector2_a : 8; + bdrkreg_t pdf_ecc_b : 1; + bdrkreg_t pdf_reserved : 5; + bdrkreg_t pdf_tag2_b : 2; + bdrkreg_t pdf_vector2_b : 8; +}; + +#else + +struct md_pdir_fine_fmt { /* shared (fine) */ + bdrkreg_t pdf_vector2_b : 8; + bdrkreg_t pdf_tag2_b : 2; + bdrkreg_t pdf_reserved : 5; + bdrkreg_t pdf_ecc_b : 1; + bdrkreg_t pdf_vector2_a : 8; + bdrkreg_t pdf_tag2valid : 1; + bdrkreg_t pdf_locprot : 1; + bdrkreg_t pdf_ecc_a : 6; + bdrkreg_t pdf_vector1_b : 8; + bdrkreg_t pdf_tag1_b : 2; + bdrkreg_t pdf_reserved_1 : 6; + bdrkreg_t pdf_vector1_a : 8; + bdrkreg_t pdf_tag2_a : 3; + bdrkreg_t pdf_tag1_a : 3; + bdrkreg_t pdf_format : 2; +}; + +#endif + +#ifdef LITTLE_ENDIAN + +struct md_pdir_sparse_fmt { /* shared (sparse) */ + bdrkreg_t pds_format : 2; + bdrkreg_t pds_column_a : 6; + bdrkreg_t pds_row_a : 8; + bdrkreg_t pds_column_b : 16; + bdrkreg_t pds_ecc_a : 6; + bdrkreg_t pds_locprot : 1; + bdrkreg_t pds_reserved_1 : 1; + bdrkreg_t pds_row_b : 8; + bdrkreg_t pds_ecc_b : 1; + bdrkreg_t pds_column_c : 10; + bdrkreg_t pds_reserved : 5; +}; + +#else + +struct md_pdir_sparse_fmt { /* shared (sparse) */ + bdrkreg_t pds_reserved : 5; + bdrkreg_t pds_column_c : 10; + bdrkreg_t pds_ecc_b : 1; + bdrkreg_t pds_row_b : 8; + bdrkreg_t pds_reserved_1 : 1; + bdrkreg_t pds_locprot : 1; + bdrkreg_t pds_ecc_a : 6; + bdrkreg_t pds_column_b : 16; + bdrkreg_t pds_row_a : 8; + bdrkreg_t pds_column_a : 6; + bdrkreg_t pds_format : 2; +}; + +#endif + +typedef union md_pdir { + /* The 64 bits of premium directory */ + uint64_t pd_val; + struct md_pdir_pointer_fmt pdp_fmt; + struct md_pdir_fine_fmt pdf_fmt; + struct md_pdir_sparse_fmt pds_fmt; +} md_pdir_t; + +#endif /* _LANGUAGE_C */ + + +/********************************************************************** + + The defines for backdoor directory and backdoor ECC. + +***********************************************************************/ + +/* Directory formats, for each format's "format" field */ + +#define MD_FORMAT_UNOWNED (UINT64_CAST 0x0) /* 00 */ +#define MD_FORMAT_POINTER (UINT64_CAST 0x1) /* 01 */ +#define MD_FORMAT_SHFINE (UINT64_CAST 0x2) /* 10 */ +#define MD_FORMAT_SHCOARSE (UINT64_CAST 0x3) /* 11 */ + /* Shared coarse (standard) and shared sparse (premium) both use fmt 0x3 */ + + +/* + * Cacheline state values. + * + * These are really *software* notions of the "state" of a cacheline; but the + * actual values have been carefully chosen to align with some hardware values! + * The MD_FMT_ST_TO_STATE macro is used to convert from hardware format/state + * pairs in the directory entried into one of these cacheline state values. + */ + +#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x0) /* ptr format, hw-defined */ +#define MD_DIR_UNOWNED (UINT64_CAST 0x1) /* format=0 */ +#define MD_DIR_SHARED (UINT64_CAST 0x2) /* format=2,3 */ +#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x4) /* ptr format, hw-defined */ +#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x5) /* ptr format, hw-defined */ +#define MD_DIR_WAIT (UINT64_CAST 0x6) /* ptr format, hw-defined */ +#define MD_DIR_POISONED (UINT64_CAST 0x7) /* ptr format, hw-defined */ + +#ifdef _LANGUAGE_C + +/* Convert format and state fields into a single "cacheline state" value, defined above */ + +#define MD_FMT_ST_TO_STATE(fmt, state) \ + ((fmt) == MD_FORMAT_POINTER ? (state) : \ + (fmt) == MD_FORMAT_UNOWNED ? MD_DIR_UNOWNED : \ + MD_DIR_SHARED) +#define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x)) + +#endif /* _LANGUAGE_C */ + + + +/* Directory field shifts and masks */ + +/* Standard */ + +#define MD_SDIR_FORMAT_SHFT 0 /* All formats */ +#define MD_SDIR_FORMAT_MASK (0x3 << 0) +#define MD_SDIR_STATE_SHFT 2 /* Pointer fmt. only */ +#define MD_SDIR_STATE_MASK (0x7 << 2) + +/* Premium */ + +#define MD_PDIR_FORMAT_SHFT 0 /* All formats */ +#define MD_PDIR_FORMAT_MASK (0x3 << 0) +#define MD_PDIR_STATE_SHFT 2 /* Pointer fmt. only */ +#define MD_PDIR_STATE_MASK (0x7 << 2) + +/* Generic */ + +#define MD_FORMAT_SHFT 0 /* All formats */ +#define MD_FORMAT_MASK (0x3 << 0) +#define MD_STATE_SHFT 2 /* Pointer fmt. only */ +#define MD_STATE_MASK (0x7 << 2) + + +/* Special shifts to reconstruct fields from the _a and _b parts */ + +/* Standard: only shared coarse has split fields */ + +#define MD_SDC_VECTORB_SHFT 8 /* eg: sdc_vector_a is 8 bits */ + +/* Premium: pointer, shared fine, shared sparse */ + +#define MD_PDP_POINTER1A_MASK 0xFF +#define MD_PDP_POINTER1B_SHFT 8 +#define MD_PDP_POINTER2B_SHFT 5 +#define MD_PDP_ECCB_SHFT 6 + +#define MD_PDF_VECTOR1B_SHFT 8 +#define MD_PDF_VECTOR2B_SHFT 8 +#define MD_PDF_TAG1B_SHFT 3 +#define MD_PDF_TAG2B_SHFT 3 +#define MD_PDF_ECC_SHFT 6 + +#define MD_PDS_ROWB_SHFT 8 +#define MD_PDS_COLUMNB_SHFT 6 +#define MD_PDS_COLUMNC_SHFT (MD_PDS_COLUMNB_SHFT + 16) +#define MD_PDS_ECC_SHFT 6 + + + +/* + * Directory/protection/counter initialization values, premium and standard + */ + +#define MD_PDIR_INIT 0 +#define MD_PDIR_INIT_CNT 0 +#define MD_PDIR_INIT_PROT 0 + +#define MD_SDIR_INIT 0 +#define MD_SDIR_INIT_CNT 0 +#define MD_SDIR_INIT_PROT 0 + +#define MD_PDIR_MASK 0xffffffffffffffff +#define MD_SDIR_MASK 0xffffffff + +/* When premium mode is on for probing but standard directory memory + is installed, the vaild directory bits depend on the phys. bank */ +#define MD_PDIR_PROBE_MASK(pb) 0xffffffffffffffff +#define MD_SDIR_PROBE_MASK(pb) (0xffff0000ffff << ((pb) ? 16 : 0)) + + +/* + * Misc. field extractions and conversions + */ + +/* Convert an MD pointer (or message source, supplemental fields) */ + +#define MD_PTR_NODE(x) ((x) >> MD_PTR_NODE_SHFT) +#define MD_PTR_DEVICE(x) ((x) & MD_PTR_DEVICE_MASK) +#define MD_PTR_SLICE(x) (((x) & MD_PTR_SUBNODE0_MASK) | \ + ((x) & MD_PTR_SUBNODE1_MASK) >> 1) +#define MD_PTR_OWNER_CPU(x) (! ((x) & 2)) +#define MD_PTR_OWNER_IO(x) ((x) & 2) + +/* Extract format and raw state from a directory entry */ + +#define MD_DIR_FORMAT(x) ((x) >> MD_SDIR_FORMAT_SHFT & \ + MD_SDIR_FORMAT_MASK >> MD_SDIR_FORMAT_SHFT) +#define MD_DIR_STVAL(x) ((x) >> MD_SDIR_STATE_SHFT & \ + MD_SDIR_STATE_MASK >> MD_SDIR_STATE_SHFT) + +/* Mask & Shift to get HSPEC_ADDR from MD DIR_ERROR register */ +#define ERROR_ADDR_SHFT 3 +#define ERROR_HSPEC_SHFT 3 +#define DIR_ERR_HSPEC_MASK 0x1fffffff8 + +/* + * DIR_ERR* and MEM_ERR* defines are used to avoid ugly + * #ifdefs for SN0 and SN1 in memerror.c code. See SN0/hubmd.h + * for corresponding SN0 definitions. + */ +#define md_dir_error_t md_dir_error_u_t +#define md_mem_error_t md_mem_error_u_t +#define derr_reg md_dir_error_regval +#define merr_reg md_mem_error_regval + +#define DIR_ERR_UCE_VALID dir_err.md_dir_error_fld_s.de_uce_valid +#define DIR_ERR_AE_VALID dir_err.md_dir_error_fld_s.de_ae_valid +#define DIR_ERR_BAD_SYN dir_err.md_dir_error_fld_s.de_bad_syn +#define DIR_ERR_CE_OVERRUN dir_err.md_dir_error_fld_s.de_ce_overrun +#define MEM_ERR_ADDRESS mem_err.md_mem_error_fld_s.me_address + /* BRINGUP Can the overrun bit be set without the valid bit? */ +#define MEM_ERR_CE_OVERRUN (mem_err.md_mem_error_fld_s.me_read_ce >> 1) +#define MEM_ERR_BAD_SYN mem_err.md_mem_error_fld_s.me_bad_syn +#define MEM_ERR_UCE_VALID (mem_err.md_mem_error_fld_s.me_read_uce & 1) + + + +/********************************************************************* + + We have the shift and masks of various fields defined below. + + *********************************************************************/ + +/* MD_REFRESH_CONTROL fields */ + +#define MRC_ENABLE_SHFT 63 +#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63) +#define MRC_ENABLE (UINT64_CAST 1 << 63) +#define MRC_COUNTER_SHFT 12 +#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12) +#define MRC_CNT_THRESH_MASK 0xfff +#define MRC_RESET_DEFAULTS (UINT64_CAST 0x800) + +/* MD_DIR_CONFIG fields */ + +#define MDC_DIR_PREMIUM (UINT64_CAST 1 << 0) +#define MDC_IGNORE_ECC_SHFT 1 +#define MDC_IGNORE_ECC_MASK (UINT64_CAST 1 << 1) + +/* MD_MEMORY_CONFIG fields */ + +#define MMC_RP_CONFIG_SHFT 61 +#define MMC_RP_CONFIG_MASK (UINT64_CAST 1 << 61) +#define MMC_RCD_CONFIG_SHFT 60 +#define MMC_RCD_CONFIG_MASK (UINT64_CAST 1 << 60) +#define MMC_MB_NEG_EDGE_SHFT 56 +#define MMC_MB_NEG_EDGE_MASK (UINT64_CAST 0x7 << 56) +#define MMC_SAMPLE_TIME_SHFT 52 +#define MMC_SAMPLE_TIME_MASK (UINT64_CAST 0x3 << 52) +#define MMC_DELAY_MUX_SEL_SHFT 50 +#define MMC_DELAY_MUX_SEL_MASK (UINT64_CAST 0x3 << 50) +#define MMC_PHASE_DELAY_SHFT 49 +#define MMC_PHASE_DELAY_MASK (UINT64_CAST 1 << 49) +#define MMC_DB_NEG_EDGE_SHFT 48 +#define MMC_DB_NEG_EDGE_MASK (UINT64_CAST 1 << 48) +#define MMC_CPU_PROT_IGNORE_SHFT 47 +#define MMC_CPU_PROT_IGNORE_MASK (UINT64_CAST 1 << 47) +#define MMC_IO_PROT_IGNORE_SHFT 46 +#define MMC_IO_PROT_IGNORE_MASK (UINT64_CAST 1 << 46) +#define MMC_IO_PROT_EN_SHFT 45 +#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 45) +#define MMC_CC_ENABLE_SHFT 44 +#define MMC_CC_ENABLE_MASK (UINT64_CAST 1 << 44) +#define MMC_DIMM0_SEL_SHFT 32 +#define MMC_DIMM0_SEL_MASK (UINT64_CAST 0x3 << 32) +#define MMC_DIMM_SIZE_SHFT(_dimm) ((_dimm << 3) + 4) +#define MMC_DIMM_SIZE_MASK(_dimm) (UINT64_CAST 0xf << MMC_DIMM_SIZE_SHFT(_dimm)) +#define MMC_DIMM_WIDTH_SHFT(_dimm) ((_dimm << 3) + 3) +#define MMC_DIMM_WIDTH_MASK(_dimm) (UINT64_CAST 0x1 << MMC_DIMM_WIDTH_SHFT(_dimm)) +#define MMC_DIMM_BANKS_SHFT(_dimm) (_dimm << 3) +#define MMC_DIMM_BANKS_MASK(_dimm) (UINT64_CAST 0x3 << MMC_DIMM_BANKS_SHFT(_dimm)) +#define MMC_BANK_ALL_MASK 0xffffffffLL +/* Default values for write-only bits in MD_MEMORY_CONFIG */ +#define MMC_DEFAULT_BITS (UINT64_CAST 0x7 << MMC_MB_NEG_EDGE_SHFT) + +/* MD_MB_ECC_CONFIG fields */ + +#define MEC_IGNORE_ECC (UINT64_CAST 0x1 << 0) + +/* MD_BIST_DATA fields */ + +#define MBD_BIST_WRITE (UINT64_CAST 1 << 7) +#define MBD_BIST_CYCLE (UINT64_CAST 1 << 6) +#define MBD_BIST_BYTE (UINT64_CAST 1 << 5) +#define MBD_BIST_NIBBLE (UINT64_CAST 1 << 4) +#define MBD_BIST_DATA_MASK 0xf + +/* MD_BIST_CTL fields */ + +#define MBC_DIMM_SHFT 5 +#define MBC_DIMM_MASK (UINT64_CAST 0x3 << 5) +#define MBC_BANK_SHFT 4 +#define MBC_BANK_MASK (UINT64_CAST 0x1 << 4) +#define MBC_BIST_RESET (UINT64_CAST 0x1 << 2) +#define MBC_BIST_STOP (UINT64_CAST 0x1 << 1) +#define MBC_BIST_START (UINT64_CAST 0x1 << 0) + +#define MBC_GO(dimm, bank) \ + (((dimm) << MBC_DIMM_SHFT) & MBC_DIMM_MASK | \ + ((bank) << MBC_BANK_SHFT) & MBC_BANK_MASK | \ + MBC_BIST_START) + +/* MD_BIST_STATUS fields */ + +#define MBS_BIST_DONE (UINT64_CAST 0X1 << 1) +#define MBS_BIST_PASSED (UINT64_CAST 0X1 << 0) + +/* MD_JUNK_BUS_TIMING fields */ + +#define MJT_SYNERGY_ENABLE_SHFT 40 +#define MJT_SYNERGY_ENABLE_MASK (UINT64_CAST 0Xff << MJT_SYNERGY_ENABLE_SHFT) +#define MJT_SYNERGY_SETUP_SHFT 32 +#define MJT_SYNERGY_SETUP_MASK (UINT64_CAST 0Xff << MJT_SYNERGY_SETUP_SHFT) +#define MJT_UART_ENABLE_SHFT 24 +#define MJT_UART_ENABLE_MASK (UINT64_CAST 0Xff << MJT_UART_ENABLE_SHFT) +#define MJT_UART_SETUP_SHFT 16 +#define MJT_UART_SETUP_MASK (UINT64_CAST 0Xff << MJT_UART_SETUP_SHFT) +#define MJT_FPROM_ENABLE_SHFT 8 +#define MJT_FPROM_ENABLE_MASK (UINT64_CAST 0Xff << MJT_FPROM_ENABLE_SHFT) +#define MJT_FPROM_SETUP_SHFT 0 +#define MJT_FPROM_SETUP_MASK (UINT64_CAST 0Xff << MJT_FPROM_SETUP_SHFT) + +#define MEM_ERROR_VALID_CE 1 + + +/* MD_FANDOP_CAC_STAT0, MD_FANDOP_CAC_STAT1 addr field shift */ + +#define MFC_ADDR_SHFT 6 + +#endif /* _ASM_SN_SN1_HUBMD_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubni.h b/include/asm-ia64/sn/sn1/hubni.h new file mode 100644 index 000000000..018aa9de6 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubni.h @@ -0,0 +1,1782 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBNI_H +#define _ASM_SN_SN1_HUBNI_H + + +/************************************************************************ + * * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * + * * + * This file is created by an automated script. Any (minimal) changes * + * made manually to this file should be made with care. * + * * + * MAKE ALL ADDITIONS TO THE END OF THIS FILE * + * * + ************************************************************************/ + +#define NI_PORT_STATUS 0x00680000 /* LLP Status */ + + + +#define NI_PORT_RESET 0x00680008 /* + * Reset the Network + * Interface + */ + + + +#define NI_RESET_ENABLE 0x00680010 /* Warm Reset Enable */ + + + +#define NI_DIAG_PARMS 0x00680018 /* + * Diagnostic + * Parameters + */ + + + +#define NI_CHANNEL_CONTROL 0x00680020 /* + * Virtual channel + * control + */ + + + +#define NI_CHANNEL_TEST 0x00680028 /* LLP Test Control. */ + + + +#define NI_PORT_PARMS 0x00680030 /* LLP Parameters */ + + + +#define NI_CHANNEL_AGE 0x00680038 /* + * Network age + * injection control + */ + + + +#define NI_PORT_ERRORS 0x00680100 /* Errors */ + + + +#define NI_PORT_HEADER_A 0x00680108 /* + * Error Header first + * half + */ + + + +#define NI_PORT_HEADER_B 0x00680110 /* + * Error Header second + * half + */ + + + +#define NI_PORT_SIDEBAND 0x00680118 /* Error Sideband */ + + + +#define NI_PORT_ERROR_CLEAR 0x00680120 /* + * Clear the Error + * bits + */ + + + +#define NI_LOCAL_TABLE_0 0x00681000 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_1 0x00681008 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_2 0x00681010 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_3 0x00681018 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_4 0x00681020 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_5 0x00681028 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_6 0x00681030 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_7 0x00681038 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_8 0x00681040 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_9 0x00681048 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_10 0x00681050 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_11 0x00681058 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_12 0x00681060 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_13 0x00681068 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_14 0x00681070 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_15 0x00681078 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_16 0x00681080 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_17 0x00681088 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_18 0x00681090 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_19 0x00681098 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_20 0x006810A0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_21 0x006810A8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_22 0x006810B0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_23 0x006810B8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_24 0x006810C0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_25 0x006810C8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_26 0x006810D0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_27 0x006810D8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_28 0x006810E0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_29 0x006810E8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_30 0x006810F0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_31 0x006810F8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_32 0x00681100 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_33 0x00681108 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_34 0x00681110 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_35 0x00681118 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_36 0x00681120 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_37 0x00681128 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_38 0x00681130 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_39 0x00681138 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_40 0x00681140 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_41 0x00681148 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_42 0x00681150 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_43 0x00681158 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_44 0x00681160 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_45 0x00681168 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_46 0x00681170 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_47 0x00681178 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_48 0x00681180 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_49 0x00681188 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_50 0x00681190 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_51 0x00681198 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_52 0x006811A0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_53 0x006811A8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_54 0x006811B0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_55 0x006811B8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_56 0x006811C0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_57 0x006811C8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_58 0x006811D0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_59 0x006811D8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_60 0x006811E0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_61 0x006811E8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_62 0x006811F0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_63 0x006811F8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_64 0x00681200 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_65 0x00681208 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_66 0x00681210 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_67 0x00681218 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_68 0x00681220 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_69 0x00681228 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_70 0x00681230 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_71 0x00681238 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_72 0x00681240 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_73 0x00681248 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_74 0x00681250 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_75 0x00681258 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_76 0x00681260 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_77 0x00681268 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_78 0x00681270 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_79 0x00681278 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_80 0x00681280 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_81 0x00681288 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_82 0x00681290 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_83 0x00681298 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_84 0x006812A0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_85 0x006812A8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_86 0x006812B0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_87 0x006812B8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_88 0x006812C0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_89 0x006812C8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_90 0x006812D0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_91 0x006812D8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_92 0x006812E0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_93 0x006812E8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_94 0x006812F0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_95 0x006812F8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_96 0x00681300 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_97 0x00681308 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_98 0x00681310 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_99 0x00681318 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_100 0x00681320 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_101 0x00681328 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_102 0x00681330 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_103 0x00681338 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_104 0x00681340 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_105 0x00681348 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_106 0x00681350 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_107 0x00681358 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_108 0x00681360 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_109 0x00681368 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_110 0x00681370 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_111 0x00681378 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_112 0x00681380 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_113 0x00681388 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_114 0x00681390 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_115 0x00681398 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_116 0x006813A0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_117 0x006813A8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_118 0x006813B0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_119 0x006813B8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_120 0x006813C0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_121 0x006813C8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_122 0x006813D0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_123 0x006813D8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_124 0x006813E0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_125 0x006813E8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_126 0x006813F0 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_LOCAL_TABLE_127 0x006813F8 /* + * Base of Local + * Mapping Table 0-127 + */ + + + +#define NI_GLOBAL_TABLE 0x00682000 /* + * Base of Global + * Mapping Table + */ + + + + + +#ifdef _LANGUAGE_C + +/************************************************************************ + * * + * This register describes the LLP status. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_status_u { + bdrkreg_t ni_port_status_regval; + struct { + bdrkreg_t ps_port_status : 2; + bdrkreg_t ps_remote_power : 1; + bdrkreg_t ps_rsvd : 61; + } ni_port_status_fld_s; +} ni_port_status_u_t; + +#else + +typedef union ni_port_status_u { + bdrkreg_t ni_port_status_regval; + struct { + bdrkreg_t ps_rsvd : 61; + bdrkreg_t ps_remote_power : 1; + bdrkreg_t ps_port_status : 2; + } ni_port_status_fld_s; +} ni_port_status_u_t; + +#endif + + + + +/************************************************************************ + * * + * Writing this register issues a reset to the network interface. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_reset_u { + bdrkreg_t ni_port_reset_regval; + struct { + bdrkreg_t pr_link_reset_out : 1; + bdrkreg_t pr_port_reset : 1; + bdrkreg_t pr_local_reset : 1; + bdrkreg_t pr_rsvd : 61; + } ni_port_reset_fld_s; +} ni_port_reset_u_t; + +#else + +typedef union ni_port_reset_u { + bdrkreg_t ni_port_reset_regval; + struct { + bdrkreg_t pr_rsvd : 61; + bdrkreg_t pr_local_reset : 1; + bdrkreg_t pr_port_reset : 1; + bdrkreg_t pr_link_reset_out : 1; + } ni_port_reset_fld_s; +} ni_port_reset_u_t; + +#endif + + + +/************************************************************************ + * * + * This register contains the warm reset enable bit. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_reset_enable_u { + bdrkreg_t ni_reset_enable_regval; + struct { + bdrkreg_t re_reset_ok : 1; + bdrkreg_t re_rsvd : 63; + } ni_reset_enable_fld_s; +} ni_reset_enable_u_t; + +#else + +typedef union ni_reset_enable_u { + bdrkreg_t ni_reset_enable_regval; + struct { + bdrkreg_t re_rsvd : 63; + bdrkreg_t re_reset_ok : 1; + } ni_reset_enable_fld_s; +} ni_reset_enable_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains parameters for diagnostics. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_diag_parms_u { + bdrkreg_t ni_diag_parms_regval; + struct { + bdrkreg_t dp_send_data_error : 1; + bdrkreg_t dp_port_disable : 1; + bdrkreg_t dp_send_err_off : 1; + bdrkreg_t dp_rsvd : 61; + } ni_diag_parms_fld_s; +} ni_diag_parms_u_t; + +#else + +typedef union ni_diag_parms_u { + bdrkreg_t ni_diag_parms_regval; + struct { + bdrkreg_t dp_rsvd : 61; + bdrkreg_t dp_send_err_off : 1; + bdrkreg_t dp_port_disable : 1; + bdrkreg_t dp_send_data_error : 1; + } ni_diag_parms_fld_s; +} ni_diag_parms_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the virtual channel selection control for * + * outgoing messages from the Bedrock. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_channel_control_u { + bdrkreg_t ni_channel_control_regval; + struct { + bdrkreg_t cc_vch_one_request : 1; + bdrkreg_t cc_vch_two_request : 1; + bdrkreg_t cc_vch_nine_request : 1; + bdrkreg_t cc_vch_vector_request : 1; + bdrkreg_t cc_vch_one_reply : 1; + bdrkreg_t cc_vch_two_reply : 1; + bdrkreg_t cc_vch_nine_reply : 1; + bdrkreg_t cc_vch_vector_reply : 1; + bdrkreg_t cc_send_vch_sel : 1; + bdrkreg_t cc_rsvd : 55; + } ni_channel_control_fld_s; +} ni_channel_control_u_t; + +#else + +typedef union ni_channel_control_u { + bdrkreg_t ni_channel_control_regval; + struct { + bdrkreg_t cc_rsvd : 55; + bdrkreg_t cc_send_vch_sel : 1; + bdrkreg_t cc_vch_vector_reply : 1; + bdrkreg_t cc_vch_nine_reply : 1; + bdrkreg_t cc_vch_two_reply : 1; + bdrkreg_t cc_vch_one_reply : 1; + bdrkreg_t cc_vch_vector_request : 1; + bdrkreg_t cc_vch_nine_request : 1; + bdrkreg_t cc_vch_two_request : 1; + bdrkreg_t cc_vch_one_request : 1; + } ni_channel_control_fld_s; +} ni_channel_control_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register allows access to the LLP test logic. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_channel_test_u { + bdrkreg_t ni_channel_test_regval; + struct { + bdrkreg_t ct_testseed : 20; + bdrkreg_t ct_testmask : 8; + bdrkreg_t ct_testdata : 20; + bdrkreg_t ct_testvalid : 1; + bdrkreg_t ct_testcberr : 1; + bdrkreg_t ct_testflit : 3; + bdrkreg_t ct_testclear : 1; + bdrkreg_t ct_testerrcapture : 1; + bdrkreg_t ct_rsvd : 9; + } ni_channel_test_fld_s; +} ni_channel_test_u_t; + +#else + +typedef union ni_channel_test_u { + bdrkreg_t ni_channel_test_regval; + struct { + bdrkreg_t ct_rsvd : 9; + bdrkreg_t ct_testerrcapture : 1; + bdrkreg_t ct_testclear : 1; + bdrkreg_t ct_testflit : 3; + bdrkreg_t ct_testcberr : 1; + bdrkreg_t ct_testvalid : 1; + bdrkreg_t ct_testdata : 20; + bdrkreg_t ct_testmask : 8; + bdrkreg_t ct_testseed : 20; + } ni_channel_test_fld_s; +} ni_channel_test_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains LLP port parameters and enables for the * + * capture of header data. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_parms_u { + bdrkreg_t ni_port_parms_regval; + struct { + bdrkreg_t pp_max_burst : 10; + bdrkreg_t pp_null_timeout : 6; + bdrkreg_t pp_max_retry : 10; + bdrkreg_t pp_d_avail_sel : 2; + bdrkreg_t pp_rsvd_1 : 1; + bdrkreg_t pp_first_err_enable : 1; + bdrkreg_t pp_squash_err_enable : 1; + bdrkreg_t pp_vch_err_enable : 4; + bdrkreg_t pp_rsvd : 29; + } ni_port_parms_fld_s; +} ni_port_parms_u_t; + +#else + +typedef union ni_port_parms_u { + bdrkreg_t ni_port_parms_regval; + struct { + bdrkreg_t pp_rsvd : 29; + bdrkreg_t pp_vch_err_enable : 4; + bdrkreg_t pp_squash_err_enable : 1; + bdrkreg_t pp_first_err_enable : 1; + bdrkreg_t pp_rsvd_1 : 1; + bdrkreg_t pp_d_avail_sel : 2; + bdrkreg_t pp_max_retry : 10; + bdrkreg_t pp_null_timeout : 6; + bdrkreg_t pp_max_burst : 10; + } ni_port_parms_fld_s; +} ni_port_parms_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains the age at which request and reply packets * + * are injected into the network. This feature allows replies to be * + * given a higher fixed priority than requests, which can be * + * important in some network saturation situations. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_channel_age_u { + bdrkreg_t ni_channel_age_regval; + struct { + bdrkreg_t ca_request_inject_age : 8; + bdrkreg_t ca_reply_inject_age : 8; + bdrkreg_t ca_rsvd : 48; + } ni_channel_age_fld_s; +} ni_channel_age_u_t; + +#else + +typedef union ni_channel_age_u { + bdrkreg_t ni_channel_age_regval; + struct { + bdrkreg_t ca_rsvd : 48; + bdrkreg_t ca_reply_inject_age : 8; + bdrkreg_t ca_request_inject_age : 8; + } ni_channel_age_fld_s; +} ni_channel_age_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains latched LLP port and problematic message * + * errors. The contents are the same information as the * + * NI_PORT_ERROR_CLEAR register, but, in this register read accesses * + * are non-destructive. Bits [52:24] assert the NI interrupt. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_errors_u { + bdrkreg_t ni_port_errors_regval; + struct { + bdrkreg_t pe_sn_error_count : 8; + bdrkreg_t pe_cb_error_count : 8; + bdrkreg_t pe_retry_count : 8; + bdrkreg_t pe_tail_timeout : 4; + bdrkreg_t pe_fifo_overflow : 4; + bdrkreg_t pe_external_short : 4; + bdrkreg_t pe_external_long : 4; + bdrkreg_t pe_external_bad_header : 4; + bdrkreg_t pe_internal_short : 4; + bdrkreg_t pe_internal_long : 4; + bdrkreg_t pe_link_reset_in : 1; + bdrkreg_t pe_rsvd : 11; + } ni_port_errors_fld_s; +} ni_port_errors_u_t; + +#else + +typedef union ni_port_errors_u { + bdrkreg_t ni_port_errors_regval; + struct { + bdrkreg_t pe_rsvd : 11; + bdrkreg_t pe_link_reset_in : 1; + bdrkreg_t pe_internal_long : 4; + bdrkreg_t pe_internal_short : 4; + bdrkreg_t pe_external_bad_header : 4; + bdrkreg_t pe_external_long : 4; + bdrkreg_t pe_external_short : 4; + bdrkreg_t pe_fifo_overflow : 4; + bdrkreg_t pe_tail_timeout : 4; + bdrkreg_t pe_retry_count : 8; + bdrkreg_t pe_cb_error_count : 8; + bdrkreg_t pe_sn_error_count : 8; + } ni_port_errors_fld_s; +} ni_port_errors_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register provides the sideband data associated with the * + * NI_PORT_HEADER registers and also additional data for error * + * processing. This register is not cleared on reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_sideband_u { + bdrkreg_t ni_port_sideband_regval; + struct { + bdrkreg_t ps_sideband : 8; + bdrkreg_t ps_bad_dest : 1; + bdrkreg_t ps_bad_prexsel : 1; + bdrkreg_t ps_rcv_error : 1; + bdrkreg_t ps_bad_message : 1; + bdrkreg_t ps_squash : 1; + bdrkreg_t ps_sn_status : 1; + bdrkreg_t ps_cb_status : 1; + bdrkreg_t ps_send_error : 1; + bdrkreg_t ps_vch_active : 4; + bdrkreg_t ps_rsvd : 44; + } ni_port_sideband_fld_s; +} ni_port_sideband_u_t; + +#else + +typedef union ni_port_sideband_u { + bdrkreg_t ni_port_sideband_regval; + struct { + bdrkreg_t ps_rsvd : 44; + bdrkreg_t ps_vch_active : 4; + bdrkreg_t ps_send_error : 1; + bdrkreg_t ps_cb_status : 1; + bdrkreg_t ps_sn_status : 1; + bdrkreg_t ps_squash : 1; + bdrkreg_t ps_bad_message : 1; + bdrkreg_t ps_rcv_error : 1; + bdrkreg_t ps_bad_prexsel : 1; + bdrkreg_t ps_bad_dest : 1; + bdrkreg_t ps_sideband : 8; + } ni_port_sideband_fld_s; +} ni_port_sideband_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register contains latched LLP port and problematic message * + * errors. The contents are the same information as the * + * NI_PORT_ERROR_CLEAR register, but, in this register read accesses * + * are non-destructive. Bits [52:24] assert the NI interrupt. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_error_clear_u { + bdrkreg_t ni_port_error_clear_regval; + struct { + bdrkreg_t pec_sn_error_count : 8; + bdrkreg_t pec_cb_error_count : 8; + bdrkreg_t pec_retry_count : 8; + bdrkreg_t pec_tail_timeout : 4; + bdrkreg_t pec_fifo_overflow : 4; + bdrkreg_t pec_external_short : 4; + bdrkreg_t pec_external_long : 4; + bdrkreg_t pec_external_bad_header : 4; + bdrkreg_t pec_internal_short : 4; + bdrkreg_t pec_internal_long : 4; + bdrkreg_t pec_link_reset_in : 1; + bdrkreg_t pec_rsvd : 11; + } ni_port_error_clear_fld_s; +} ni_port_error_clear_u_t; + +#else + +typedef union ni_port_error_clear_u { + bdrkreg_t ni_port_error_clear_regval; + struct { + bdrkreg_t pec_rsvd : 11; + bdrkreg_t pec_link_reset_in : 1; + bdrkreg_t pec_internal_long : 4; + bdrkreg_t pec_internal_short : 4; + bdrkreg_t pec_external_bad_header : 4; + bdrkreg_t pec_external_long : 4; + bdrkreg_t pec_external_short : 4; + bdrkreg_t pec_fifo_overflow : 4; + bdrkreg_t pec_tail_timeout : 4; + bdrkreg_t pec_retry_count : 8; + bdrkreg_t pec_cb_error_count : 8; + bdrkreg_t pec_sn_error_count : 8; + } ni_port_error_clear_fld_s; +} ni_port_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * Lookup table for the next hop's exit port. The table entry * + * selection is based on the 7-bit LocalCube routing destination. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_local_table_0_u { + bdrkreg_t ni_local_table_0_regval; + struct { + bdrkreg_t lt0_next_exit_port : 4; + bdrkreg_t lt0_next_vch_lsb : 1; + bdrkreg_t lt0_rsvd : 59; + } ni_local_table_0_fld_s; +} ni_local_table_0_u_t; + +#else + +typedef union ni_local_table_0_u { + bdrkreg_t ni_local_table_0_regval; + struct { + bdrkreg_t lt0_rsvd : 59; + bdrkreg_t lt0_next_vch_lsb : 1; + bdrkreg_t lt0_next_exit_port : 4; + } ni_local_table_0_fld_s; +} ni_local_table_0_u_t; + +#endif + + + + +/************************************************************************ + * * + * Lookup table for the next hop's exit port. The table entry * + * selection is based on the 7-bit LocalCube routing destination. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_local_table_127_u { + bdrkreg_t ni_local_table_127_regval; + struct { + bdrkreg_t lt1_next_exit_port : 4; + bdrkreg_t lt1_next_vch_lsb : 1; + bdrkreg_t lt1_rsvd : 59; + } ni_local_table_127_fld_s; +} ni_local_table_127_u_t; + +#else + +typedef union ni_local_table_127_u { + bdrkreg_t ni_local_table_127_regval; + struct { + bdrkreg_t lt1_rsvd : 59; + bdrkreg_t lt1_next_vch_lsb : 1; + bdrkreg_t lt1_next_exit_port : 4; + } ni_local_table_127_fld_s; +} ni_local_table_127_u_t; + +#endif + + + + +/************************************************************************ + * * + * Lookup table for the next hop's exit port. The table entry * + * selection is based on the 1-bit MetaCube routing destination. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union ni_global_table_u { + bdrkreg_t ni_global_table_regval; + struct { + bdrkreg_t gt_next_exit_port : 4; + bdrkreg_t gt_next_vch_lsb : 1; + bdrkreg_t gt_rsvd : 59; + } ni_global_table_fld_s; +} ni_global_table_u_t; + +#else + +typedef union ni_global_table_u { + bdrkreg_t ni_global_table_regval; + struct { + bdrkreg_t gt_rsvd : 59; + bdrkreg_t gt_next_vch_lsb : 1; + bdrkreg_t gt_next_exit_port : 4; + } ni_global_table_fld_s; +} ni_global_table_u_t; + +#endif + + + + + + +#endif /* _LANGUAGE_C */ + +/************************************************************************ + * * + * The following defines which were not formed into structures are * + * probably indentical to another register, and the name of the * + * register is provided against each of these registers. This * + * information needs to be checked carefully * + * * + * NI_LOCAL_TABLE_1 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_2 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_3 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_4 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_5 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_6 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_7 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_8 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_9 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_10 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_11 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_12 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_13 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_14 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_15 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_16 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_17 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_18 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_19 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_20 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_21 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_22 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_23 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_24 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_25 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_26 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_27 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_28 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_29 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_30 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_31 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_32 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_33 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_34 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_35 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_36 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_37 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_38 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_39 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_40 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_41 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_42 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_43 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_44 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_45 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_46 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_47 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_48 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_49 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_50 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_51 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_52 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_53 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_54 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_55 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_56 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_57 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_58 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_59 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_60 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_61 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_62 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_63 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_64 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_65 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_66 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_67 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_68 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_69 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_70 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_71 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_72 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_73 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_74 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_75 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_76 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_77 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_78 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_79 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_80 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_81 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_82 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_83 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_84 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_85 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_86 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_87 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_88 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_89 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_90 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_91 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_92 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_93 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_94 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_95 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_96 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_97 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_98 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_99 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_100 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_101 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_102 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_103 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_104 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_105 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_106 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_107 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_108 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_109 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_110 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_111 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_112 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_113 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_114 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_115 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_116 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_117 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_118 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_119 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_120 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_121 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_122 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_123 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_124 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_125 NI_LOCAL_TABLE_0 * + * NI_LOCAL_TABLE_126 NI_LOCAL_TABLE_0 * + * * + ************************************************************************/ + + +/************************************************************************ + * * + * The following defines were not formed into structures * + * * + * This could be because the document did not contain details of the * + * register, or because the automated script did not recognize the * + * register details in the documentation. If these register need * + * structure definition, please create them manually * + * * + * NI_PORT_HEADER_A 0x680108 * + * NI_PORT_HEADER_B 0x680110 * + * * + ************************************************************************/ + + +/************************************************************************ + * * + * MAKE ALL ADDITIONS AFTER THIS LINE * + * * + ************************************************************************/ + + + + + +#endif /* _ASM_SN_SN1_HUBNI_H */ diff --git a/include/asm-ia64/sn/sn1/hubni_next.h b/include/asm-ia64/sn/sn1/hubni_next.h new file mode 100644 index 000000000..3d0dbed4c --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubni_next.h @@ -0,0 +1,175 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBNI_NEXT_H +#define _ASM_SN_SN1_HUBNI_NEXT_H + +#define NI_LOCAL_ENTRIES 128 +#define NI_META_ENTRIES 1 + +#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE_0 + (8 * (_x))) +#define NI_META_TABLE(_x) (NI_GLOBAL_TABLE + (8 * (_x))) + +/************************************************************** + + Masks and shifts for NI registers are defined below. + +**************************************************************/ + +#define NPS_LINKUP_SHFT 1 +#define NPS_LINKUP_MASK (UINT64_CAST 0x1 << 1) + + +#define NPR_LOCALRESET (UINT64_CAST 1 << 2) /* Reset loc. bdrck */ +#define NPR_PORTRESET (UINT64_CAST 1 << 1) /* Send warm reset */ +#define NPR_LINKRESET (UINT64_CAST 1 << 0) /* Send link reset */ + +/* NI_DIAG_PARMS bit definitions */ +#define NDP_SENDERROR (UINT64_CAST 1 << 0) /* Send data error */ +#define NDP_PORTDISABLE (UINT64_CAST 1 << 1) /* Port disable */ +#define NDP_SENDERROFF (UINT64_CAST 1 << 2) /* Disable send error recovery */ + + +/* NI_PORT_ERROR mask and shift definitions (some are not present in SN0) */ + +#define NPE_LINKRESET (UINT64_CAST 1 << 52) +#define NPE_INTLONG_SHFT 48 +#define NPE_INTLONG_MASK (UINT64_CAST 0xf << NPE_INTLONG_SHFT) +#define NPE_INTSHORT_SHFT 44 +#define NPE_INTSHORT_MASK (UINT64_CAST 0xf << NPE_INTSHORT_SHFT) +#define NPE_EXTBADHEADER_SHFT 40 +#define NPE_EXTBADHEADER_MASK (UINT64_CAST 0xf << NPE_EXTBADHEADER_SHFT) +#define NPE_EXTLONG_SHFT 36 +#define NPE_EXTLONG_MASK (UINT64_CAST 0xf << NPE_EXTLONG_SHFT) +#define NPE_EXTSHORT_SHFT 32 +#define NPE_EXTSHORT_MASK (UINT64_CAST 0xf << NPE_EXTSHORT_SHFT) +#define NPE_FIFOOVFLOW_SHFT 28 +#define NPE_FIFOOVFLOW_MASK (UINT64_CAST 0xf << NPE_FIFOOVFLOW_SHFT) +#define NPE_TAILTO_SHFT 24 +#define NPE_TAILTO_MASK (UINT64_CAST 0xf << NPE_TAILTO_SHFT) +#define NPE_RETRYCOUNT_SHFT 16 +#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << NPE_RETRYCOUNT_SHFT) +#define NPE_CBERRCOUNT_SHFT 8 +#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << NPE_CBERRCOUNT_SHFT) +#define NPE_SNERRCOUNT_SHFT 0 +#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << NPE_SNERRCOUNT_SHFT) + +#define NPE_COUNT_MAX 0xff + +#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTLONG_MASK |\ + NPE_INTSHORT_MASK | NPE_EXTBADHEADER_MASK |\ + NPE_EXTLONG_MASK | NPE_EXTSHORT_MASK |\ + NPE_FIFOOVFLOW_MASK | NPE_TAILTO_MASK) + +#ifdef _LANGUAGE_C +/* NI_PORT_HEADER[AB] registers (not automatically generated) */ + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_header_a_u { + bdrkreg_t ni_port_header_a_regval; + struct { + bdrkreg_t pha_v : 1; + bdrkreg_t pha_age : 8; + bdrkreg_t pha_direction : 4; + bdrkreg_t pha_destination : 8; + bdrkreg_t pha_reserved_1 : 3; + bdrkreg_t pha_command : 8; + bdrkreg_t pha_prexsel : 3; + bdrkreg_t pha_address_b : 27; + bdrkreg_t pha_reserved : 2; + } ni_port_header_a_fld_s; +} ni_port_header_a_u_t; + +#else + +typedef union ni_port_header_a_u { + bdrkreg_t ni_port_header_a_regval; + struct { + bdrkreg_t pha_reserved : 2; + bdrkreg_t pha_address_b : 27; + bdrkreg_t pha_prexsel : 3; + bdrkreg_t pha_command : 8; + bdrkreg_t pha_reserved_1 : 3; + bdrkreg_t pha_destination : 8; + bdrkreg_t pha_direction : 4; + bdrkreg_t pha_age : 8; + bdrkreg_t pha_v : 1; + } ni_port_header_a_fld_s; +} ni_port_header_a_u_t; + +#endif + +#ifdef LITTLE_ENDIAN + +typedef union ni_port_header_b_u { + bdrkreg_t ni_port_header_b_regval; + struct { + bdrkreg_t phb_supplemental : 11; + bdrkreg_t phb_reserved_2 : 5; + bdrkreg_t phb_source : 11; + bdrkreg_t phb_reserved_1 : 8; + bdrkreg_t phb_address_a : 3; + bdrkreg_t phb_address_c : 8; + bdrkreg_t phb_reserved : 18; + } ni_port_header_b_fld_s; +} ni_port_header_b_u_t; + +#else + +typedef union ni_port_header_b_u { + bdrkreg_t ni_port_header_b_regval; + struct { + bdrkreg_t phb_reserved : 18; + bdrkreg_t phb_address_c : 8; + bdrkreg_t phb_address_a : 3; + bdrkreg_t phb_reserved_1 : 8; + bdrkreg_t phb_source : 11; + bdrkreg_t phb_reserved_2 : 5; + bdrkreg_t phb_supplemental : 11; + } ni_port_header_b_fld_s; +} ni_port_header_b_u_t; + +#endif +#endif + +/* NI_RESET_ENABLE mask definitions */ + +#define NRE_RESETOK (UINT64_CAST 1) /* Let LLP reset bedrock */ + +/* NI PORT_ERRORS, Max number of RETRY_COUNT, Check Bit, and Sequence */ +/* Number errors (8 bit counters that do not wrap). */ +#define NI_LLP_RETRY_MAX 0xff +#define NI_LLP_CB_MAX 0xff +#define NI_LLP_SN_MAX 0xff + +/* NI_PORT_PARMS shift and mask definitions */ + +#define NPP_VCH_ERR_EN_SHFT 31 +#define NPP_VCH_ERR_EN_MASK (0xf << NPP_VCH_ERR_EN_SHFT) +#define NPP_SQUASH_ERR_EN_SHFT 30 +#define NPP_SQUASH_ERR_EN_MASK (0x1 << NPP_SQUASH_ERR_EN_SHFT) +#define NPP_FIRST_ERR_EN_SHFT 29 +#define NPP_FIRST_ERR_EN_MASK (0x1 << NPP_FIRST_ERR_EN_SHFT) +#define NPP_D_AVAIL_SEL_SHFT 26 +#define NPP_D_AVAIL_SEL_MASK (0x3 << NPP_D_AVAIL_SEL_SHFT) +#define NPP_MAX_RETRY_SHFT 16 +#define NPP_MAX_RETRY_MASK (0x3ff << NPP_MAX_RETRY_SHFT) +#define NPP_NULL_TIMEOUT_SHFT 10 +#define NPP_NULL_TIMEOUT_MASK (0x3f << NPP_NULL_TIMEOUT_SHFT) +#define NPP_MAX_BURST_SHFT 0 +#define NPP_MAX_BURST_MASK (0x3ff << NPP_MAX_BURST_SHFT) + +#define NPP_RESET_DEFAULTS (0xf << NPP_VCH_ERR_EN_SHFT | \ + 0x1 << NPP_FIRST_ERR_EN_SHFT | \ + 0x3ff << NPP_MAX_RETRY_SHFT | \ + 0x6 << NPP_NULL_TIMEOUT_SHFT | \ + 0x3f0 << NPP_MAX_BURST_SHFT) + +#endif /* _ASM_SN_SN1_HUBNI_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubpi.h b/include/asm-ia64/sn/sn1/hubpi.h new file mode 100644 index 000000000..4b81ca32b --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubpi.h @@ -0,0 +1,4264 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBPI_H +#define _ASM_SN_SN1_HUBPI_H + +/************************************************************************ + * * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * + * * + * This file is created by an automated script. Any (minimal) changes * + * made manually to this file should be made with care. * + * * + * MAKE ALL ADDITIONS TO THE END OF THIS FILE * + * * + ************************************************************************/ + + +#define PI_CPU_PROTECT 0x00000000 /* CPU Protection */ + + + +#define PI_PROT_OVRRD 0x00000008 /* + * Clear CPU + * Protection bit in + * CPU_PROTECT + */ + + + +#define PI_IO_PROTECT 0x00000010 /* + * Interrupt Pending + * Protection for IO + * access + */ + + + +#define PI_REGION_PRESENT 0x00000018 /* Region present */ + + + +#define PI_CPU_NUM 0x00000020 /* CPU Number ID */ + + + +#define PI_CALIAS_SIZE 0x00000028 /* Cached Alias Size */ + + + +#define PI_MAX_CRB_TIMEOUT 0x00000030 /* + * Maximum Timeout for + * CRB + */ + + + +#define PI_CRB_SFACTOR 0x00000038 /* + * Scale Factor for + * CRB Timeout + */ + + + +#define PI_CPU_PRESENT_A 0x00000040 /* + * CPU Present for + * CPU_A + */ + + + +#define PI_CPU_PRESENT_B 0x00000048 /* + * CPU Present for + * CPU_B + */ + + + +#define PI_CPU_ENABLE_A 0x00000050 /* + * CPU Enable for + * CPU_A + */ + + + +#define PI_CPU_ENABLE_B 0x00000058 /* + * CPU Enable for + * CPU_B + */ + + + +#define PI_REPLY_LEVEL 0x00010060 /* + * Reply FIFO Priority + * Control + */ + + + +#define PI_GFX_CREDIT_MODE 0x00020068 /* + * Graphics Credit + * Mode + */ + + + +#define PI_NMI_A 0x00000070 /* + * Non-maskable + * Interrupt to CPU A + */ + + + +#define PI_NMI_B 0x00000078 /* + * Non-maskable + * Interrupt to CPU B + */ + + + +#define PI_INT_PEND_MOD 0x00000090 /* + * Interrupt Pending + * Modify + */ + + + +#define PI_INT_PEND0 0x00000098 /* Interrupt Pending 0 */ + + + +#define PI_INT_PEND1 0x000000A0 /* Interrupt Pending 1 */ + + + +#define PI_INT_MASK0_A 0x000000A8 /* + * Interrupt Mask 0 + * for CPU A + */ + + + +#define PI_INT_MASK1_A 0x000000B0 /* + * Interrupt Mask 1 + * for CPU A + */ + + + +#define PI_INT_MASK0_B 0x000000B8 /* + * Interrupt Mask 0 + * for CPU B + */ + + + +#define PI_INT_MASK1_B 0x000000C0 /* + * Interrupt Mask 1 + * for CPU B + */ + + + +#define PI_CC_PEND_SET_A 0x000000C8 /* + * CC Interrupt + * Pending for CPU A + */ + + + +#define PI_CC_PEND_SET_B 0x000000D0 /* + * CC Interrupt + * Pending for CPU B + */ + + + +#define PI_CC_PEND_CLR_A 0x000000D8 /* + * CPU to CPU + * Interrupt Pending + * Clear for CPU A + */ + + + +#define PI_CC_PEND_CLR_B 0x000000E0 /* + * CPU to CPU + * Interrupt Pending + * Clear for CPU B + */ + + + +#define PI_CC_MASK 0x000000E8 /* + * Mask of both + * CC_PENDs + */ + + + +#define PI_INT_PEND1_REMAP 0x000000F0 /* + * Remap Interrupt + * Pending + */ + + + +#define PI_RT_COUNTER 0x00030100 /* Real Time Counter */ + + + +#define PI_RT_COMPARE_A 0x00000108 /* Real Time Compare A */ + + + +#define PI_RT_COMPARE_B 0x00000110 /* Real Time Compare B */ + + + +#define PI_PROFILE_COMPARE 0x00000118 /* Profiling Compare */ + + + +#define PI_RT_INT_PEND_A 0x00000120 /* + * RT interrupt + * pending + */ + + + +#define PI_RT_INT_PEND_B 0x00000128 /* + * RT interrupt + * pending + */ + + + +#define PI_PROF_INT_PEND_A 0x00000130 /* + * Profiling interrupt + * pending + */ + + + +#define PI_PROF_INT_PEND_B 0x00000138 /* + * Profiling interrupt + * pending + */ + + + +#define PI_RT_INT_EN_A 0x00000140 /* RT Interrupt Enable */ + + + +#define PI_RT_INT_EN_B 0x00000148 /* RT Interrupt Enable */ + + + +#define PI_PROF_INT_EN_A 0x00000150 /* + * Profiling Interrupt + * Enable + */ + + + +#define PI_PROF_INT_EN_B 0x00000158 /* + * Profiling Interrupt + * Enable + */ + + + +#define PI_DEBUG_SEL 0x00000160 /* PI Debug Select */ + + + +#define PI_INT_PEND_MOD_ALIAS 0x00000180 /* + * Interrupt Pending + * Modify + */ + + + +#define PI_PERF_CNTL_A 0x00040200 /* + * Performance Counter + * Control A + */ + + + +#define PI_PERF_CNTR0_A 0x00040208 /* + * Performance Counter + * 0 A + */ + + + +#define PI_PERF_CNTR1_A 0x00040210 /* + * Performance Counter + * 1 A + */ + + + +#define PI_PERF_CNTL_B 0x00050200 /* + * Performance Counter + * Control B + */ + + + +#define PI_PERF_CNTR0_B 0x00050208 /* + * Performance Counter + * 0 B + */ + + + +#define PI_PERF_CNTR1_B 0x00050210 /* + * Performance Counter + * 1 B + */ + + + +#define PI_GFX_PAGE_A 0x00000300 /* Graphics Page */ + + + +#define PI_GFX_CREDIT_CNTR_A 0x00000308 /* + * Graphics Credit + * Counter + */ + + + +#define PI_GFX_BIAS_A 0x00000310 /* TRex+ BIAS */ + + + +#define PI_GFX_INT_CNTR_A 0x00000318 /* + * Graphics Interrupt + * Counter + */ + + + +#define PI_GFX_INT_CMP_A 0x00000320 /* + * Graphics Interrupt + * Compare + */ + + + +#define PI_GFX_PAGE_B 0x00000328 /* Graphics Page */ + + + +#define PI_GFX_CREDIT_CNTR_B 0x00000330 /* + * Graphics Credit + * Counter + */ + + + +#define PI_GFX_BIAS_B 0x00000338 /* TRex+ BIAS */ + + + +#define PI_GFX_INT_CNTR_B 0x00000340 /* + * Graphics Interrupt + * Counter + */ + + + +#define PI_GFX_INT_CMP_B 0x00000348 /* + * Graphics Interrupt + * Compare + */ + + + +#define PI_ERR_INT_PEND_WR 0x000003F8 /* + * Error Interrupt + * Pending (Writable) + */ + + + +#define PI_ERR_INT_PEND 0x00000400 /* + * Error Interrupt + * Pending + */ + + + +#define PI_ERR_INT_MASK_A 0x00000408 /* + * Error Interrupt + * Mask CPU_A + */ + + + +#define PI_ERR_INT_MASK_B 0x00000410 /* + * Error Interrupt + * Mask CPU_B + */ + + + +#define PI_ERR_STACK_ADDR_A 0x00000418 /* + * Error Stack Address + * Pointer + */ + + + +#define PI_ERR_STACK_ADDR_B 0x00000420 /* + * Error Stack Address + * Pointer + */ + + + +#define PI_ERR_STACK_SIZE 0x00000428 /* Error Stack Size */ + + + +#define PI_ERR_STATUS0_A 0x00000430 /* Error Status 0 */ + + + +#define PI_ERR_STATUS0_A_CLR 0x00000438 /* Error Status 0 */ + + + +#define PI_ERR_STATUS1_A 0x00000440 /* Error Status 1 */ + + + +#define PI_ERR_STATUS1_A_CLR 0x00000448 /* Error Status 1 */ + + + +#define PI_ERR_STATUS0_B 0x00000450 /* Error Status 0 */ + + + +#define PI_ERR_STATUS0_B_CLR 0x00000458 /* Error Status 0 */ + + + +#define PI_ERR_STATUS1_B 0x00000460 /* Error Status 1 */ + + + +#define PI_ERR_STATUS1_B_CLR 0x00000468 /* Error Status 1 */ + + + +#define PI_SPOOL_CMP_A 0x00000470 /* Spool Compare */ + + + +#define PI_SPOOL_CMP_B 0x00000478 /* Spool Compare */ + + + +#define PI_CRB_TIMEOUT_A 0x00000480 /* + * CRB entries which + * have timed out but + * are still valid + */ + + + +#define PI_CRB_TIMEOUT_B 0x00000488 /* + * CRB entries which + * have timed out but + * are still valid + */ + + + +#define PI_SYSAD_ERRCHK_EN 0x00000490 /* + * enables + * sysad/cmd/state + * error checking + */ + + + +#define PI_FORCE_BAD_CHECK_BIT_A 0x00000498 /* + * force SysAD Check + * Bit error + */ + + + +#define PI_FORCE_BAD_CHECK_BIT_B 0x000004A0 /* + * force SysAD Check + * Bit error + */ + + + +#define PI_NACK_CNT_A 0x000004A8 /* + * consecutive NACK + * counter + */ + + + +#define PI_NACK_CNT_B 0x000004B0 /* + * consecutive NACK + * counter + */ + + + +#define PI_NACK_CMP 0x000004B8 /* NACK count compare */ + + + +#define PI_SPOOL_MASK 0x000004C0 /* Spool error mask */ + + + +#define PI_SPURIOUS_HDR_0 0x000004C8 /* Spurious Error 0 */ + + + +#define PI_SPURIOUS_HDR_1 0x000004D0 /* Spurious Error 1 */ + + + +#define PI_ERR_INJECT 0x000004D8 /* + * SysAD bus error + * injection + */ + + + + + +#ifdef _LANGUAGE_C + +/************************************************************************ + * * + * Description: This read/write register determines on a * + * bit-per-region basis whether incoming CPU-initiated PIO Read and * + * Write to local PI registers are allowed. If access is allowed, the * + * PI's response to a partial read is a PRPLY message, and the * + * response to a partial write is a PACK message. If access is not * + * allowed, the PI's response to a partial read is a PRERR message, * + * and the response to a partial write is a PWERR message. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +typedef union pi_cpu_protect_u { + bdrkreg_t pi_cpu_protect_regval; + struct { + bdrkreg_t cp_cpu_protect : 64; + } pi_cpu_protect_fld_s; +} pi_cpu_protect_u_t; + + + + +/************************************************************************ + * * + * A write with a special data pattern allows any CPU to set its * + * region's bit in CPU_PROTECT. This register has data pattern * + * protection. * + * * + ************************************************************************/ + + + + +typedef union pi_prot_ovrrd_u { + bdrkreg_t pi_prot_ovrrd_regval; + struct { + bdrkreg_t po_prot_ovrrd : 64; + } pi_prot_ovrrd_fld_s; +} pi_prot_ovrrd_u_t; + + + + +/************************************************************************ + * * + * Description: This read/write register determines on a * + * bit-per-region basis whether incoming IO-initiated interrupts are * + * allowed to set bits in INT_PEND0 and INT_PEND1. If access is * + * allowed, the PI's response to a partial read is a PRPLY message, * + * and the response to a partial write is a PACK message. If access * + * is not allowed, the PI's response to a partial read is a PRERR * + * message, and the response to a partial write is a PWERR message. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +typedef union pi_io_protect_u { + bdrkreg_t pi_io_protect_regval; + struct { + bdrkreg_t ip_io_protect : 64; + } pi_io_protect_fld_s; +} pi_io_protect_u_t; + + + + +/************************************************************************ + * * + * Description: This read/write register determines on a * + * bit-per-region basis whether read access from a local processor to * + * the region is permissible. For example, setting a bit to 0 * + * prevents speculative reads to that non-existent node. If a read * + * request to a non-present region occurs, an ERR response is issued * + * to the TRex+ (no PI error registers are modified). It is up to * + * software to load this register with the proper contents. * + * Region-present checking is only done for coherent read requests - * + * partial reads/writes will be issued to a non-present region. The * + * setting of these bits does not affect a node's access to its * + * CALIAS space. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +typedef union pi_region_present_u { + bdrkreg_t pi_region_present_regval; + struct { + bdrkreg_t rp_region_present : 64; + } pi_region_present_fld_s; +} pi_region_present_u_t; + + + + +/************************************************************************ + * * + * A read to the location will allow a CPU to identify itself as * + * either CPU_A or CPU_B, and will indicate whether the CPU is * + * connected to PI 0 or PI 1. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_cpu_num_u { + bdrkreg_t pi_cpu_num_regval; + struct { + bdrkreg_t cn_cpu_num : 1; + bdrkreg_t cn_pi_id : 1; + bdrkreg_t cn_rsvd : 62; + } pi_cpu_num_fld_s; +} pi_cpu_num_u_t; + +#else + +typedef union pi_cpu_num_u { + bdrkreg_t pi_cpu_num_regval; + struct { + bdrkreg_t cn_rsvd : 62; + bdrkreg_t cn_pi_id : 1; + bdrkreg_t cn_cpu_num : 1; + } pi_cpu_num_fld_s; +} pi_cpu_num_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This read/write location determines the size of the * + * Calias Space. * + * This register is not reset by a soft reset. * + * NOTE: For predictable behavior, all Calias spaces in a system must * + * be set to the same size. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_calias_size_u { + bdrkreg_t pi_calias_size_regval; + struct { + bdrkreg_t cs_calias_size : 4; + bdrkreg_t cs_rsvd : 60; + } pi_calias_size_fld_s; +} pi_calias_size_u_t; + +#else + +typedef union pi_calias_size_u { + bdrkreg_t pi_calias_size_regval; + struct { + bdrkreg_t cs_rsvd : 60; + bdrkreg_t cs_calias_size : 4; + } pi_calias_size_fld_s; +} pi_calias_size_u_t; + +#endif + + + + +/************************************************************************ + * * + * This Read/Write location determines at which value (increment) * + * the CRB Timeout Counters cause a timeout error to occur. See * + * Section 3.4.2.2, "Time-outs in RRB and WRB" in the * + * Processor Interface chapter, volume 1 of this document for more * + * details. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_max_crb_timeout_u { + bdrkreg_t pi_max_crb_timeout_regval; + struct { + bdrkreg_t mct_max_timeout : 8; + bdrkreg_t mct_rsvd : 56; + } pi_max_crb_timeout_fld_s; +} pi_max_crb_timeout_u_t; + +#else + +typedef union pi_max_crb_timeout_u { + bdrkreg_t pi_max_crb_timeout_regval; + struct { + bdrkreg_t mct_rsvd : 56; + bdrkreg_t mct_max_timeout : 8; + } pi_max_crb_timeout_fld_s; +} pi_max_crb_timeout_u_t; + +#endif + + + + +/************************************************************************ + * * + * This Read/Write location determines how often a valid CRB's * + * Timeout Counter is incremented. See Section 3.4.2.2, * + * "Time-outs in RRB and WRB" in the Processor Interface * + * chapter, volume 1 of this document for more details. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_crb_sfactor_u { + bdrkreg_t pi_crb_sfactor_regval; + struct { + bdrkreg_t cs_sfactor : 24; + bdrkreg_t cs_rsvd : 40; + } pi_crb_sfactor_fld_s; +} pi_crb_sfactor_u_t; + +#else + +typedef union pi_crb_sfactor_u { + bdrkreg_t pi_crb_sfactor_regval; + struct { + bdrkreg_t cs_rsvd : 40; + bdrkreg_t cs_sfactor : 24; + } pi_crb_sfactor_fld_s; +} pi_crb_sfactor_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. The PI sets this * + * bit when it sees the first transaction initiated by the associated * + * CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_cpu_present_a_u { + bdrkreg_t pi_cpu_present_a_regval; + struct { + bdrkreg_t cpa_cpu_present : 1; + bdrkreg_t cpa_rsvd : 63; + } pi_cpu_present_a_fld_s; +} pi_cpu_present_a_u_t; + +#else + +typedef union pi_cpu_present_a_u { + bdrkreg_t pi_cpu_present_a_regval; + struct { + bdrkreg_t cpa_rsvd : 63; + bdrkreg_t cpa_cpu_present : 1; + } pi_cpu_present_a_fld_s; +} pi_cpu_present_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. The PI sets this * + * bit when it sees the first transaction initiated by the associated * + * CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_cpu_present_b_u { + bdrkreg_t pi_cpu_present_b_regval; + struct { + bdrkreg_t cpb_cpu_present : 1; + bdrkreg_t cpb_rsvd : 63; + } pi_cpu_present_b_fld_s; +} pi_cpu_present_b_u_t; + +#else + +typedef union pi_cpu_present_b_u { + bdrkreg_t pi_cpu_present_b_regval; + struct { + bdrkreg_t cpb_rsvd : 63; + bdrkreg_t cpb_cpu_present : 1; + } pi_cpu_present_b_fld_s; +} pi_cpu_present_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There is one of these registers for each CPU. This * + * Read/Write location determines whether the associated CPU is * + * enabled to issue external requests. When this bit is zero for a * + * processor, the PI ignores SysReq_L from that processor, and so * + * never grants it the bus. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_cpu_enable_a_u { + bdrkreg_t pi_cpu_enable_a_regval; + struct { + bdrkreg_t cea_cpu_enable : 1; + bdrkreg_t cea_rsvd : 63; + } pi_cpu_enable_a_fld_s; +} pi_cpu_enable_a_u_t; + +#else + +typedef union pi_cpu_enable_a_u { + bdrkreg_t pi_cpu_enable_a_regval; + struct { + bdrkreg_t cea_rsvd : 63; + bdrkreg_t cea_cpu_enable : 1; + } pi_cpu_enable_a_fld_s; +} pi_cpu_enable_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There is one of these registers for each CPU. This * + * Read/Write location determines whether the associated CPU is * + * enabled to issue external requests. When this bit is zero for a * + * processor, the PI ignores SysReq_L from that processor, and so * + * never grants it the bus. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_cpu_enable_b_u { + bdrkreg_t pi_cpu_enable_b_regval; + struct { + bdrkreg_t ceb_cpu_enable : 1; + bdrkreg_t ceb_rsvd : 63; + } pi_cpu_enable_b_fld_s; +} pi_cpu_enable_b_u_t; + +#else + +typedef union pi_cpu_enable_b_u { + bdrkreg_t pi_cpu_enable_b_regval; + struct { + bdrkreg_t ceb_rsvd : 63; + bdrkreg_t ceb_cpu_enable : 1; + } pi_cpu_enable_b_fld_s; +} pi_cpu_enable_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. A write to this * + * location will cause an NMI to be issued to the CPU. * + * * + ************************************************************************/ + + + + +typedef union pi_nmi_a_u { + bdrkreg_t pi_nmi_a_regval; + struct { + bdrkreg_t na_nmi_cpu : 64; + } pi_nmi_a_fld_s; +} pi_nmi_a_u_t; + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. A write to this * + * location will cause an NMI to be issued to the CPU. * + * * + ************************************************************************/ + + + + +typedef union pi_nmi_b_u { + bdrkreg_t pi_nmi_b_regval; + struct { + bdrkreg_t nb_nmi_cpu : 64; + } pi_nmi_b_fld_s; +} pi_nmi_b_u_t; + + + + +/************************************************************************ + * * + * A write to this register allows a single bit in the INT_PEND0 or * + * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is * + * modified in INT_PEND0, while if 6 is set, a bit is modified in * + * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine * + * which bit in the register is effected. The value of 8 will * + * determine whether the desired bit is set (8=1) or cleared (8=0). * + * This is the only register which is accessible by IO issued PWRI * + * command and is protected through the IO_PROTECT register. If the * + * region bit in the IO_PROTECT is not set then a WERR reply is * + * issued. CPU access is controlled through CPU_PROTECT. The contents * + * of this register are masked with the contents of INT_MASK_A * + * (INT_MASK_B) to determine whether an L2 interrupt is issued to * + * CPU_A (CPU_B). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_int_pend_mod_u { + bdrkreg_t pi_int_pend_mod_regval; + struct { + bdrkreg_t ipm_bit_select : 6; + bdrkreg_t ipm_reg_select : 1; + bdrkreg_t ipm_rsvd_1 : 1; + bdrkreg_t ipm_value : 1; + bdrkreg_t ipm_rsvd : 55; + } pi_int_pend_mod_fld_s; +} pi_int_pend_mod_u_t; + +#else + +typedef union pi_int_pend_mod_u { + bdrkreg_t pi_int_pend_mod_regval; + struct { + bdrkreg_t ipm_rsvd : 55; + bdrkreg_t ipm_value : 1; + bdrkreg_t ipm_rsvd_1 : 1; + bdrkreg_t ipm_reg_select : 1; + bdrkreg_t ipm_bit_select : 6; + } pi_int_pend_mod_fld_s; +} pi_int_pend_mod_u_t; + +#endif + + + + +/************************************************************************ + * * + * This read-only register provides information about interrupts * + * that are currently pending. The interrupts in this register map to * + * interrupt level 2 (L2). The GFX_INT_A/B bits are set by hardware * + * but must be cleared by software. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_int_pend0_u { + bdrkreg_t pi_int_pend0_regval; + struct { + bdrkreg_t ip_int_pend0_lo : 1; + bdrkreg_t ip_gfx_int_a : 1; + bdrkreg_t ip_gfx_int_b : 1; + bdrkreg_t ip_page_migration : 1; + bdrkreg_t ip_uart_ucntrl : 1; + bdrkreg_t ip_or_cc_pend_a : 1; + bdrkreg_t ip_or_cc_pend_b : 1; + bdrkreg_t ip_int_pend0_hi : 57; + } pi_int_pend0_fld_s; +} pi_int_pend0_u_t; + +#else + +typedef union pi_int_pend0_u { + bdrkreg_t pi_int_pend0_regval; + struct { + bdrkreg_t ip_int_pend0_hi : 57; + bdrkreg_t ip_or_cc_pend_b : 1; + bdrkreg_t ip_or_cc_pend_a : 1; + bdrkreg_t ip_uart_ucntrl : 1; + bdrkreg_t ip_page_migration : 1; + bdrkreg_t ip_gfx_int_b : 1; + bdrkreg_t ip_gfx_int_a : 1; + bdrkreg_t ip_int_pend0_lo : 1; + } pi_int_pend0_fld_s; +} pi_int_pend0_u_t; + +#endif + + + + +/************************************************************************ + * * + * This read-only register provides information about interrupts * + * that are currently pending. The interrupts in this register map to * + * interrupt level 3 (L3), unless remapped by the INT_PEND1_REMAP * + * register. The SYS_COR_ERR_A/B, RTC_DROP_OUT, and NACK_INT_A/B bits * + * are set by hardware but must be cleared by software. The * + * SYSTEM_SHUTDOWN, NI_ERROR, LB_ERROR and XB_ERROR bits just reflect * + * the value of other logic, and cannot be changed by PI register * + * writes. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_int_pend1_u { + bdrkreg_t pi_int_pend1_regval; + struct { + bdrkreg_t ip_int_pend1 : 54; + bdrkreg_t ip_xb_error : 1; + bdrkreg_t ip_lb_error : 1; + bdrkreg_t ip_nack_int_a : 1; + bdrkreg_t ip_nack_int_b : 1; + bdrkreg_t ip_perf_cntr_oflow : 1; + bdrkreg_t ip_sys_cor_err_b : 1; + bdrkreg_t ip_sys_cor_err_a : 1; + bdrkreg_t ip_md_corr_error : 1; + bdrkreg_t ip_ni_error : 1; + bdrkreg_t ip_system_shutdown : 1; + } pi_int_pend1_fld_s; +} pi_int_pend1_u_t; + +#else + +typedef union pi_int_pend1_u { + bdrkreg_t pi_int_pend1_regval; + struct { + bdrkreg_t ip_system_shutdown : 1; + bdrkreg_t ip_ni_error : 1; + bdrkreg_t ip_md_corr_error : 1; + bdrkreg_t ip_sys_cor_err_a : 1; + bdrkreg_t ip_sys_cor_err_b : 1; + bdrkreg_t ip_perf_cntr_oflow : 1; + bdrkreg_t ip_nack_int_b : 1; + bdrkreg_t ip_nack_int_a : 1; + bdrkreg_t ip_lb_error : 1; + bdrkreg_t ip_xb_error : 1; + bdrkreg_t ip_int_pend1 : 54; + } pi_int_pend1_fld_s; +} pi_int_pend1_u_t; + +#endif + + + + +/************************************************************************ + * * + * This read/write register masks the contents of INT_PEND0 to * + * determine whether an L2 interrupt (bit 10 of the processor's Cause * + * register) is sent to CPU_A if the same bit in the INT_PEND0 * + * register is also set. Only one processor in a Bedrock should * + * enable the PAGE_MIGRATION bit/interrupt. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_int_mask0_a_u { + bdrkreg_t pi_int_mask0_a_regval; + struct { + bdrkreg_t ima_int_mask0_lo : 1; + bdrkreg_t ima_gfx_int_a : 1; + bdrkreg_t ima_gfx_int_b : 1; + bdrkreg_t ima_page_migration : 1; + bdrkreg_t ima_uart_ucntrl : 1; + bdrkreg_t ima_or_ccp_mask_a : 1; + bdrkreg_t ima_or_ccp_mask_b : 1; + bdrkreg_t ima_int_mask0_hi : 57; + } pi_int_mask0_a_fld_s; +} pi_int_mask0_a_u_t; + +#else + +typedef union pi_int_mask0_a_u { + bdrkreg_t pi_int_mask0_a_regval; + struct { + bdrkreg_t ima_int_mask0_hi : 57; + bdrkreg_t ima_or_ccp_mask_b : 1; + bdrkreg_t ima_or_ccp_mask_a : 1; + bdrkreg_t ima_uart_ucntrl : 1; + bdrkreg_t ima_page_migration : 1; + bdrkreg_t ima_gfx_int_b : 1; + bdrkreg_t ima_gfx_int_a : 1; + bdrkreg_t ima_int_mask0_lo : 1; + } pi_int_mask0_a_fld_s; +} pi_int_mask0_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * This read/write register masks the contents of INT_PEND1 to * + * determine whether an interrupt should be sent. Bits 63:32 always * + * generate an L3 interrupt (bit 11 of the processor's Cause * + * register) is sent to CPU_A if the same bit in the INT_PEND1 * + * register is set. Bits 31:0 can generate either an L3 or L2 * + * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only * + * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR, * + * XB_ERROR and MD_CORR_ERROR bits. * + * * + ************************************************************************/ + + + + +typedef union pi_int_mask1_a_u { + bdrkreg_t pi_int_mask1_a_regval; + struct { + bdrkreg_t ima_int_mask1 : 64; + } pi_int_mask1_a_fld_s; +} pi_int_mask1_a_u_t; + + + + +/************************************************************************ + * * + * This read/write register masks the contents of INT_PEND0 to * + * determine whether an L2 interrupt (bit 10 of the processor's Cause * + * register) is sent to CPU_B if the same bit in the INT_PEND0 * + * register is also set. Only one processor in a Bedrock should * + * enable the PAGE_MIGRATION bit/interrupt. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_int_mask0_b_u { + bdrkreg_t pi_int_mask0_b_regval; + struct { + bdrkreg_t imb_int_mask0_lo : 1; + bdrkreg_t imb_gfx_int_a : 1; + bdrkreg_t imb_gfx_int_b : 1; + bdrkreg_t imb_page_migration : 1; + bdrkreg_t imb_uart_ucntrl : 1; + bdrkreg_t imb_or_ccp_mask_a : 1; + bdrkreg_t imb_or_ccp_mask_b : 1; + bdrkreg_t imb_int_mask0_hi : 57; + } pi_int_mask0_b_fld_s; +} pi_int_mask0_b_u_t; + +#else + +typedef union pi_int_mask0_b_u { + bdrkreg_t pi_int_mask0_b_regval; + struct { + bdrkreg_t imb_int_mask0_hi : 57; + bdrkreg_t imb_or_ccp_mask_b : 1; + bdrkreg_t imb_or_ccp_mask_a : 1; + bdrkreg_t imb_uart_ucntrl : 1; + bdrkreg_t imb_page_migration : 1; + bdrkreg_t imb_gfx_int_b : 1; + bdrkreg_t imb_gfx_int_a : 1; + bdrkreg_t imb_int_mask0_lo : 1; + } pi_int_mask0_b_fld_s; +} pi_int_mask0_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * This read/write register masks the contents of INT_PEND1 to * + * determine whether an interrupt should be sent. Bits 63:32 always * + * generate an L3 interrupt (bit 11 of the processor's Cause * + * register) is sent to CPU_B if the same bit in the INT_PEND1 * + * register is set. Bits 31:0 can generate either an L3 or L2 * + * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only * + * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR, * + * XB_ERROR and MD_CORR_ERROR bits. * + * * + ************************************************************************/ + + + + +typedef union pi_int_mask1_b_u { + bdrkreg_t pi_int_mask1_b_regval; + struct { + bdrkreg_t imb_int_mask1 : 64; + } pi_int_mask1_b_fld_s; +} pi_int_mask1_b_u_t; + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. These registers do * + * not have access protection. A store to this location by a CPU will * + * cause the bit corresponding to the source's region to be set in * + * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B) * + * determines on a bit-per-region basis whether a CPU-to-CPU * + * interrupt is pending CPU_A (or CPU_B). * + * * + ************************************************************************/ + + + + +typedef union pi_cc_pend_set_a_u { + bdrkreg_t pi_cc_pend_set_a_regval; + struct { + bdrkreg_t cpsa_cc_pend : 64; + } pi_cc_pend_set_a_fld_s; +} pi_cc_pend_set_a_u_t; + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. These registers do * + * not have access protection. A store to this location by a CPU will * + * cause the bit corresponding to the source's region to be set in * + * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B) * + * determines on a bit-per-region basis whether a CPU-to-CPU * + * interrupt is pending CPU_A (or CPU_B). * + * * + ************************************************************************/ + + + + +typedef union pi_cc_pend_set_b_u { + bdrkreg_t pi_cc_pend_set_b_regval; + struct { + bdrkreg_t cpsb_cc_pend : 64; + } pi_cc_pend_set_b_fld_s; +} pi_cc_pend_set_b_u_t; + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Reading this * + * location will return the contents of CC_PEND_A (or CC_PEND_B). * + * Writing this location will clear the bits corresponding to which * + * data bits are driven high during the store; therefore, storing all * + * ones would clear all bits. * + * * + ************************************************************************/ + + + + +typedef union pi_cc_pend_clr_a_u { + bdrkreg_t pi_cc_pend_clr_a_regval; + struct { + bdrkreg_t cpca_cc_pend : 64; + } pi_cc_pend_clr_a_fld_s; +} pi_cc_pend_clr_a_u_t; + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Reading this * + * location will return the contents of CC_PEND_A (or CC_PEND_B). * + * Writing this location will clear the bits corresponding to which * + * data bits are driven high during the store; therefore, storing all * + * ones would clear all bits. * + * * + ************************************************************************/ + + + + +typedef union pi_cc_pend_clr_b_u { + bdrkreg_t pi_cc_pend_clr_b_regval; + struct { + bdrkreg_t cpcb_cc_pend : 64; + } pi_cc_pend_clr_b_fld_s; +} pi_cc_pend_clr_b_u_t; + + + + +/************************************************************************ + * * + * This read/write register masks the contents of both CC_PEND_A and * + * CC_PEND_B. * + * * + ************************************************************************/ + + + + +typedef union pi_cc_mask_u { + bdrkreg_t pi_cc_mask_regval; + struct { + bdrkreg_t cm_cc_mask : 64; + } pi_cc_mask_fld_s; +} pi_cc_mask_u_t; + + + + +/************************************************************************ + * * + * This read/write register redirects INT_PEND1[31:0] from L3 to L2 * + * interrupt level.Bit 4 in this register is used to enable error * + * interrupt forwarding to the II. When this bit is set, if any of * + * the three memory interrupts (correctable error, uncorrectable * + * error, or page migration), or the NI, LB or XB error interrupts * + * are set, the PI_II_ERROR_INT wire will be asserted. When this wire * + * is asserted, the II will send an interrupt to the node specified * + * in its IIDSR (Interrupt Destination Register). This allows these * + * interrupts to be forwarded to another node. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_int_pend1_remap_u { + bdrkreg_t pi_int_pend1_remap_regval; + struct { + bdrkreg_t ipr_remap_0 : 1; + bdrkreg_t ipr_remap_1 : 1; + bdrkreg_t ipr_remap_2 : 1; + bdrkreg_t ipr_remap_3 : 1; + bdrkreg_t ipr_error_forward : 1; + bdrkreg_t ipr_reserved : 59; + } pi_int_pend1_remap_fld_s; +} pi_int_pend1_remap_u_t; + +#else + +typedef union pi_int_pend1_remap_u { + bdrkreg_t pi_int_pend1_remap_regval; + struct { + bdrkreg_t ipr_reserved : 59; + bdrkreg_t ipr_error_forward : 1; + bdrkreg_t ipr_remap_3 : 1; + bdrkreg_t ipr_remap_2 : 1; + bdrkreg_t ipr_remap_1 : 1; + bdrkreg_t ipr_remap_0 : 1; + } pi_int_pend1_remap_fld_s; +} pi_int_pend1_remap_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. When the real time * + * counter (RT_Counter) is equal to the value in this register, the * + * RT_INT_PEND register is set, which causes a Level-4 interrupt to * + * be sent to the processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_rt_compare_a_u { + bdrkreg_t pi_rt_compare_a_regval; + struct { + bdrkreg_t rca_rt_compare : 55; + bdrkreg_t rca_rsvd : 9; + } pi_rt_compare_a_fld_s; +} pi_rt_compare_a_u_t; + +#else + +typedef union pi_rt_compare_a_u { + bdrkreg_t pi_rt_compare_a_regval; + struct { + bdrkreg_t rca_rsvd : 9; + bdrkreg_t rca_rt_compare : 55; + } pi_rt_compare_a_fld_s; +} pi_rt_compare_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. When the real time * + * counter (RT_Counter) is equal to the value in this register, the * + * RT_INT_PEND register is set, which causes a Level-4 interrupt to * + * be sent to the processor. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_rt_compare_b_u { + bdrkreg_t pi_rt_compare_b_regval; + struct { + bdrkreg_t rcb_rt_compare : 55; + bdrkreg_t rcb_rsvd : 9; + } pi_rt_compare_b_fld_s; +} pi_rt_compare_b_u_t; + +#else + +typedef union pi_rt_compare_b_u { + bdrkreg_t pi_rt_compare_b_regval; + struct { + bdrkreg_t rcb_rsvd : 9; + bdrkreg_t rcb_rt_compare : 55; + } pi_rt_compare_b_fld_s; +} pi_rt_compare_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * When the least significant 32 bits of the real time counter * + * (RT_Counter) are equal to the value in this register, the * + * PROF_INT_PEND_A and PROF_INT_PEND_B registers are set to 0x1. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_profile_compare_u { + bdrkreg_t pi_profile_compare_regval; + struct { + bdrkreg_t pc_profile_compare : 32; + bdrkreg_t pc_rsvd : 32; + } pi_profile_compare_fld_s; +} pi_profile_compare_u_t; + +#else + +typedef union pi_profile_compare_u { + bdrkreg_t pi_profile_compare_regval; + struct { + bdrkreg_t pc_rsvd : 32; + bdrkreg_t pc_profile_compare : 32; + } pi_profile_compare_fld_s; +} pi_profile_compare_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. If the bit in the * + * corresponding RT_INT_EN_A/B register is set, the processor's level * + * 5 interrupt is set to the value of the RTC_INT_PEND bit in this * + * register. Storing any value to this location will clear the * + * RTC_INT_PEND bit in the register. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_rt_int_pend_a_u { + bdrkreg_t pi_rt_int_pend_a_regval; + struct { + bdrkreg_t ripa_rtc_int_pend : 1; + bdrkreg_t ripa_rsvd : 63; + } pi_rt_int_pend_a_fld_s; +} pi_rt_int_pend_a_u_t; + +#else + +typedef union pi_rt_int_pend_a_u { + bdrkreg_t pi_rt_int_pend_a_regval; + struct { + bdrkreg_t ripa_rsvd : 63; + bdrkreg_t ripa_rtc_int_pend : 1; + } pi_rt_int_pend_a_fld_s; +} pi_rt_int_pend_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. If the bit in the * + * corresponding RT_INT_EN_A/B register is set, the processor's level * + * 5 interrupt is set to the value of the RTC_INT_PEND bit in this * + * register. Storing any value to this location will clear the * + * RTC_INT_PEND bit in the register. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_rt_int_pend_b_u { + bdrkreg_t pi_rt_int_pend_b_regval; + struct { + bdrkreg_t ripb_rtc_int_pend : 1; + bdrkreg_t ripb_rsvd : 63; + } pi_rt_int_pend_b_fld_s; +} pi_rt_int_pend_b_u_t; + +#else + +typedef union pi_rt_int_pend_b_u { + bdrkreg_t pi_rt_int_pend_b_regval; + struct { + bdrkreg_t ripb_rsvd : 63; + bdrkreg_t ripb_rtc_int_pend : 1; + } pi_rt_int_pend_b_fld_s; +} pi_rt_int_pend_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Both registers are * + * set when the PROFILE_COMPARE register is equal to bits [31:0] of * + * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B * + * register is set, the processor's level 5 interrupt is set to the * + * value of the PROF_INT_PEND bit in this register. Storing any value * + * to this location will clear the PROF_INT_PEND bit in the register. * + * The reason for having A and B versions of this register is that * + * they need to be cleared independently. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_prof_int_pend_a_u { + bdrkreg_t pi_prof_int_pend_a_regval; + struct { + bdrkreg_t pipa_prof_int_pend : 1; + bdrkreg_t pipa_rsvd : 63; + } pi_prof_int_pend_a_fld_s; +} pi_prof_int_pend_a_u_t; + +#else + +typedef union pi_prof_int_pend_a_u { + bdrkreg_t pi_prof_int_pend_a_regval; + struct { + bdrkreg_t pipa_rsvd : 63; + bdrkreg_t pipa_prof_int_pend : 1; + } pi_prof_int_pend_a_fld_s; +} pi_prof_int_pend_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Both registers are * + * set when the PROFILE_COMPARE register is equal to bits [31:0] of * + * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B * + * register is set, the processor's level 5 interrupt is set to the * + * value of the PROF_INT_PEND bit in this register. Storing any value * + * to this location will clear the PROF_INT_PEND bit in the register. * + * The reason for having A and B versions of this register is that * + * they need to be cleared independently. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_prof_int_pend_b_u { + bdrkreg_t pi_prof_int_pend_b_regval; + struct { + bdrkreg_t pipb_prof_int_pend : 1; + bdrkreg_t pipb_rsvd : 63; + } pi_prof_int_pend_b_fld_s; +} pi_prof_int_pend_b_u_t; + +#else + +typedef union pi_prof_int_pend_b_u { + bdrkreg_t pi_prof_int_pend_b_regval; + struct { + bdrkreg_t pipb_rsvd : 63; + bdrkreg_t pipb_prof_int_pend : 1; + } pi_prof_int_pend_b_fld_s; +} pi_prof_int_pend_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Enables RTC * + * interrupt to the associated CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_rt_int_en_a_u { + bdrkreg_t pi_rt_int_en_a_regval; + struct { + bdrkreg_t riea_rtc_int_en : 1; + bdrkreg_t riea_rsvd : 63; + } pi_rt_int_en_a_fld_s; +} pi_rt_int_en_a_u_t; + +#else + +typedef union pi_rt_int_en_a_u { + bdrkreg_t pi_rt_int_en_a_regval; + struct { + bdrkreg_t riea_rsvd : 63; + bdrkreg_t riea_rtc_int_en : 1; + } pi_rt_int_en_a_fld_s; +} pi_rt_int_en_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Enables RTC * + * interrupt to the associated CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_rt_int_en_b_u { + bdrkreg_t pi_rt_int_en_b_regval; + struct { + bdrkreg_t rieb_rtc_int_en : 1; + bdrkreg_t rieb_rsvd : 63; + } pi_rt_int_en_b_fld_s; +} pi_rt_int_en_b_u_t; + +#else + +typedef union pi_rt_int_en_b_u { + bdrkreg_t pi_rt_int_en_b_regval; + struct { + bdrkreg_t rieb_rsvd : 63; + bdrkreg_t rieb_rtc_int_en : 1; + } pi_rt_int_en_b_fld_s; +} pi_rt_int_en_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Enables profiling * + * interrupt to the associated CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_prof_int_en_a_u { + bdrkreg_t pi_prof_int_en_a_regval; + struct { + bdrkreg_t piea_prof_int_en : 1; + bdrkreg_t piea_rsvd : 63; + } pi_prof_int_en_a_fld_s; +} pi_prof_int_en_a_u_t; + +#else + +typedef union pi_prof_int_en_a_u { + bdrkreg_t pi_prof_int_en_a_regval; + struct { + bdrkreg_t piea_rsvd : 63; + bdrkreg_t piea_prof_int_en : 1; + } pi_prof_int_en_a_fld_s; +} pi_prof_int_en_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. Enables profiling * + * interrupt to the associated CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_prof_int_en_b_u { + bdrkreg_t pi_prof_int_en_b_regval; + struct { + bdrkreg_t pieb_prof_int_en : 1; + bdrkreg_t pieb_rsvd : 63; + } pi_prof_int_en_b_fld_s; +} pi_prof_int_en_b_u_t; + +#else + +typedef union pi_prof_int_en_b_u { + bdrkreg_t pi_prof_int_en_b_regval; + struct { + bdrkreg_t pieb_rsvd : 63; + bdrkreg_t pieb_prof_int_en : 1; + } pi_prof_int_en_b_fld_s; +} pi_prof_int_en_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register controls operation of the debug data from the PI, * + * along with Debug_Sel[2:0] from the Debug module. For some values * + * of Debug_Sel[2:0], the B_SEL bit selects whether the debug bits * + * are looking at the processor A or processor B logic. The remaining * + * bits select which signal(s) are ORed to create DebugData bits 31 * + * and 30 for all of the PI debug selections. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_debug_sel_u { + bdrkreg_t pi_debug_sel_regval; + struct { + bdrkreg_t ds_low_t5cc_a : 1; + bdrkreg_t ds_low_t5cc_b : 1; + bdrkreg_t ds_low_totcc_a : 1; + bdrkreg_t ds_low_totcc_b : 1; + bdrkreg_t ds_low_reqcc_a : 1; + bdrkreg_t ds_low_reqcc_b : 1; + bdrkreg_t ds_low_rplcc_a : 1; + bdrkreg_t ds_low_rplcc_b : 1; + bdrkreg_t ds_low_intcc : 1; + bdrkreg_t ds_low_perf_inc_a_0 : 1; + bdrkreg_t ds_low_perf_inc_a_1 : 1; + bdrkreg_t ds_low_perf_inc_b_0 : 1; + bdrkreg_t ds_low_perf_inc_b_1 : 1; + bdrkreg_t ds_high_t5cc_a : 1; + bdrkreg_t ds_high_t5cc_b : 1; + bdrkreg_t ds_high_totcc_a : 1; + bdrkreg_t ds_high_totcc_b : 1; + bdrkreg_t ds_high_reqcc_a : 1; + bdrkreg_t ds_high_reqcc_b : 1; + bdrkreg_t ds_high_rplcc_a : 1; + bdrkreg_t ds_high_rplcc_b : 1; + bdrkreg_t ds_high_intcc : 1; + bdrkreg_t ds_high_perf_inc_a_0 : 1; + bdrkreg_t ds_high_perf_inc_a_1 : 1; + bdrkreg_t ds_high_perf_inc_b_0 : 1; + bdrkreg_t ds_high_perf_inc_b_1 : 1; + bdrkreg_t ds_b_sel : 1; + bdrkreg_t ds_rsvd : 37; + } pi_debug_sel_fld_s; +} pi_debug_sel_u_t; + +#else + +typedef union pi_debug_sel_u { + bdrkreg_t pi_debug_sel_regval; + struct { + bdrkreg_t ds_rsvd : 37; + bdrkreg_t ds_b_sel : 1; + bdrkreg_t ds_high_perf_inc_b_1 : 1; + bdrkreg_t ds_high_perf_inc_b_0 : 1; + bdrkreg_t ds_high_perf_inc_a_1 : 1; + bdrkreg_t ds_high_perf_inc_a_0 : 1; + bdrkreg_t ds_high_intcc : 1; + bdrkreg_t ds_high_rplcc_b : 1; + bdrkreg_t ds_high_rplcc_a : 1; + bdrkreg_t ds_high_reqcc_b : 1; + bdrkreg_t ds_high_reqcc_a : 1; + bdrkreg_t ds_high_totcc_b : 1; + bdrkreg_t ds_high_totcc_a : 1; + bdrkreg_t ds_high_t5cc_b : 1; + bdrkreg_t ds_high_t5cc_a : 1; + bdrkreg_t ds_low_perf_inc_b_1 : 1; + bdrkreg_t ds_low_perf_inc_b_0 : 1; + bdrkreg_t ds_low_perf_inc_a_1 : 1; + bdrkreg_t ds_low_perf_inc_a_0 : 1; + bdrkreg_t ds_low_intcc : 1; + bdrkreg_t ds_low_rplcc_b : 1; + bdrkreg_t ds_low_rplcc_a : 1; + bdrkreg_t ds_low_reqcc_b : 1; + bdrkreg_t ds_low_reqcc_a : 1; + bdrkreg_t ds_low_totcc_b : 1; + bdrkreg_t ds_low_totcc_a : 1; + bdrkreg_t ds_low_t5cc_b : 1; + bdrkreg_t ds_low_t5cc_a : 1; + } pi_debug_sel_fld_s; +} pi_debug_sel_u_t; + +#endif + + +/************************************************************************ + * * + * A write to this register allows a single bit in the INT_PEND0 or * + * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is * + * modified in INT_PEND0, while if 6 is set, a bit is modified in * + * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine * + * which bit in the register is effected. The value of 8 will * + * determine whether the desired bit is set (8=1) or cleared (8=0). * + * This is the only register which is accessible by IO issued PWRI * + * command and is protected through the IO_PROTECT register. If the * + * region bit in the IO_PROTECT is not set then a WERR reply is * + * issued. CPU access is controlled through CPU_PROTECT. The contents * + * of this register are masked with the contents of INT_MASK_A * + * (INT_MASK_B) to determine whether an L2 interrupt is issued to * + * CPU_A (CPU_B). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_int_pend_mod_alias_u { + bdrkreg_t pi_int_pend_mod_alias_regval; + struct { + bdrkreg_t ipma_bit_select : 6; + bdrkreg_t ipma_reg_select : 1; + bdrkreg_t ipma_rsvd_1 : 1; + bdrkreg_t ipma_value : 1; + bdrkreg_t ipma_rsvd : 55; + } pi_int_pend_mod_alias_fld_s; +} pi_int_pend_mod_alias_u_t; + +#else + +typedef union pi_int_pend_mod_alias_u { + bdrkreg_t pi_int_pend_mod_alias_regval; + struct { + bdrkreg_t ipma_rsvd : 55; + bdrkreg_t ipma_value : 1; + bdrkreg_t ipma_rsvd_1 : 1; + bdrkreg_t ipma_reg_select : 1; + bdrkreg_t ipma_bit_select : 6; + } pi_int_pend_mod_alias_fld_s; +} pi_int_pend_mod_alias_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. This register * + * specifies the value of the Graphics Page. Uncached writes into the * + * Graphics Page (with uncached attribute of IO) are done with GFXWS * + * commands rather than the normal PWRI commands. GFXWS commands are * + * tracked with the graphics credit counters. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_page_a_u { + bdrkreg_t pi_gfx_page_a_regval; + struct { + bdrkreg_t gpa_rsvd_1 : 17; + bdrkreg_t gpa_gfx_page_addr : 23; + bdrkreg_t gpa_en_gfx_page : 1; + bdrkreg_t gpa_rsvd : 23; + } pi_gfx_page_a_fld_s; +} pi_gfx_page_a_u_t; + +#else + +typedef union pi_gfx_page_a_u { + bdrkreg_t pi_gfx_page_a_regval; + struct { + bdrkreg_t gpa_rsvd : 23; + bdrkreg_t gpa_en_gfx_page : 1; + bdrkreg_t gpa_gfx_page_addr : 23; + bdrkreg_t gpa_rsvd_1 : 17; + } pi_gfx_page_a_fld_s; +} pi_gfx_page_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. This register * + * counts graphics credits. This counter is decremented for each * + * doubleword sent to graphics with GFXWS or GFXWL commands. It is * + * incremented for each doubleword acknowledge from graphics. When * + * this counter has a smaller value than the GFX_BIAS register, * + * SysWrRdy_L is deasserted, an interrupt is sent to the processor, * + * and SysWrRdy_L is allowed to be asserted again. This is the basic * + * mechanism for flow-controlling graphics writes. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_credit_cntr_a_u { + bdrkreg_t pi_gfx_credit_cntr_a_regval; + struct { + bdrkreg_t gcca_gfx_credit_cntr : 12; + bdrkreg_t gcca_rsvd : 52; + } pi_gfx_credit_cntr_a_fld_s; +} pi_gfx_credit_cntr_a_u_t; + +#else + +typedef union pi_gfx_credit_cntr_a_u { + bdrkreg_t pi_gfx_credit_cntr_a_regval; + struct { + bdrkreg_t gcca_rsvd : 52; + bdrkreg_t gcca_gfx_credit_cntr : 12; + } pi_gfx_credit_cntr_a_fld_s; +} pi_gfx_credit_cntr_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. When the graphics * + * credit counter is less than or equal to this value, a flow control * + * interrupt is sent. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_bias_a_u { + bdrkreg_t pi_gfx_bias_a_regval; + struct { + bdrkreg_t gba_gfx_bias : 12; + bdrkreg_t gba_rsvd : 52; + } pi_gfx_bias_a_fld_s; +} pi_gfx_bias_a_u_t; + +#else + +typedef union pi_gfx_bias_a_u { + bdrkreg_t pi_gfx_bias_a_regval; + struct { + bdrkreg_t gba_rsvd : 52; + bdrkreg_t gba_gfx_bias : 12; + } pi_gfx_bias_a_fld_s; +} pi_gfx_bias_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There is one of these registers for each CPU. When * + * this counter reaches the value of the GFX_INT_CMP register, an * + * interrupt is sent to the associated processor. At each clock * + * cycle, the value in this register can be changed by any one of the * + * following actions: * + * - Written by software. * + * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or * + * soft reset occurs, thus preventing an additional interrupt. * + * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. * + * - Incremented (by one at each clock) for each clock that the * + * GFX_CREDIT_CNTR is less than or equal to zero. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_int_cntr_a_u { + bdrkreg_t pi_gfx_int_cntr_a_regval; + struct { + bdrkreg_t gica_gfx_int_cntr : 26; + bdrkreg_t gica_rsvd : 38; + } pi_gfx_int_cntr_a_fld_s; +} pi_gfx_int_cntr_a_u_t; + +#else + +typedef union pi_gfx_int_cntr_a_u { + bdrkreg_t pi_gfx_int_cntr_a_regval; + struct { + bdrkreg_t gica_rsvd : 38; + bdrkreg_t gica_gfx_int_cntr : 26; + } pi_gfx_int_cntr_a_fld_s; +} pi_gfx_int_cntr_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. The value in this * + * register is loaded into the GFX_INT_CNTR register when an * + * interrupt, NMI, or soft reset is sent to the processor. The value * + * in this register is compared to the value of GFX_INT_CNTR and an * + * interrupt is sent when they become equal. * + * * + ************************************************************************/ + + + + +#ifdef LINUX + +typedef union pi_gfx_int_cmp_a_u { + bdrkreg_t pi_gfx_int_cmp_a_regval; + struct { + bdrkreg_t gica_gfx_int_cmp : 26; + bdrkreg_t gica_rsvd : 38; + } pi_gfx_int_cmp_a_fld_s; +} pi_gfx_int_cmp_a_u_t; + +#else + +typedef union pi_gfx_int_cmp_a_u { + bdrkreg_t pi_gfx_int_cmp_a_regval; + struct { + bdrkreg_t gica_rsvd : 38; + bdrkreg_t gica_gfx_int_cmp : 26; + } pi_gfx_int_cmp_a_fld_s; +} pi_gfx_int_cmp_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. This register * + * specifies the value of the Graphics Page. Uncached writes into the * + * Graphics Page (with uncached attribute of IO) are done with GFXWS * + * commands rather than the normal PWRI commands. GFXWS commands are * + * tracked with the graphics credit counters. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_page_b_u { + bdrkreg_t pi_gfx_page_b_regval; + struct { + bdrkreg_t gpb_rsvd_1 : 17; + bdrkreg_t gpb_gfx_page_addr : 23; + bdrkreg_t gpb_en_gfx_page : 1; + bdrkreg_t gpb_rsvd : 23; + } pi_gfx_page_b_fld_s; +} pi_gfx_page_b_u_t; + +#else + +typedef union pi_gfx_page_b_u { + bdrkreg_t pi_gfx_page_b_regval; + struct { + bdrkreg_t gpb_rsvd : 23; + bdrkreg_t gpb_en_gfx_page : 1; + bdrkreg_t gpb_gfx_page_addr : 23; + bdrkreg_t gpb_rsvd_1 : 17; + } pi_gfx_page_b_fld_s; +} pi_gfx_page_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. This register * + * counts graphics credits. This counter is decremented for each * + * doubleword sent to graphics with GFXWS or GFXWL commands. It is * + * incremented for each doubleword acknowledge from graphics. When * + * this counter has a smaller value than the GFX_BIAS register, * + * SysWrRdy_L is deasserted, an interrupt is sent to the processor, * + * and SysWrRdy_L is allowed to be asserted again. This is the basic * + * mechanism for flow-controlling graphics writes. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_credit_cntr_b_u { + bdrkreg_t pi_gfx_credit_cntr_b_regval; + struct { + bdrkreg_t gccb_gfx_credit_cntr : 12; + bdrkreg_t gccb_rsvd : 52; + } pi_gfx_credit_cntr_b_fld_s; +} pi_gfx_credit_cntr_b_u_t; + +#else + +typedef union pi_gfx_credit_cntr_b_u { + bdrkreg_t pi_gfx_credit_cntr_b_regval; + struct { + bdrkreg_t gccb_rsvd : 52; + bdrkreg_t gccb_gfx_credit_cntr : 12; + } pi_gfx_credit_cntr_b_fld_s; +} pi_gfx_credit_cntr_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. When the graphics * + * credit counter is less than or equal to this value, a flow control * + * interrupt is sent. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_bias_b_u { + bdrkreg_t pi_gfx_bias_b_regval; + struct { + bdrkreg_t gbb_gfx_bias : 12; + bdrkreg_t gbb_rsvd : 52; + } pi_gfx_bias_b_fld_s; +} pi_gfx_bias_b_u_t; + +#else + +typedef union pi_gfx_bias_b_u { + bdrkreg_t pi_gfx_bias_b_regval; + struct { + bdrkreg_t gbb_rsvd : 52; + bdrkreg_t gbb_gfx_bias : 12; + } pi_gfx_bias_b_fld_s; +} pi_gfx_bias_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There is one of these registers for each CPU. When * + * this counter reaches the value of the GFX_INT_CMP register, an * + * interrupt is sent to the associated processor. At each clock * + * cycle, the value in this register can be changed by any one of the * + * following actions: * + * - Written by software. * + * - Loaded with the value of GFX_INT_CMP, when an interrupt, NMI, or * + * soft reset occurs, thus preventing an additional interrupt. * + * - Zeroed, when the GFX_CREDIT_CNTR rises above the bias value. * + * - Incremented (by one at each clock) for each clock that the * + * GFX_CREDIT_CNTR is less than or equal to zero. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_int_cntr_b_u { + bdrkreg_t pi_gfx_int_cntr_b_regval; + struct { + bdrkreg_t gicb_gfx_int_cntr : 26; + bdrkreg_t gicb_rsvd : 38; + } pi_gfx_int_cntr_b_fld_s; +} pi_gfx_int_cntr_b_u_t; + +#else + +typedef union pi_gfx_int_cntr_b_u { + bdrkreg_t pi_gfx_int_cntr_b_regval; + struct { + bdrkreg_t gicb_rsvd : 38; + bdrkreg_t gicb_gfx_int_cntr : 26; + } pi_gfx_int_cntr_b_fld_s; +} pi_gfx_int_cntr_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. The value in this * + * register is loaded into the GFX_INT_CNTR register when an * + * interrupt, NMI, or soft reset is sent to the processor. The value * + * in this register is compared to the value of GFX_INT_CNTR and an * + * interrupt is sent when they become equal. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_int_cmp_b_u { + bdrkreg_t pi_gfx_int_cmp_b_regval; + struct { + bdrkreg_t gicb_gfx_int_cmp : 26; + bdrkreg_t gicb_rsvd : 38; + } pi_gfx_int_cmp_b_fld_s; +} pi_gfx_int_cmp_b_u_t; + +#else + +typedef union pi_gfx_int_cmp_b_u { + bdrkreg_t pi_gfx_int_cmp_b_regval; + struct { + bdrkreg_t gicb_rsvd : 38; + bdrkreg_t gicb_gfx_int_cmp : 26; + } pi_gfx_int_cmp_b_fld_s; +} pi_gfx_int_cmp_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: A read of this register returns all sources of * + * Bedrock Error Interrupts. Storing to the write-with-clear location * + * clears any bit for which a one appears on the data bus. Storing to * + * the writable location does a direct write to all unreserved bits * + * (except for MEM_UNC). * + * In Synergy mode, the processor that is the source of the command * + * that got an error is independent of the A or B SysAD bus. So in * + * Synergy mode, Synergy provides the source processor number in bit * + * 52 of the SysAD bus in all commands. The PI saves this in the RRB * + * or WRB entry, and uses that value to determine which error bit (A * + * or B) to set, as well as which ERR_STATUS and spool registers to * + * use, for all error types in this register that are specified as an * + * error to CPU_A or CPU_B. * + * This register is not cleared at reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_int_pend_wr_u { + bdrkreg_t pi_err_int_pend_wr_regval; + struct { + bdrkreg_t eipw_spool_comp_b : 1; + bdrkreg_t eipw_spool_comp_a : 1; + bdrkreg_t eipw_spurious_b : 1; + bdrkreg_t eipw_spurious_a : 1; + bdrkreg_t eipw_wrb_terr_b : 1; + bdrkreg_t eipw_wrb_terr_a : 1; + bdrkreg_t eipw_wrb_werr_b : 1; + bdrkreg_t eipw_wrb_werr_a : 1; + bdrkreg_t eipw_sysstate_par_b : 1; + bdrkreg_t eipw_sysstate_par_a : 1; + bdrkreg_t eipw_sysad_data_ecc_b : 1; + bdrkreg_t eipw_sysad_data_ecc_a : 1; + bdrkreg_t eipw_sysad_addr_ecc_b : 1; + bdrkreg_t eipw_sysad_addr_ecc_a : 1; + bdrkreg_t eipw_syscmd_data_par_b : 1; + bdrkreg_t eipw_syscmd_data_par_a : 1; + bdrkreg_t eipw_syscmd_addr_par_b : 1; + bdrkreg_t eipw_syscmd_addr_par_a : 1; + bdrkreg_t eipw_spool_err_b : 1; + bdrkreg_t eipw_spool_err_a : 1; + bdrkreg_t eipw_ue_uncached_b : 1; + bdrkreg_t eipw_ue_uncached_a : 1; + bdrkreg_t eipw_sysstate_tag_b : 1; + bdrkreg_t eipw_sysstate_tag_a : 1; + bdrkreg_t eipw_mem_unc : 1; + bdrkreg_t eipw_sysad_bad_data_b : 1; + bdrkreg_t eipw_sysad_bad_data_a : 1; + bdrkreg_t eipw_ue_cached_b : 1; + bdrkreg_t eipw_ue_cached_a : 1; + bdrkreg_t eipw_pkt_len_err_b : 1; + bdrkreg_t eipw_pkt_len_err_a : 1; + bdrkreg_t eipw_irb_err_b : 1; + bdrkreg_t eipw_irb_err_a : 1; + bdrkreg_t eipw_irb_timeout_b : 1; + bdrkreg_t eipw_irb_timeout_a : 1; + bdrkreg_t eipw_rsvd : 29; + } pi_err_int_pend_wr_fld_s; +} pi_err_int_pend_wr_u_t; + +#else + +typedef union pi_err_int_pend_wr_u { + bdrkreg_t pi_err_int_pend_wr_regval; + struct { + bdrkreg_t eipw_rsvd : 29; + bdrkreg_t eipw_irb_timeout_a : 1; + bdrkreg_t eipw_irb_timeout_b : 1; + bdrkreg_t eipw_irb_err_a : 1; + bdrkreg_t eipw_irb_err_b : 1; + bdrkreg_t eipw_pkt_len_err_a : 1; + bdrkreg_t eipw_pkt_len_err_b : 1; + bdrkreg_t eipw_ue_cached_a : 1; + bdrkreg_t eipw_ue_cached_b : 1; + bdrkreg_t eipw_sysad_bad_data_a : 1; + bdrkreg_t eipw_sysad_bad_data_b : 1; + bdrkreg_t eipw_mem_unc : 1; + bdrkreg_t eipw_sysstate_tag_a : 1; + bdrkreg_t eipw_sysstate_tag_b : 1; + bdrkreg_t eipw_ue_uncached_a : 1; + bdrkreg_t eipw_ue_uncached_b : 1; + bdrkreg_t eipw_spool_err_a : 1; + bdrkreg_t eipw_spool_err_b : 1; + bdrkreg_t eipw_syscmd_addr_par_a : 1; + bdrkreg_t eipw_syscmd_addr_par_b : 1; + bdrkreg_t eipw_syscmd_data_par_a : 1; + bdrkreg_t eipw_syscmd_data_par_b : 1; + bdrkreg_t eipw_sysad_addr_ecc_a : 1; + bdrkreg_t eipw_sysad_addr_ecc_b : 1; + bdrkreg_t eipw_sysad_data_ecc_a : 1; + bdrkreg_t eipw_sysad_data_ecc_b : 1; + bdrkreg_t eipw_sysstate_par_a : 1; + bdrkreg_t eipw_sysstate_par_b : 1; + bdrkreg_t eipw_wrb_werr_a : 1; + bdrkreg_t eipw_wrb_werr_b : 1; + bdrkreg_t eipw_wrb_terr_a : 1; + bdrkreg_t eipw_wrb_terr_b : 1; + bdrkreg_t eipw_spurious_a : 1; + bdrkreg_t eipw_spurious_b : 1; + bdrkreg_t eipw_spool_comp_a : 1; + bdrkreg_t eipw_spool_comp_b : 1; + } pi_err_int_pend_wr_fld_s; +} pi_err_int_pend_wr_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: A read of this register returns all sources of * + * Bedrock Error Interrupts. Storing to the write-with-clear location * + * clears any bit for which a one appears on the data bus. Storing to * + * the writable location does a direct write to all unreserved bits * + * (except for MEM_UNC). * + * In Synergy mode, the processor that is the source of the command * + * that got an error is independent of the A or B SysAD bus. So in * + * Synergy mode, Synergy provides the source processor number in bit * + * 52 of the SysAD bus in all commands. The PI saves this in the RRB * + * or WRB entry, and uses that value to determine which error bit (A * + * or B) to set, as well as which ERR_STATUS and spool registers to * + * use, for all error types in this register that are specified as an * + * error to CPU_A or CPU_B. * + * This register is not cleared at reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_int_pend_u { + bdrkreg_t pi_err_int_pend_regval; + struct { + bdrkreg_t eip_spool_comp_b : 1; + bdrkreg_t eip_spool_comp_a : 1; + bdrkreg_t eip_spurious_b : 1; + bdrkreg_t eip_spurious_a : 1; + bdrkreg_t eip_wrb_terr_b : 1; + bdrkreg_t eip_wrb_terr_a : 1; + bdrkreg_t eip_wrb_werr_b : 1; + bdrkreg_t eip_wrb_werr_a : 1; + bdrkreg_t eip_sysstate_par_b : 1; + bdrkreg_t eip_sysstate_par_a : 1; + bdrkreg_t eip_sysad_data_ecc_b : 1; + bdrkreg_t eip_sysad_data_ecc_a : 1; + bdrkreg_t eip_sysad_addr_ecc_b : 1; + bdrkreg_t eip_sysad_addr_ecc_a : 1; + bdrkreg_t eip_syscmd_data_par_b : 1; + bdrkreg_t eip_syscmd_data_par_a : 1; + bdrkreg_t eip_syscmd_addr_par_b : 1; + bdrkreg_t eip_syscmd_addr_par_a : 1; + bdrkreg_t eip_spool_err_b : 1; + bdrkreg_t eip_spool_err_a : 1; + bdrkreg_t eip_ue_uncached_b : 1; + bdrkreg_t eip_ue_uncached_a : 1; + bdrkreg_t eip_sysstate_tag_b : 1; + bdrkreg_t eip_sysstate_tag_a : 1; + bdrkreg_t eip_mem_unc : 1; + bdrkreg_t eip_sysad_bad_data_b : 1; + bdrkreg_t eip_sysad_bad_data_a : 1; + bdrkreg_t eip_ue_cached_b : 1; + bdrkreg_t eip_ue_cached_a : 1; + bdrkreg_t eip_pkt_len_err_b : 1; + bdrkreg_t eip_pkt_len_err_a : 1; + bdrkreg_t eip_irb_err_b : 1; + bdrkreg_t eip_irb_err_a : 1; + bdrkreg_t eip_irb_timeout_b : 1; + bdrkreg_t eip_irb_timeout_a : 1; + bdrkreg_t eip_rsvd : 29; + } pi_err_int_pend_fld_s; +} pi_err_int_pend_u_t; + +#else + +typedef union pi_err_int_pend_u { + bdrkreg_t pi_err_int_pend_regval; + struct { + bdrkreg_t eip_rsvd : 29; + bdrkreg_t eip_irb_timeout_a : 1; + bdrkreg_t eip_irb_timeout_b : 1; + bdrkreg_t eip_irb_err_a : 1; + bdrkreg_t eip_irb_err_b : 1; + bdrkreg_t eip_pkt_len_err_a : 1; + bdrkreg_t eip_pkt_len_err_b : 1; + bdrkreg_t eip_ue_cached_a : 1; + bdrkreg_t eip_ue_cached_b : 1; + bdrkreg_t eip_sysad_bad_data_a : 1; + bdrkreg_t eip_sysad_bad_data_b : 1; + bdrkreg_t eip_mem_unc : 1; + bdrkreg_t eip_sysstate_tag_a : 1; + bdrkreg_t eip_sysstate_tag_b : 1; + bdrkreg_t eip_ue_uncached_a : 1; + bdrkreg_t eip_ue_uncached_b : 1; + bdrkreg_t eip_spool_err_a : 1; + bdrkreg_t eip_spool_err_b : 1; + bdrkreg_t eip_syscmd_addr_par_a : 1; + bdrkreg_t eip_syscmd_addr_par_b : 1; + bdrkreg_t eip_syscmd_data_par_a : 1; + bdrkreg_t eip_syscmd_data_par_b : 1; + bdrkreg_t eip_sysad_addr_ecc_a : 1; + bdrkreg_t eip_sysad_addr_ecc_b : 1; + bdrkreg_t eip_sysad_data_ecc_a : 1; + bdrkreg_t eip_sysad_data_ecc_b : 1; + bdrkreg_t eip_sysstate_par_a : 1; + bdrkreg_t eip_sysstate_par_b : 1; + bdrkreg_t eip_wrb_werr_a : 1; + bdrkreg_t eip_wrb_werr_b : 1; + bdrkreg_t eip_wrb_terr_a : 1; + bdrkreg_t eip_wrb_terr_b : 1; + bdrkreg_t eip_spurious_a : 1; + bdrkreg_t eip_spurious_b : 1; + bdrkreg_t eip_spool_comp_a : 1; + bdrkreg_t eip_spool_comp_b : 1; + } pi_err_int_pend_fld_s; +} pi_err_int_pend_u_t; + +#endif + + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. This read/write * + * register masks the contents of ERR_INT_PEND to determine which * + * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set * + * allows the interrupt. Only one processor in a Bedrock should * + * enable the Memory/Directory Uncorrectable Error bit. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_int_mask_a_u { + bdrkreg_t pi_err_int_mask_a_regval; + struct { + bdrkreg_t eima_mask : 35; + bdrkreg_t eima_rsvd : 29; + } pi_err_int_mask_a_fld_s; +} pi_err_int_mask_a_u_t; + +#else + +typedef union pi_err_int_mask_a_u { + bdrkreg_t pi_err_int_mask_a_regval; + struct { + bdrkreg_t eima_rsvd : 29; + bdrkreg_t eima_mask : 35; + } pi_err_int_mask_a_fld_s; +} pi_err_int_mask_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. This read/write * + * register masks the contents of ERR_INT_PEND to determine which * + * conditions cause a Level-6 interrupt to CPU_A or CPU_B. A bit set * + * allows the interrupt. Only one processor in a Bedrock should * + * enable the Memory/Directory Uncorrectable Error bit. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_int_mask_b_u { + bdrkreg_t pi_err_int_mask_b_regval; + struct { + bdrkreg_t eimb_mask : 35; + bdrkreg_t eimb_rsvd : 29; + } pi_err_int_mask_b_fld_s; +} pi_err_int_mask_b_u_t; + +#else + +typedef union pi_err_int_mask_b_u { + bdrkreg_t pi_err_int_mask_b_regval; + struct { + bdrkreg_t eimb_rsvd : 29; + bdrkreg_t eimb_mask : 35; + } pi_err_int_mask_b_fld_s; +} pi_err_int_mask_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There is one of these registers for each CPU. This * + * register is the address of the next write to the error stack. This * + * register is incremented after each such write. Only the low N bits * + * are incremented, where N is defined by the size of the error stack * + * specified in the ERR_STACK_SIZE register. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_stack_addr_a_u { + bdrkreg_t pi_err_stack_addr_a_regval; + struct { + bdrkreg_t esaa_rsvd_1 : 3; + bdrkreg_t esaa_addr : 30; + bdrkreg_t esaa_rsvd : 31; + } pi_err_stack_addr_a_fld_s; +} pi_err_stack_addr_a_u_t; + +#else + +typedef union pi_err_stack_addr_a_u { + bdrkreg_t pi_err_stack_addr_a_regval; + struct { + bdrkreg_t esaa_rsvd : 31; + bdrkreg_t esaa_addr : 30; + bdrkreg_t esaa_rsvd_1 : 3; + } pi_err_stack_addr_a_fld_s; +} pi_err_stack_addr_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: There is one of these registers for each CPU. This * + * register is the address of the next write to the error stack. This * + * register is incremented after each such write. Only the low N bits * + * are incremented, where N is defined by the size of the error stack * + * specified in the ERR_STACK_SIZE register. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_stack_addr_b_u { + bdrkreg_t pi_err_stack_addr_b_regval; + struct { + bdrkreg_t esab_rsvd_1 : 3; + bdrkreg_t esab_addr : 30; + bdrkreg_t esab_rsvd : 31; + } pi_err_stack_addr_b_fld_s; +} pi_err_stack_addr_b_u_t; + +#else + +typedef union pi_err_stack_addr_b_u { + bdrkreg_t pi_err_stack_addr_b_regval; + struct { + bdrkreg_t esab_rsvd : 31; + bdrkreg_t esab_addr : 30; + bdrkreg_t esab_rsvd_1 : 3; + } pi_err_stack_addr_b_fld_s; +} pi_err_stack_addr_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: Sets the size (number of 64-bit entries) in the * + * error stack that is spooled to local memory when an error occurs. * + * Table16 defines the format of each entry in the spooled error * + * stack. * + * This register is not reset by a soft reset. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_stack_size_u { + bdrkreg_t pi_err_stack_size_regval; + struct { + bdrkreg_t ess_size : 4; + bdrkreg_t ess_rsvd : 60; + } pi_err_stack_size_fld_s; +} pi_err_stack_size_u_t; + +#else + +typedef union pi_err_stack_size_u { + bdrkreg_t pi_err_stack_size_regval; + struct { + bdrkreg_t ess_rsvd : 60; + bdrkreg_t ess_size : 4; + } pi_err_stack_size_fld_s; +} pi_err_stack_size_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_A and ERR_STATUS1_A registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status0_a_u { + bdrkreg_t pi_err_status0_a_regval; + struct { + bdrkreg_t esa_error_type : 3; + bdrkreg_t esa_proc_req_num : 3; + bdrkreg_t esa_supplemental : 11; + bdrkreg_t esa_cmd : 8; + bdrkreg_t esa_addr : 37; + bdrkreg_t esa_over_run : 1; + bdrkreg_t esa_valid : 1; + } pi_err_status0_a_fld_s; +} pi_err_status0_a_u_t; + +#else + +typedef union pi_err_status0_a_u { + bdrkreg_t pi_err_status0_a_regval; + struct { + bdrkreg_t esa_valid : 1; + bdrkreg_t esa_over_run : 1; + bdrkreg_t esa_addr : 37; + bdrkreg_t esa_cmd : 8; + bdrkreg_t esa_supplemental : 11; + bdrkreg_t esa_proc_req_num : 3; + bdrkreg_t esa_error_type : 3; + } pi_err_status0_a_fld_s; +} pi_err_status0_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_A and ERR_STATUS1_A registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status0_a_clr_u { + bdrkreg_t pi_err_status0_a_clr_regval; + struct { + bdrkreg_t esac_error_type : 3; + bdrkreg_t esac_proc_req_num : 3; + bdrkreg_t esac_supplemental : 11; + bdrkreg_t esac_cmd : 8; + bdrkreg_t esac_addr : 37; + bdrkreg_t esac_over_run : 1; + bdrkreg_t esac_valid : 1; + } pi_err_status0_a_clr_fld_s; +} pi_err_status0_a_clr_u_t; + +#else + +typedef union pi_err_status0_a_clr_u { + bdrkreg_t pi_err_status0_a_clr_regval; + struct { + bdrkreg_t esac_valid : 1; + bdrkreg_t esac_over_run : 1; + bdrkreg_t esac_addr : 37; + bdrkreg_t esac_cmd : 8; + bdrkreg_t esac_supplemental : 11; + bdrkreg_t esac_proc_req_num : 3; + bdrkreg_t esac_error_type : 3; + } pi_err_status0_a_clr_fld_s; +} pi_err_status0_a_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_A and ERR_STATUS1_A registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status1_a_u { + bdrkreg_t pi_err_status1_a_regval; + struct { + bdrkreg_t esa_spool_count : 21; + bdrkreg_t esa_time_out_count : 8; + bdrkreg_t esa_inval_count : 10; + bdrkreg_t esa_crb_num : 3; + bdrkreg_t esa_wrb : 1; + bdrkreg_t esa_e_bits : 2; + bdrkreg_t esa_t_bit : 1; + bdrkreg_t esa_i_bit : 1; + bdrkreg_t esa_h_bit : 1; + bdrkreg_t esa_w_bit : 1; + bdrkreg_t esa_a_bit : 1; + bdrkreg_t esa_r_bit : 1; + bdrkreg_t esa_v_bit : 1; + bdrkreg_t esa_p_bit : 1; + bdrkreg_t esa_source : 11; + } pi_err_status1_a_fld_s; +} pi_err_status1_a_u_t; + +#else + +typedef union pi_err_status1_a_u { + bdrkreg_t pi_err_status1_a_regval; + struct { + bdrkreg_t esa_source : 11; + bdrkreg_t esa_p_bit : 1; + bdrkreg_t esa_v_bit : 1; + bdrkreg_t esa_r_bit : 1; + bdrkreg_t esa_a_bit : 1; + bdrkreg_t esa_w_bit : 1; + bdrkreg_t esa_h_bit : 1; + bdrkreg_t esa_i_bit : 1; + bdrkreg_t esa_t_bit : 1; + bdrkreg_t esa_e_bits : 2; + bdrkreg_t esa_wrb : 1; + bdrkreg_t esa_crb_num : 3; + bdrkreg_t esa_inval_count : 10; + bdrkreg_t esa_time_out_count : 8; + bdrkreg_t esa_spool_count : 21; + } pi_err_status1_a_fld_s; +} pi_err_status1_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_A and ERR_STATUS1_A registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status1_a_clr_u { + bdrkreg_t pi_err_status1_a_clr_regval; + struct { + bdrkreg_t esac_spool_count : 21; + bdrkreg_t esac_time_out_count : 8; + bdrkreg_t esac_inval_count : 10; + bdrkreg_t esac_crb_num : 3; + bdrkreg_t esac_wrb : 1; + bdrkreg_t esac_e_bits : 2; + bdrkreg_t esac_t_bit : 1; + bdrkreg_t esac_i_bit : 1; + bdrkreg_t esac_h_bit : 1; + bdrkreg_t esac_w_bit : 1; + bdrkreg_t esac_a_bit : 1; + bdrkreg_t esac_r_bit : 1; + bdrkreg_t esac_v_bit : 1; + bdrkreg_t esac_p_bit : 1; + bdrkreg_t esac_source : 11; + } pi_err_status1_a_clr_fld_s; +} pi_err_status1_a_clr_u_t; + +#else + +typedef union pi_err_status1_a_clr_u { + bdrkreg_t pi_err_status1_a_clr_regval; + struct { + bdrkreg_t esac_source : 11; + bdrkreg_t esac_p_bit : 1; + bdrkreg_t esac_v_bit : 1; + bdrkreg_t esac_r_bit : 1; + bdrkreg_t esac_a_bit : 1; + bdrkreg_t esac_w_bit : 1; + bdrkreg_t esac_h_bit : 1; + bdrkreg_t esac_i_bit : 1; + bdrkreg_t esac_t_bit : 1; + bdrkreg_t esac_e_bits : 2; + bdrkreg_t esac_wrb : 1; + bdrkreg_t esac_crb_num : 3; + bdrkreg_t esac_inval_count : 10; + bdrkreg_t esac_time_out_count : 8; + bdrkreg_t esac_spool_count : 21; + } pi_err_status1_a_clr_fld_s; +} pi_err_status1_a_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_B and ERR_STATUS1_B registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status0_b_u { + bdrkreg_t pi_err_status0_b_regval; + struct { + bdrkreg_t esb_error_type : 3; + bdrkreg_t esb_proc_request_number : 3; + bdrkreg_t esb_supplemental : 11; + bdrkreg_t esb_cmd : 8; + bdrkreg_t esb_addr : 37; + bdrkreg_t esb_over_run : 1; + bdrkreg_t esb_valid : 1; + } pi_err_status0_b_fld_s; +} pi_err_status0_b_u_t; + +#else + +typedef union pi_err_status0_b_u { + bdrkreg_t pi_err_status0_b_regval; + struct { + bdrkreg_t esb_valid : 1; + bdrkreg_t esb_over_run : 1; + bdrkreg_t esb_addr : 37; + bdrkreg_t esb_cmd : 8; + bdrkreg_t esb_supplemental : 11; + bdrkreg_t esb_proc_request_number : 3; + bdrkreg_t esb_error_type : 3; + } pi_err_status0_b_fld_s; +} pi_err_status0_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_B and ERR_STATUS1_B registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status0_b_clr_u { + bdrkreg_t pi_err_status0_b_clr_regval; + struct { + bdrkreg_t esbc_error_type : 3; + bdrkreg_t esbc_proc_request_number : 3; + bdrkreg_t esbc_supplemental : 11; + bdrkreg_t esbc_cmd : 8; + bdrkreg_t esbc_addr : 37; + bdrkreg_t esbc_over_run : 1; + bdrkreg_t esbc_valid : 1; + } pi_err_status0_b_clr_fld_s; +} pi_err_status0_b_clr_u_t; + +#else + +typedef union pi_err_status0_b_clr_u { + bdrkreg_t pi_err_status0_b_clr_regval; + struct { + bdrkreg_t esbc_valid : 1; + bdrkreg_t esbc_over_run : 1; + bdrkreg_t esbc_addr : 37; + bdrkreg_t esbc_cmd : 8; + bdrkreg_t esbc_supplemental : 11; + bdrkreg_t esbc_proc_request_number : 3; + bdrkreg_t esbc_error_type : 3; + } pi_err_status0_b_clr_fld_s; +} pi_err_status0_b_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_B and ERR_STATUS1_B registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status1_b_u { + bdrkreg_t pi_err_status1_b_regval; + struct { + bdrkreg_t esb_spool_count : 21; + bdrkreg_t esb_time_out_count : 8; + bdrkreg_t esb_inval_count : 10; + bdrkreg_t esb_crb_num : 3; + bdrkreg_t esb_wrb : 1; + bdrkreg_t esb_e_bits : 2; + bdrkreg_t esb_t_bit : 1; + bdrkreg_t esb_i_bit : 1; + bdrkreg_t esb_h_bit : 1; + bdrkreg_t esb_w_bit : 1; + bdrkreg_t esb_a_bit : 1; + bdrkreg_t esb_r_bit : 1; + bdrkreg_t esb_v_bit : 1; + bdrkreg_t esb_p_bit : 1; + bdrkreg_t esb_source : 11; + } pi_err_status1_b_fld_s; +} pi_err_status1_b_u_t; + +#else + +typedef union pi_err_status1_b_u { + bdrkreg_t pi_err_status1_b_regval; + struct { + bdrkreg_t esb_source : 11; + bdrkreg_t esb_p_bit : 1; + bdrkreg_t esb_v_bit : 1; + bdrkreg_t esb_r_bit : 1; + bdrkreg_t esb_a_bit : 1; + bdrkreg_t esb_w_bit : 1; + bdrkreg_t esb_h_bit : 1; + bdrkreg_t esb_i_bit : 1; + bdrkreg_t esb_t_bit : 1; + bdrkreg_t esb_e_bits : 2; + bdrkreg_t esb_wrb : 1; + bdrkreg_t esb_crb_num : 3; + bdrkreg_t esb_inval_count : 10; + bdrkreg_t esb_time_out_count : 8; + bdrkreg_t esb_spool_count : 21; + } pi_err_status1_b_fld_s; +} pi_err_status1_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. Writing this register with * + * the Write-clear address (with any data) clears both the * + * ERR_STATUS0_B and ERR_STATUS1_B registers. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_status1_b_clr_u { + bdrkreg_t pi_err_status1_b_clr_regval; + struct { + bdrkreg_t esbc_spool_count : 21; + bdrkreg_t esbc_time_out_count : 8; + bdrkreg_t esbc_inval_count : 10; + bdrkreg_t esbc_crb_num : 3; + bdrkreg_t esbc_wrb : 1; + bdrkreg_t esbc_e_bits : 2; + bdrkreg_t esbc_t_bit : 1; + bdrkreg_t esbc_i_bit : 1; + bdrkreg_t esbc_h_bit : 1; + bdrkreg_t esbc_w_bit : 1; + bdrkreg_t esbc_a_bit : 1; + bdrkreg_t esbc_r_bit : 1; + bdrkreg_t esbc_v_bit : 1; + bdrkreg_t esbc_p_bit : 1; + bdrkreg_t esbc_source : 11; + } pi_err_status1_b_clr_fld_s; +} pi_err_status1_b_clr_u_t; + +#else + +typedef union pi_err_status1_b_clr_u { + bdrkreg_t pi_err_status1_b_clr_regval; + struct { + bdrkreg_t esbc_source : 11; + bdrkreg_t esbc_p_bit : 1; + bdrkreg_t esbc_v_bit : 1; + bdrkreg_t esbc_r_bit : 1; + bdrkreg_t esbc_a_bit : 1; + bdrkreg_t esbc_w_bit : 1; + bdrkreg_t esbc_h_bit : 1; + bdrkreg_t esbc_i_bit : 1; + bdrkreg_t esbc_t_bit : 1; + bdrkreg_t esbc_e_bits : 2; + bdrkreg_t esbc_wrb : 1; + bdrkreg_t esbc_crb_num : 3; + bdrkreg_t esbc_inval_count : 10; + bdrkreg_t esbc_time_out_count : 8; + bdrkreg_t esbc_spool_count : 21; + } pi_err_status1_b_clr_fld_s; +} pi_err_status1_b_clr_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_spool_cmp_a_u { + bdrkreg_t pi_spool_cmp_a_regval; + struct { + bdrkreg_t sca_compare : 20; + bdrkreg_t sca_rsvd : 44; + } pi_spool_cmp_a_fld_s; +} pi_spool_cmp_a_u_t; + +#else + +typedef union pi_spool_cmp_a_u { + bdrkreg_t pi_spool_cmp_a_regval; + struct { + bdrkreg_t sca_rsvd : 44; + bdrkreg_t sca_compare : 20; + } pi_spool_cmp_a_fld_s; +} pi_spool_cmp_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_spool_cmp_b_u { + bdrkreg_t pi_spool_cmp_b_regval; + struct { + bdrkreg_t scb_compare : 20; + bdrkreg_t scb_rsvd : 44; + } pi_spool_cmp_b_fld_s; +} pi_spool_cmp_b_u_t; + +#else + +typedef union pi_spool_cmp_b_u { + bdrkreg_t pi_spool_cmp_b_regval; + struct { + bdrkreg_t scb_rsvd : 44; + bdrkreg_t scb_compare : 20; + } pi_spool_cmp_b_fld_s; +} pi_spool_cmp_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. A timeout can be * + * forced by writing one(s). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_crb_timeout_a_u { + bdrkreg_t pi_crb_timeout_a_regval; + struct { + bdrkreg_t cta_rrb : 4; + bdrkreg_t cta_wrb : 8; + bdrkreg_t cta_rsvd : 52; + } pi_crb_timeout_a_fld_s; +} pi_crb_timeout_a_u_t; + +#else + +typedef union pi_crb_timeout_a_u { + bdrkreg_t pi_crb_timeout_a_regval; + struct { + bdrkreg_t cta_rsvd : 52; + bdrkreg_t cta_wrb : 8; + bdrkreg_t cta_rrb : 4; + } pi_crb_timeout_a_fld_s; +} pi_crb_timeout_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. A timeout can be * + * forced by writing one(s). * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_crb_timeout_b_u { + bdrkreg_t pi_crb_timeout_b_regval; + struct { + bdrkreg_t ctb_rrb : 4; + bdrkreg_t ctb_wrb : 8; + bdrkreg_t ctb_rsvd : 52; + } pi_crb_timeout_b_fld_s; +} pi_crb_timeout_b_u_t; + +#else + +typedef union pi_crb_timeout_b_u { + bdrkreg_t pi_crb_timeout_b_regval; + struct { + bdrkreg_t ctb_rsvd : 52; + bdrkreg_t ctb_wrb : 8; + bdrkreg_t ctb_rrb : 4; + } pi_crb_timeout_b_fld_s; +} pi_crb_timeout_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register controls error checking and forwarding of SysAD * + * errors. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_sysad_errchk_en_u { + bdrkreg_t pi_sysad_errchk_en_regval; + struct { + bdrkreg_t see_ecc_gen_en : 1; + bdrkreg_t see_qual_gen_en : 1; + bdrkreg_t see_sadp_chk_en : 1; + bdrkreg_t see_cmdp_chk_en : 1; + bdrkreg_t see_state_chk_en : 1; + bdrkreg_t see_qual_chk_en : 1; + bdrkreg_t see_rsvd : 58; + } pi_sysad_errchk_en_fld_s; +} pi_sysad_errchk_en_u_t; + +#else + +typedef union pi_sysad_errchk_en_u { + bdrkreg_t pi_sysad_errchk_en_regval; + struct { + bdrkreg_t see_rsvd : 58; + bdrkreg_t see_qual_chk_en : 1; + bdrkreg_t see_state_chk_en : 1; + bdrkreg_t see_cmdp_chk_en : 1; + bdrkreg_t see_sadp_chk_en : 1; + bdrkreg_t see_qual_gen_en : 1; + bdrkreg_t see_ecc_gen_en : 1; + } pi_sysad_errchk_en_fld_s; +} pi_sysad_errchk_en_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. If any bit in this * + * register is set, then whenever reply data arrives with the UE * + * (uncorrectable error) indication set, the check-bits that are * + * generated and sent to the SysAD will be inverted corresponding to * + * the bits set in the register. This will also prevent the assertion * + * of the data quality indicator. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_force_bad_check_bit_a_u { + bdrkreg_t pi_force_bad_check_bit_a_regval; + struct { + bdrkreg_t fbcba_bad_check_bit : 8; + bdrkreg_t fbcba_rsvd : 56; + } pi_force_bad_check_bit_a_fld_s; +} pi_force_bad_check_bit_a_u_t; + +#else + +typedef union pi_force_bad_check_bit_a_u { + bdrkreg_t pi_force_bad_check_bit_a_regval; + struct { + bdrkreg_t fbcba_rsvd : 56; + bdrkreg_t fbcba_bad_check_bit : 8; + } pi_force_bad_check_bit_a_fld_s; +} pi_force_bad_check_bit_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. If any bit in this * + * register is set, then whenever reply data arrives with the UE * + * (uncorrectable error) indication set, the check-bits that are * + * generated and sent to the SysAD will be inverted corresponding to * + * the bits set in the register. This will also prevent the assertion * + * of the data quality indicator. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_force_bad_check_bit_b_u { + bdrkreg_t pi_force_bad_check_bit_b_regval; + struct { + bdrkreg_t fbcbb_bad_check_bit : 8; + bdrkreg_t fbcbb_rsvd : 56; + } pi_force_bad_check_bit_b_fld_s; +} pi_force_bad_check_bit_b_u_t; + +#else + +typedef union pi_force_bad_check_bit_b_u { + bdrkreg_t pi_force_bad_check_bit_b_regval; + struct { + bdrkreg_t fbcbb_rsvd : 56; + bdrkreg_t fbcbb_bad_check_bit : 8; + } pi_force_bad_check_bit_b_fld_s; +} pi_force_bad_check_bit_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. When a counter is * + * enabled, it increments each time a DNACK reply is received. The * + * counter is cleared when any other reply is received. The register * + * is cleared when the CNT_EN bit is zero. If a DNACK reply is * + * received when the counter equals the value in the NACK_CMP * + * register, the counter is cleared, an error response is sent to the * + * CPU instead of a nack response, and the NACK_INT_A/B bit is set in * + * INT_PEND1. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_nack_cnt_a_u { + bdrkreg_t pi_nack_cnt_a_regval; + struct { + bdrkreg_t nca_nack_cnt : 20; + bdrkreg_t nca_cnt_en : 1; + bdrkreg_t nca_rsvd : 43; + } pi_nack_cnt_a_fld_s; +} pi_nack_cnt_a_u_t; + +#else + +typedef union pi_nack_cnt_a_u { + bdrkreg_t pi_nack_cnt_a_regval; + struct { + bdrkreg_t nca_rsvd : 43; + bdrkreg_t nca_cnt_en : 1; + bdrkreg_t nca_nack_cnt : 20; + } pi_nack_cnt_a_fld_s; +} pi_nack_cnt_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * There is one of these registers for each CPU. When a counter is * + * enabled, it increments each time a DNACK reply is received. The * + * counter is cleared when any other reply is received. The register * + * is cleared when the CNT_EN bit is zero. If a DNACK reply is * + * received when the counter equals the value in the NACK_CMP * + * register, the counter is cleared, an error response is sent to the * + * CPU instead of a nack response, and the NACK_INT_A/B bit is set in * + * INT_PEND1. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_nack_cnt_b_u { + bdrkreg_t pi_nack_cnt_b_regval; + struct { + bdrkreg_t ncb_nack_cnt : 20; + bdrkreg_t ncb_cnt_en : 1; + bdrkreg_t ncb_rsvd : 43; + } pi_nack_cnt_b_fld_s; +} pi_nack_cnt_b_u_t; + +#else + +typedef union pi_nack_cnt_b_u { + bdrkreg_t pi_nack_cnt_b_regval; + struct { + bdrkreg_t ncb_rsvd : 43; + bdrkreg_t ncb_cnt_en : 1; + bdrkreg_t ncb_nack_cnt : 20; + } pi_nack_cnt_b_fld_s; +} pi_nack_cnt_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * The setting of this register affects both CPUs on this PI. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_nack_cmp_u { + bdrkreg_t pi_nack_cmp_regval; + struct { + bdrkreg_t nc_nack_cmp : 20; + bdrkreg_t nc_rsvd : 44; + } pi_nack_cmp_fld_s; +} pi_nack_cmp_u_t; + +#else + +typedef union pi_nack_cmp_u { + bdrkreg_t pi_nack_cmp_regval; + struct { + bdrkreg_t nc_rsvd : 44; + bdrkreg_t nc_nack_cmp : 20; + } pi_nack_cmp_fld_s; +} pi_nack_cmp_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register controls which errors are spooled. When a bit in * + * this register is set, the corresponding error is spooled. The * + * setting of this register affects both CPUs on this PI. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_spool_mask_u { + bdrkreg_t pi_spool_mask_regval; + struct { + bdrkreg_t sm_access_err : 1; + bdrkreg_t sm_uncached_err : 1; + bdrkreg_t sm_dir_err : 1; + bdrkreg_t sm_timeout_err : 1; + bdrkreg_t sm_poison_err : 1; + bdrkreg_t sm_nack_oflow_err : 1; + bdrkreg_t sm_rsvd : 58; + } pi_spool_mask_fld_s; +} pi_spool_mask_u_t; + +#else + +typedef union pi_spool_mask_u { + bdrkreg_t pi_spool_mask_regval; + struct { + bdrkreg_t sm_rsvd : 58; + bdrkreg_t sm_nack_oflow_err : 1; + bdrkreg_t sm_poison_err : 1; + bdrkreg_t sm_timeout_err : 1; + bdrkreg_t sm_dir_err : 1; + bdrkreg_t sm_uncached_err : 1; + bdrkreg_t sm_access_err : 1; + } pi_spool_mask_fld_s; +} pi_spool_mask_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. When the VALID bit is * + * zero, this register (along with SPURIOUS_HDR_1) will capture the * + * header of an incoming spurious message received from the XBar. A * + * spurious message is a message that does not match up with any of * + * the CRB entries. This is a read/write register, so it is cleared * + * by writing of all zeros. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_spurious_hdr_0_u { + bdrkreg_t pi_spurious_hdr_0_regval; + struct { + bdrkreg_t sh0_prev_valid_b : 1; + bdrkreg_t sh0_prev_valid_a : 1; + bdrkreg_t sh0_rsvd : 4; + bdrkreg_t sh0_supplemental : 11; + bdrkreg_t sh0_cmd : 8; + bdrkreg_t sh0_addr : 37; + bdrkreg_t sh0_tail : 1; + bdrkreg_t sh0_valid : 1; + } pi_spurious_hdr_0_fld_s; +} pi_spurious_hdr_0_u_t; + +#else + +typedef union pi_spurious_hdr_0_u { + bdrkreg_t pi_spurious_hdr_0_regval; + struct { + bdrkreg_t sh0_valid : 1; + bdrkreg_t sh0_tail : 1; + bdrkreg_t sh0_addr : 37; + bdrkreg_t sh0_cmd : 8; + bdrkreg_t sh0_supplemental : 11; + bdrkreg_t sh0_rsvd : 4; + bdrkreg_t sh0_prev_valid_a : 1; + bdrkreg_t sh0_prev_valid_b : 1; + } pi_spurious_hdr_0_fld_s; +} pi_spurious_hdr_0_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is not cleared at reset. When the VALID bit in * + * SPURIOUS_HDR_0 is zero, this register (along with SPURIOUS_HDR_0) * + * will capture the header of an incoming spurious message received * + * from the XBar. A spurious message is a message that does not match * + * up with any of the CRB entries. This is a read/write register, so * + * it is cleared by writing of all zeros. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_spurious_hdr_1_u { + bdrkreg_t pi_spurious_hdr_1_regval; + struct { + bdrkreg_t sh1_rsvd : 53; + bdrkreg_t sh1_source : 11; + } pi_spurious_hdr_1_fld_s; +} pi_spurious_hdr_1_u_t; + +#else + +typedef union pi_spurious_hdr_1_u { + bdrkreg_t pi_spurious_hdr_1_regval; + struct { + bdrkreg_t sh1_source : 11; + bdrkreg_t sh1_rsvd : 53; + } pi_spurious_hdr_1_fld_s; +} pi_spurious_hdr_1_u_t; + +#endif + + + + +/************************************************************************ + * * + * Description: This register controls the injection of errors in * + * outbound SysAD transfers. When a write sets a bit in this * + * register, the PI logic is "armed" to inject that error. At the * + * first transfer of the specified type, the error is injected and * + * the bit in this register is cleared. Writing to this register does * + * not cause a transaction to occur. A bit in this register will * + * remain set until a transaction of the specified type occurs as a * + * result of normal system activity. This register can be polled to * + * determine if an error has been injected or is still "armed". * + * This register does not control injection of data quality bad * + * indicator on a data cycle. This type of error can be created by * + * reading from a memory location that has an uncorrectable ECC * + * error. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_err_inject_u { + bdrkreg_t pi_err_inject_regval; + struct { + bdrkreg_t ei_cmd_syscmd_par_a : 1; + bdrkreg_t ei_data_syscmd_par_a : 1; + bdrkreg_t ei_cmd_sysad_corecc_a : 1; + bdrkreg_t ei_data_sysad_corecc_a : 1; + bdrkreg_t ei_cmd_sysad_uncecc_a : 1; + bdrkreg_t ei_data_sysad_uncecc_a : 1; + bdrkreg_t ei_sysresp_par_a : 1; + bdrkreg_t ei_reserved_1 : 25; + bdrkreg_t ei_cmd_syscmd_par_b : 1; + bdrkreg_t ei_data_syscmd_par_b : 1; + bdrkreg_t ei_cmd_sysad_corecc_b : 1; + bdrkreg_t ei_data_sysad_corecc_b : 1; + bdrkreg_t ei_cmd_sysad_uncecc_b : 1; + bdrkreg_t ei_data_sysad_uncecc_b : 1; + bdrkreg_t ei_sysresp_par_b : 1; + bdrkreg_t ei_reserved : 25; + } pi_err_inject_fld_s; +} pi_err_inject_u_t; + +#else + +typedef union pi_err_inject_u { + bdrkreg_t pi_err_inject_regval; + struct { + bdrkreg_t ei_reserved : 25; + bdrkreg_t ei_sysresp_par_b : 1; + bdrkreg_t ei_data_sysad_uncecc_b : 1; + bdrkreg_t ei_cmd_sysad_uncecc_b : 1; + bdrkreg_t ei_data_sysad_corecc_b : 1; + bdrkreg_t ei_cmd_sysad_corecc_b : 1; + bdrkreg_t ei_data_syscmd_par_b : 1; + bdrkreg_t ei_cmd_syscmd_par_b : 1; + bdrkreg_t ei_reserved_1 : 25; + bdrkreg_t ei_sysresp_par_a : 1; + bdrkreg_t ei_data_sysad_uncecc_a : 1; + bdrkreg_t ei_cmd_sysad_uncecc_a : 1; + bdrkreg_t ei_data_sysad_corecc_a : 1; + bdrkreg_t ei_cmd_sysad_corecc_a : 1; + bdrkreg_t ei_data_syscmd_par_a : 1; + bdrkreg_t ei_cmd_syscmd_par_a : 1; + } pi_err_inject_fld_s; +} pi_err_inject_u_t; + +#endif + + + + +/************************************************************************ + * * + * This Read/Write location determines at what point the TRex+ is * + * stopped from issuing requests, based on the number of entries in * + * the incoming reply FIFO. When the number of entries in the Reply * + * FIFO is greater than the value of this register, the PI will * + * deassert both SysWrRdy and SysRdRdy to both processors. The Reply * + * FIFO has a depth of 0x3F entries, so setting this register to 0x3F * + * effectively disables this feature, allowing requests to be issued * + * always. Setting this register to 0x00 effectively lowers the * + * TRex+'s priority below the reply FIFO, disabling TRex+ requests * + * any time there is an entry waiting in the incoming FIFO.This * + * register is in its own 64KB page so that it can be mapped to user * + * space. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_reply_level_u { + bdrkreg_t pi_reply_level_regval; + struct { + bdrkreg_t rl_reply_level : 6; + bdrkreg_t rl_rsvd : 58; + } pi_reply_level_fld_s; +} pi_reply_level_u_t; + +#else + +typedef union pi_reply_level_u { + bdrkreg_t pi_reply_level_regval; + struct { + bdrkreg_t rl_rsvd : 58; + bdrkreg_t rl_reply_level : 6; + } pi_reply_level_fld_s; +} pi_reply_level_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register is used to change the graphics credit counter * + * operation from "Doubleword" mode to "Transaction" mode. This * + * register is in its own 64KB page so that it can be mapped to user * + * space. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_gfx_credit_mode_u { + bdrkreg_t pi_gfx_credit_mode_regval; + struct { + bdrkreg_t gcm_trans_mode : 1; + bdrkreg_t gcm_rsvd : 63; + } pi_gfx_credit_mode_fld_s; +} pi_gfx_credit_mode_u_t; + +#else + +typedef union pi_gfx_credit_mode_u { + bdrkreg_t pi_gfx_credit_mode_regval; + struct { + bdrkreg_t gcm_rsvd : 63; + bdrkreg_t gcm_trans_mode : 1; + } pi_gfx_credit_mode_fld_s; +} pi_gfx_credit_mode_u_t; + +#endif + + + +/************************************************************************ + * * + * This location contains a 55-bit read/write counter that wraps to * + * zero when the maximum value is reached. This counter is * + * incremented at each rising edge of the global clock (GCLK). This * + * register is in its own 64KB page so that it can be mapped to user * + * space. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_rt_counter_u { + bdrkreg_t pi_rt_counter_regval; + struct { + bdrkreg_t rc_count : 55; + bdrkreg_t rc_rsvd : 9; + } pi_rt_counter_fld_s; +} pi_rt_counter_u_t; + +#else + +typedef union pi_rt_counter_u { + bdrkreg_t pi_rt_counter_regval; + struct { + bdrkreg_t rc_rsvd : 9; + bdrkreg_t rc_count : 55; + } pi_rt_counter_fld_s; +} pi_rt_counter_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register controls the performance counters for one CPU. * + * There are two counters for each CPU. Each counter can be * + * configured to count a variety of events. The performance counter * + * registers for each processor are in their own 64KB page so that * + * they can be mapped to user space. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_perf_cntl_a_u { + bdrkreg_t pi_perf_cntl_a_regval; + struct { + bdrkreg_t pca_cntr_0_select : 28; + bdrkreg_t pca_cntr_0_mode : 3; + bdrkreg_t pca_cntr_0_enable : 1; + bdrkreg_t pca_cntr_1_select : 28; + bdrkreg_t pca_cntr_1_mode : 3; + bdrkreg_t pca_cntr_1_enable : 1; + } pi_perf_cntl_a_fld_s; +} pi_perf_cntl_a_u_t; + +#else + +typedef union pi_perf_cntl_a_u { + bdrkreg_t pi_perf_cntl_a_regval; + struct { + bdrkreg_t pca_cntr_1_enable : 1; + bdrkreg_t pca_cntr_1_mode : 3; + bdrkreg_t pca_cntr_1_select : 28; + bdrkreg_t pca_cntr_0_enable : 1; + bdrkreg_t pca_cntr_0_mode : 3; + bdrkreg_t pca_cntr_0_select : 28; + } pi_perf_cntl_a_fld_s; +} pi_perf_cntl_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register accesses the performance counter 0 for each CPU. * + * Each performance counter is 40-bits wide. On overflow, It wraps to * + * zero, sets the overflow bit in this register, and sets the * + * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_perf_cntr0_a_u { + bdrkreg_t pi_perf_cntr0_a_regval; + struct { + bdrkreg_t pca_count_value : 40; + bdrkreg_t pca_overflow : 1; + bdrkreg_t pca_rsvd : 23; + } pi_perf_cntr0_a_fld_s; +} pi_perf_cntr0_a_u_t; + +#else + +typedef union pi_perf_cntr0_a_u { + bdrkreg_t pi_perf_cntr0_a_regval; + struct { + bdrkreg_t pca_rsvd : 23; + bdrkreg_t pca_overflow : 1; + bdrkreg_t pca_count_value : 40; + } pi_perf_cntr0_a_fld_s; +} pi_perf_cntr0_a_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register accesses the performance counter 1for each CPU. * + * Each performance counter is 40-bits wide. On overflow, It wraps to * + * zero, sets the overflow bit in this register, and sets the * + * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_perf_cntr1_a_u { + bdrkreg_t pi_perf_cntr1_a_regval; + struct { + bdrkreg_t pca_count_value : 40; + bdrkreg_t pca_overflow : 1; + bdrkreg_t pca_rsvd : 23; + } pi_perf_cntr1_a_fld_s; +} pi_perf_cntr1_a_u_t; + +#else + +typedef union pi_perf_cntr1_a_u { + bdrkreg_t pi_perf_cntr1_a_regval; + struct { + bdrkreg_t pca_rsvd : 23; + bdrkreg_t pca_overflow : 1; + bdrkreg_t pca_count_value : 40; + } pi_perf_cntr1_a_fld_s; +} pi_perf_cntr1_a_u_t; + +#endif + + + + + +/************************************************************************ + * * + * This register controls the performance counters for one CPU. * + * There are two counters for each CPU. Each counter can be * + * configured to count a variety of events. The performance counter * + * registers for each processor are in their own 64KB page so that * + * they can be mapped to user space. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_perf_cntl_b_u { + bdrkreg_t pi_perf_cntl_b_regval; + struct { + bdrkreg_t pcb_cntr_0_select : 28; + bdrkreg_t pcb_cntr_0_mode : 3; + bdrkreg_t pcb_cntr_0_enable : 1; + bdrkreg_t pcb_cntr_1_select : 28; + bdrkreg_t pcb_cntr_1_mode : 3; + bdrkreg_t pcb_cntr_1_enable : 1; + } pi_perf_cntl_b_fld_s; +} pi_perf_cntl_b_u_t; + +#else + +typedef union pi_perf_cntl_b_u { + bdrkreg_t pi_perf_cntl_b_regval; + struct { + bdrkreg_t pcb_cntr_1_enable : 1; + bdrkreg_t pcb_cntr_1_mode : 3; + bdrkreg_t pcb_cntr_1_select : 28; + bdrkreg_t pcb_cntr_0_enable : 1; + bdrkreg_t pcb_cntr_0_mode : 3; + bdrkreg_t pcb_cntr_0_select : 28; + } pi_perf_cntl_b_fld_s; +} pi_perf_cntl_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register accesses the performance counter 0 for each CPU. * + * Each performance counter is 40-bits wide. On overflow, It wraps to * + * zero, sets the overflow bit in this register, and sets the * + * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_perf_cntr0_b_u { + bdrkreg_t pi_perf_cntr0_b_regval; + struct { + bdrkreg_t pcb_count_value : 40; + bdrkreg_t pcb_overflow : 1; + bdrkreg_t pcb_rsvd : 23; + } pi_perf_cntr0_b_fld_s; +} pi_perf_cntr0_b_u_t; + +#else + +typedef union pi_perf_cntr0_b_u { + bdrkreg_t pi_perf_cntr0_b_regval; + struct { + bdrkreg_t pcb_rsvd : 23; + bdrkreg_t pcb_overflow : 1; + bdrkreg_t pcb_count_value : 40; + } pi_perf_cntr0_b_fld_s; +} pi_perf_cntr0_b_u_t; + +#endif + + + + +/************************************************************************ + * * + * This register accesses the performance counter 1for each CPU. * + * Each performance counter is 40-bits wide. On overflow, It wraps to * + * zero, sets the overflow bit in this register, and sets the * + * PERF_CNTR_OFLOW bit in the INT_PEND1 register. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union pi_perf_cntr1_b_u { + bdrkreg_t pi_perf_cntr1_b_regval; + struct { + bdrkreg_t pcb_count_value : 40; + bdrkreg_t pcb_overflow : 1; + bdrkreg_t pcb_rsvd : 23; + } pi_perf_cntr1_b_fld_s; +} pi_perf_cntr1_b_u_t; + +#else + +typedef union pi_perf_cntr1_b_u { + bdrkreg_t pi_perf_cntr1_b_regval; + struct { + bdrkreg_t pcb_rsvd : 23; + bdrkreg_t pcb_overflow : 1; + bdrkreg_t pcb_count_value : 40; + } pi_perf_cntr1_b_fld_s; +} pi_perf_cntr1_b_u_t; + +#endif + + + + + + +#endif /* _LANGUAGE_C */ + +/************************************************************************ + * * + * MAKE ALL ADDITIONS AFTER THIS LINE * + * * + ************************************************************************/ + + +#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A) +#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL + + +#endif /* _ASM_SN_SN1_HUBPI_H */ diff --git a/include/asm-ia64/sn/sn1/hubpi_next.h b/include/asm-ia64/sn/sn1/hubpi_next.h new file mode 100644 index 000000000..1e31d2722 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubpi_next.h @@ -0,0 +1,332 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBPI_NEXT_H +#define _ASM_SN_SN1_HUBPI_NEXT_H + + +/* define for remote PI_1 space. It is always half of a node_addressspace + * from PI_0. The normal REMOTE_HUB space for PI registers access + * the PI_0 space, unless they are qualified by PI_1. + */ +#define PI_0(x) (x) +#define PI_1(x) ((x) + 0x200000) +#define PIREG(x,sn) ((sn) ? PI_1(x) : PI_0(x)) + +#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */ +#define PI_STACK_SIZE_SHFT 12 /* 4k */ + +#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A) +#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A) +#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A) +/* these macros are correct, but fix their users to understand two PIs + and 4 CPUs (slices) per bedrock */ +#define PI_INT_MASK_OFFSET (PI_INT_MASK0_B - PI_INT_MASK0_A) +#define PI_INT_SET_OFFSET (PI_CC_PEND_CLR_B - PI_CC_PEND_CLR_A) +#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A) + +#define ERR_STACK_SIZE_BYTES(_sz) \ + ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0) + +#define PI_CRB_STS_P (1 << 9) /* "P" (partial word read/write) bit */ +#define PI_CRB_STS_V (1 << 8) /* "V" (valid) bit */ +#define PI_CRB_STS_R (1 << 7) /* "R" (response data sent to CPU) */ +#define PI_CRB_STS_A (1 << 6) /* "A" (data ack. received) bit */ +#define PI_CRB_STS_W (1 << 5) /* "W" (waiting for write compl.) */ +#define PI_CRB_STS_H (1 << 4) /* "H" (gathering invalidates) bit */ +#define PI_CRB_STS_I (1 << 3) /* "I" (targ. inbound invalidate) */ +#define PI_CRB_STS_T (1 << 2) /* "T" (targ. inbound intervention) */ +#define PI_CRB_STS_E (0x3) /* "E" (coherent read type) */ + +/* When the "P" bit is set in the sk_crb_sts field of an error stack + * entry, the "R," "A," "H," and "I" bits are actually bits 6..3 of + * the address. This macro extracts those address bits and shifts + * them to their proper positions, ready to be ORed in to the rest of + * the address (which is calculated as sk_addr << 7). + */ +#define PI_CRB_STS_ADDR_BITS(sts) \ + ((sts) & (PI_CRB_STS_I | PI_CRB_STS_H) | \ + ((sts) & (PI_CRB_STS_A | PI_CRB_STS_R)) >> 1) + +#ifdef _LANGUAGE_C +/* + * format of error stack and error status registers. + */ + +#ifdef LITTLE_ENDIAN + +struct err_stack_format { + uint64_t sk_err_type: 3, /* error type */ + sk_suppl : 3, /* lowest 3 bit of supplemental */ + sk_t5_req : 3, /* RRB T5 request number */ + sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ + sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ + sk_crb_sts : 10, /* status from RRB or WRB */ + sk_cmd : 8, /* message command */ + sk_addr : 33; /* address */ +}; + +#else + +struct err_stack_format { + uint64_t sk_addr : 33, /* address */ + sk_cmd : 8, /* message command */ + sk_crb_sts : 10, /* status from RRB or WRB */ + sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ + sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ + sk_t5_req : 3, /* RRB T5 request number */ + sk_suppl : 3, /* lowest 3 bit of supplemental */ + sk_err_type: 3; /* error type */ +}; + +#endif + +typedef union pi_err_stack { + uint64_t pi_stk_word; + struct err_stack_format pi_stk_fmt; +} pi_err_stack_t; + +/* Simplified version of pi_err_status0_a_u_t (PI_ERR_STATUS0_A) */ +#ifdef LITTLE_ENDIAN + +struct err_status0_format { + uint64_t s0_err_type : 3, /* Encoded error cause */ + s0_proc_req_num : 3, /* Request number for RRB only */ + s0_supplemental : 11, /* ncoming message sup field */ + s0_cmd : 8, /* Incoming message command */ + s0_addr : 37, /* Address */ + s0_over_run : 1, /* Subsequent errors spooled */ + s0_valid : 1; /* error is valid */ +}; + +#else + +struct err_status0_format { + uint64_t s0_valid : 1, /* error is valid */ + s0_over_run : 1, /* Subsequent errors spooled */ + s0_addr : 37, /* Address */ + s0_cmd : 8, /* Incoming message command */ + s0_supplemental : 11, /* ncoming message sup field */ + s0_proc_req_num : 3, /* Request number for RRB only */ + s0_err_type : 3; /* Encoded error cause */ +}; + +#endif + + +typedef union pi_err_stat0 { + uint64_t pi_stat0_word; + struct err_status0_format pi_stat0_fmt; +} pi_err_stat0_t; + +/* Simplified version of pi_err_status1_a_u_t (PI_ERR_STATUS1_A) */ + +#ifdef LITTLE_ENDIAN + +struct err_status1_format { + uint64_t s1_spl_cnt : 21, /* number spooled to memory */ + s1_to_cnt : 8, /* crb timeout counter */ + s1_inval_cnt:10, /* signed invalidate counter RRB */ + s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ + s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ + s1_crb_sts : 10, /* status from RRB or WRB */ + s1_src : 11; /* message source */ +}; + +#else + +struct err_status1_format { + uint64_t s1_src : 11, /* message source */ + s1_crb_sts : 10, /* status from RRB or WRB */ + s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ + s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ + s1_inval_cnt:10, /* signed invalidate counter RRB */ + s1_to_cnt : 8, /* crb timeout counter */ + s1_spl_cnt : 21; /* number spooled to memory */ +}; + +#endif + +typedef union pi_err_stat1 { + uint64_t pi_stat1_word; + struct err_status1_format pi_stat1_fmt; +} pi_err_stat1_t; +#endif + +/* Error stack types (sk_err_type) for reads: */ +#define PI_ERR_RD_AERR 0 /* Read Access Error */ +#define PI_ERR_RD_PRERR 1 /* Uncached Partitial Read */ +#define PI_ERR_RD_DERR 2 /* Directory Error */ +#define PI_ERR_RD_TERR 3 /* read timeout */ +#define PI_ERR_RD_PERR 4 /* Poison Access Violation */ +#define PI_ERR_RD_NACK 5 /* Excessive NACKs */ +#define PI_ERR_RD_RDE 6 /* Response Data Error */ +#define PI_ERR_RD_PLERR 7 /* Packet Length Error */ +/* Error stack types (sk_err_type) for writes: */ +#define PI_ERR_WR_WERR 0 /* Write Access Error */ +#define PI_ERR_WR_PWERR 1 /* Uncached Write Error */ +#define PI_ERR_WR_TERR 3 /* write timeout */ +#define PI_ERR_WR_RDE 6 /* Response Data Error */ +#define PI_ERR_WR_PLERR 7 /* Packet Length Error */ + + +/* For backwards compatibility */ +#define PI_RT_COUNT PI_RT_COUNTER /* Real Time Counter */ +#define PI_RT_EN_A PI_RT_INT_EN_A /* RT int for CPU A enable */ +#define PI_RT_EN_B PI_RT_INT_EN_B /* RT int for CPU B enable */ +#define PI_PROF_EN_A PI_PROF_INT_EN_A /* PROF int for CPU A enable */ +#define PI_PROF_EN_B PI_PROF_INT_EN_B /* PROF int for CPU B enable */ +#define PI_RT_PEND_A PI_RT_INT_PEND_A /* RT interrupt pending */ +#define PI_RT_PEND_B PI_RT_INT_PEND_B /* RT interrupt pending */ +#define PI_PROF_PEND_A PI_PROF_INT_PEND_A /* Profiling interrupt pending */ +#define PI_PROF_PEND_B PI_PROF_INT_PEND_B /* Profiling interrupt pending */ + + +/* Bits in PI_SYSAD_ERRCHK_EN */ +#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */ +#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */ +#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */ +#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */ +#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */ +#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */ +#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */ + +/* CALIAS values */ +#define PI_CALIAS_SIZE_0 0 +#define PI_CALIAS_SIZE_4K 1 +#define PI_CALIAS_SIZE_8K 2 +#define PI_CALIAS_SIZE_16K 3 +#define PI_CALIAS_SIZE_32K 4 +#define PI_CALIAS_SIZE_64K 5 +#define PI_CALIAS_SIZE_128K 6 +#define PI_CALIAS_SIZE_256K 7 +#define PI_CALIAS_SIZE_512K 8 +#define PI_CALIAS_SIZE_1M 9 +#define PI_CALIAS_SIZE_2M 10 +#define PI_CALIAS_SIZE_4M 11 +#define PI_CALIAS_SIZE_8M 12 +#define PI_CALIAS_SIZE_16M 13 +#define PI_CALIAS_SIZE_32M 14 +#define PI_CALIAS_SIZE_64M 15 + +/* Fields in PI_ERR_STATUS0_[AB] */ +#define PI_ERR_ST0_VALID_MASK 0x8000000000000000 +#define PI_ERR_ST0_VALID_SHFT 63 + +/* Fields in PI_SPURIOUS_HDR_0 */ +#define PI_SPURIOUS_HDR_VALID_MASK 0x8000000000000000 +#define PI_SPURIOUS_HDR_VALID_SHFT 63 + +/* Fields in PI_NACK_CNT_A/B */ +#define PI_NACK_CNT_EN_SHFT 20 +#define PI_NACK_CNT_EN_MASK 0x100000 +#define PI_NACK_CNT_MASK 0x0fffff +#define PI_NACK_CNT_MAX 0x0fffff + +/* Bits in PI_ERR_INT_PEND */ +#define PI_ERR_SPOOL_CMP_B 0x000000001 /* Spool end hit high water */ +#define PI_ERR_SPOOL_CMP_A 0x000000002 +#define PI_ERR_SPUR_MSG_B 0x000000004 /* Spurious message intr. */ +#define PI_ERR_SPUR_MSG_A 0x000000008 +#define PI_ERR_WRB_TERR_B 0x000000010 /* WRB TERR */ +#define PI_ERR_WRB_TERR_A 0x000000020 +#define PI_ERR_WRB_WERR_B 0x000000040 /* WRB WERR */ +#define PI_ERR_WRB_WERR_A 0x000000080 +#define PI_ERR_SYSSTATE_B 0x000000100 /* SysState parity error */ +#define PI_ERR_SYSSTATE_A 0x000000200 +#define PI_ERR_SYSAD_DATA_B 0x000000400 /* SysAD data parity error */ +#define PI_ERR_SYSAD_DATA_A 0x000000800 +#define PI_ERR_SYSAD_ADDR_B 0x000001000 /* SysAD addr parity error */ +#define PI_ERR_SYSAD_ADDR_A 0x000002000 +#define PI_ERR_SYSCMD_DATA_B 0x000004000 /* SysCmd data parity error */ +#define PI_ERR_SYSCMD_DATA_A 0x000008000 +#define PI_ERR_SYSCMD_ADDR_B 0x000010000 /* SysCmd addr parity error */ +#define PI_ERR_SYSCMD_ADDR_A 0x000020000 +#define PI_ERR_BAD_SPOOL_B 0x000040000 /* Error spooling to memory */ +#define PI_ERR_BAD_SPOOL_A 0x000080000 +#define PI_ERR_UNCAC_UNCORR_B 0x000100000 /* Uncached uncorrectable */ +#define PI_ERR_UNCAC_UNCORR_A 0x000200000 +#define PI_ERR_SYSSTATE_TAG_B 0x000400000 /* SysState tag parity error */ +#define PI_ERR_SYSSTATE_TAG_A 0x000800000 +#define PI_ERR_MD_UNCORR 0x001000000 /* Must be cleared in MD */ +#define PI_ERR_SYSAD_BAD_DATA_B 0x002000000 /* SysAD Data quality bad */ +#define PI_ERR_SYSAD_BAD_DATA_A 0x004000000 +#define PI_ERR_UE_CACHED_B 0x008000000 /* UE during cached load */ +#define PI_ERR_UE_CACHED_A 0x010000000 +#define PI_ERR_PKT_LEN_ERR_B 0x020000000 /* Xbar data too long/short */ +#define PI_ERR_PKT_LEN_ERR_A 0x040000000 +#define PI_ERR_IRB_ERR_B 0x080000000 /* Protocol error */ +#define PI_ERR_IRB_ERR_A 0x100000000 +#define PI_ERR_IRB_TIMEOUT_B 0x200000000 /* IRB_B got a timeout */ +#define PI_ERR_IRB_TIMEOUT_A 0x400000000 + +#define PI_ERR_CLEAR_ALL_A 0x554aaaaaa +#define PI_ERR_CLEAR_ALL_B 0x2aa555555 + + +/* + * The following three macros define all possible error int pends. + */ + +#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSAD_BAD_DATA_A | \ + PI_ERR_SYSSTATE_TAG_A | \ + PI_ERR_BAD_SPOOL_A | \ + PI_ERR_SYSCMD_ADDR_A | \ + PI_ERR_SYSCMD_DATA_A | \ + PI_ERR_SYSAD_ADDR_A | \ + PI_ERR_SYSAD_DATA_A | \ + PI_ERR_SYSSTATE_A) + +#define PI_MISC_ERR_CPU_A (PI_ERR_IRB_TIMEOUT_A | \ + PI_ERR_IRB_ERR_A | \ + PI_ERR_PKT_LEN_ERR_A | \ + PI_ERR_UE_CACHED_A | \ + PI_ERR_UNCAC_UNCORR_A | \ + PI_ERR_WRB_WERR_A | \ + PI_ERR_WRB_TERR_A | \ + PI_ERR_SPUR_MSG_A | \ + PI_ERR_SPOOL_CMP_A) + +#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSAD_BAD_DATA_B | \ + PI_ERR_SYSSTATE_TAG_B | \ + PI_ERR_BAD_SPOOL_B | \ + PI_ERR_SYSCMD_ADDR_B | \ + PI_ERR_SYSCMD_DATA_B | \ + PI_ERR_SYSAD_ADDR_B | \ + PI_ERR_SYSAD_DATA_B | \ + PI_ERR_SYSSTATE_B) + +#define PI_MISC_ERR_CPU_B (PI_ERR_IRB_TIMEOUT_B | \ + PI_ERR_IRB_ERR_B | \ + PI_ERR_PKT_LEN_ERR_B | \ + PI_ERR_UE_CACHED_B | \ + PI_ERR_UNCAC_UNCORR_B | \ + PI_ERR_WRB_WERR_B | \ + PI_ERR_WRB_TERR_B | \ + PI_ERR_SPUR_MSG_B | \ + PI_ERR_SPOOL_CMP_B) + +#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR) + +/* Values for PI_MAX_CRB_TIMEOUT and PI_CRB_SFACTOR */ +#define PMCT_MAX 0xff +#define PCS_MAX 0xffffff + +/* pi_err_status0_a_u_t address shift */ +#define ERR_STAT0_ADDR_SHFT 3 + +/* PI error read/write bit (RRB == 0, WRB == 1) */ +/* pi_err_status1_a_u_t.pi_err_status1_a_fld_s.esa_wrb */ +#define PI_ERR_RRB 0 +#define PI_ERR_WRB 1 + +/* Error stack address shift, for use with pi_stk_fmt.sk_addr */ +#define ERR_STK_ADDR_SHFT 3 + +#endif /* _ASM_SN_SN1_HUBPI_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubxb.h b/include/asm-ia64/sn/sn1/hubxb.h new file mode 100644 index 000000000..21044fdfd --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubxb.h @@ -0,0 +1,1289 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBXB_H +#define _ASM_SN_SN1_HUBXB_H + +/************************************************************************ + * * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! * + * * + * This file is created by an automated script. Any (minimal) changes * + * made manually to this file should be made with care. * + * * + * MAKE ALL ADDITIONS TO THE END OF THIS FILE * + * * + ************************************************************************/ + + +#define XB_PARMS 0x00700000 /* + * Controls + * crossbar-wide + * parameters. + */ + + + +#define XB_SLOW_GNT 0x00700008 /* + * Controls wavefront + * arbiter grant + * frequency, used to + * slow XB grants + */ + + + +#define XB_SPEW_CONTROL 0x00700010 /* + * Controls spew + * settings (debug + * only). + */ + + + +#define XB_IOQ_ARB_TRIGGER 0x00700018 /* + * Controls IOQ + * trigger level + */ + + + +#define XB_FIRST_ERROR 0x00700090 /* + * Records the first + * crossbar error + * seen. + */ + + + +#define XB_POQ0_ERROR 0x00700020 /* + * POQ0 error + * register. + */ + + + +#define XB_PIQ0_ERROR 0x00700028 /* + * PIQ0 error + * register. + */ + + + +#define XB_POQ1_ERROR 0x00700030 /* + * POQ1 error + * register. + */ + + + +#define XB_PIQ1_ERROR 0x00700038 /* + * PIQ1 error + * register. + */ + + + +#define XB_MP0_ERROR 0x00700040 /* + * MOQ for PI0 error + * register. + */ + + + +#define XB_MP1_ERROR 0x00700048 /* + * MOQ for PI1 error + * register. + */ + + + +#define XB_MMQ_ERROR 0x00700050 /* + * MOQ for misc. (LB, + * NI, II) error + * register. + */ + + + +#define XB_MIQ_ERROR 0x00700058 /* + * MIQ error register, + * addtional MIQ + * errors are logged + * in MD "Input + * Error + * Registers". + */ + + + +#define XB_NOQ_ERROR 0x00700060 /* NOQ error register. */ + + + +#define XB_NIQ_ERROR 0x00700068 /* NIQ error register. */ + + + +#define XB_IOQ_ERROR 0x00700070 /* IOQ error register. */ + + + +#define XB_IIQ_ERROR 0x00700078 /* IIQ error register. */ + + + +#define XB_LOQ_ERROR 0x00700080 /* LOQ error register. */ + + + +#define XB_LIQ_ERROR 0x00700088 /* LIQ error register. */ + + + +#define XB_DEBUG_DATA_CTL 0x00700098 /* + * Debug Datapath + * Select + */ + + + +#define XB_DEBUG_ARB_CTL 0x007000A0 /* + * XB master debug + * control + */ + + + +#define XB_POQ0_ERROR_CLEAR 0x00700120 /* + * Clears + * XB_POQ0_ERROR + * register. + */ + + + +#define XB_PIQ0_ERROR_CLEAR 0x00700128 /* + * Clears + * XB_PIQ0_ERROR + * register. + */ + + + +#define XB_POQ1_ERROR_CLEAR 0x00700130 /* + * Clears + * XB_POQ1_ERROR + * register. + */ + + + +#define XB_PIQ1_ERROR_CLEAR 0x00700138 /* + * Clears + * XB_PIQ1_ERROR + * register. + */ + + + +#define XB_MP0_ERROR_CLEAR 0x00700140 /* + * Clears XB_MP0_ERROR + * register. + */ + + + +#define XB_MP1_ERROR_CLEAR 0x00700148 /* + * Clears XB_MP1_ERROR + * register. + */ + + + +#define XB_MMQ_ERROR_CLEAR 0x00700150 /* + * Clears XB_MMQ_ERROR + * register. + */ + + + +#define XB_XM_MIQ_ERROR_CLEAR 0x00700158 /* + * Clears XB_MIQ_ERROR + * register + */ + + + +#define XB_NOQ_ERROR_CLEAR 0x00700160 /* + * Clears XB_NOQ_ERROR + * register. + */ + + + +#define XB_NIQ_ERROR_CLEAR 0x00700168 /* + * Clears XB_NIQ_ERROR + * register. + */ + + + +#define XB_IOQ_ERROR_CLEAR 0x00700170 /* + * Clears XB_IOQ + * _ERROR register. + */ + + + +#define XB_IIQ_ERROR_CLEAR 0x00700178 /* + * Clears XB_IIQ + * _ERROR register. + */ + + + +#define XB_LOQ_ERROR_CLEAR 0x00700180 /* + * Clears XB_LOQ_ERROR + * register. + */ + + + +#define XB_LIQ_ERROR_CLEAR 0x00700188 /* + * Clears XB_LIQ_ERROR + * register. + */ + + + +#define XB_FIRST_ERROR_CLEAR 0x00700190 /* + * Clears + * XB_FIRST_ERROR + * register + */ + + + + + +#ifdef _LANGUAGE_C + +/************************************************************************ + * * + * Access to parameters which control various aspects of the * + * crossbar's operation. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_parms_u { + bdrkreg_t xb_parms_regval; + struct { + bdrkreg_t p_byp_en : 1; + bdrkreg_t p_rsrvd_1 : 3; + bdrkreg_t p_age_wrap : 8; + bdrkreg_t p_deadlock_to_wrap : 20; + bdrkreg_t p_tail_to_wrap : 20; + bdrkreg_t p_rsrvd : 12; + } xb_parms_fld_s; +} xb_parms_u_t; + +#else + +typedef union xb_parms_u { + bdrkreg_t xb_parms_regval; + struct { + bdrkreg_t p_rsrvd : 12; + bdrkreg_t p_tail_to_wrap : 20; + bdrkreg_t p_deadlock_to_wrap : 20; + bdrkreg_t p_age_wrap : 8; + bdrkreg_t p_rsrvd_1 : 3; + bdrkreg_t p_byp_en : 1; + } xb_parms_fld_s; +} xb_parms_u_t; + +#endif + + + + +/************************************************************************ + * * + * Sets the period of wavefront grants given to each unit. The * + * register's value corresponds to the number of cycles between each * + * wavefront grant opportunity given to the requesting unit. If set * + * to 0xF, no grants are given to this unit. If set to 0xE, the unit * + * is granted at the slowest rate (sometimes called "molasses mode"). * + * This feature can be used to apply backpressure to a unit's output * + * queue(s). The setting does not affect bypass grants. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_slow_gnt_u { + bdrkreg_t xb_slow_gnt_regval; + struct { + bdrkreg_t sg_lb_slow_gnt : 4; + bdrkreg_t sg_ii_slow_gnt : 4; + bdrkreg_t sg_ni_slow_gnt : 4; + bdrkreg_t sg_mmq_slow_gnt : 4; + bdrkreg_t sg_mp1_slow_gnt : 4; + bdrkreg_t sg_mp0_slow_gnt : 4; + bdrkreg_t sg_pi1_slow_gnt : 4; + bdrkreg_t sg_pi0_slow_gnt : 4; + bdrkreg_t sg_rsrvd : 32; + } xb_slow_gnt_fld_s; +} xb_slow_gnt_u_t; + +#else + +typedef union xb_slow_gnt_u { + bdrkreg_t xb_slow_gnt_regval; + struct { + bdrkreg_t sg_rsrvd : 32; + bdrkreg_t sg_pi0_slow_gnt : 4; + bdrkreg_t sg_pi1_slow_gnt : 4; + bdrkreg_t sg_mp0_slow_gnt : 4; + bdrkreg_t sg_mp1_slow_gnt : 4; + bdrkreg_t sg_mmq_slow_gnt : 4; + bdrkreg_t sg_ni_slow_gnt : 4; + bdrkreg_t sg_ii_slow_gnt : 4; + bdrkreg_t sg_lb_slow_gnt : 4; + } xb_slow_gnt_fld_s; +} xb_slow_gnt_u_t; + +#endif + + + + +/************************************************************************ + * * + * Enables snooping of internal crossbar traffic by spewing all * + * traffic across a selected crossbar point to the PI1 port. Only one * + * bit should be set at any one time, and any bit set will preclude * + * using the P1 for anything but a debug connection. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_spew_control_u { + bdrkreg_t xb_spew_control_regval; + struct { + bdrkreg_t sc_snoop_liq : 1; + bdrkreg_t sc_snoop_iiq : 1; + bdrkreg_t sc_snoop_niq : 1; + bdrkreg_t sc_snoop_miq : 1; + bdrkreg_t sc_snoop_piq0 : 1; + bdrkreg_t sc_snoop_loq : 1; + bdrkreg_t sc_snoop_ioq : 1; + bdrkreg_t sc_snoop_noq : 1; + bdrkreg_t sc_snoop_mmq : 1; + bdrkreg_t sc_snoop_mp0 : 1; + bdrkreg_t sc_snoop_poq0 : 1; + bdrkreg_t sc_rsrvd : 53; + } xb_spew_control_fld_s; +} xb_spew_control_u_t; + +#else + +typedef union xb_spew_control_u { + bdrkreg_t xb_spew_control_regval; + struct { + bdrkreg_t sc_rsrvd : 53; + bdrkreg_t sc_snoop_poq0 : 1; + bdrkreg_t sc_snoop_mp0 : 1; + bdrkreg_t sc_snoop_mmq : 1; + bdrkreg_t sc_snoop_noq : 1; + bdrkreg_t sc_snoop_ioq : 1; + bdrkreg_t sc_snoop_loq : 1; + bdrkreg_t sc_snoop_piq0 : 1; + bdrkreg_t sc_snoop_miq : 1; + bdrkreg_t sc_snoop_niq : 1; + bdrkreg_t sc_snoop_iiq : 1; + bdrkreg_t sc_snoop_liq : 1; + } xb_spew_control_fld_s; +} xb_spew_control_u_t; + +#endif + + + + +/************************************************************************ + * * + * Number of clocks the IOQ will wait before beginning XB * + * arbitration. This is set so that the slower IOQ data rate can * + * catch up up with the XB data rate in the IOQ buffer. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_ioq_arb_trigger_u { + bdrkreg_t xb_ioq_arb_trigger_regval; + struct { + bdrkreg_t iat_ioq_arb_trigger : 4; + bdrkreg_t iat_rsrvd : 60; + } xb_ioq_arb_trigger_fld_s; +} xb_ioq_arb_trigger_u_t; + +#else + +typedef union xb_ioq_arb_trigger_u { + bdrkreg_t xb_ioq_arb_trigger_regval; + struct { + bdrkreg_t iat_rsrvd : 60; + bdrkreg_t iat_ioq_arb_trigger : 4; + } xb_ioq_arb_trigger_fld_s; +} xb_ioq_arb_trigger_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by POQ0.Can be written to test software, will * + * cause an interrupt. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_poq0_error_u { + bdrkreg_t xb_poq0_error_regval; + struct { + bdrkreg_t pe_invalid_xsel : 2; + bdrkreg_t pe_rsrvd_3 : 2; + bdrkreg_t pe_overflow : 2; + bdrkreg_t pe_rsrvd_2 : 2; + bdrkreg_t pe_underflow : 2; + bdrkreg_t pe_rsrvd_1 : 2; + bdrkreg_t pe_tail_timeout : 2; + bdrkreg_t pe_unused : 6; + bdrkreg_t pe_rsrvd : 44; + } xb_poq0_error_fld_s; +} xb_poq0_error_u_t; + +#else + +typedef union xb_poq0_error_u { + bdrkreg_t xb_poq0_error_regval; + struct { + bdrkreg_t pe_rsrvd : 44; + bdrkreg_t pe_unused : 6; + bdrkreg_t pe_tail_timeout : 2; + bdrkreg_t pe_rsrvd_1 : 2; + bdrkreg_t pe_underflow : 2; + bdrkreg_t pe_rsrvd_2 : 2; + bdrkreg_t pe_overflow : 2; + bdrkreg_t pe_rsrvd_3 : 2; + bdrkreg_t pe_invalid_xsel : 2; + } xb_poq0_error_fld_s; +} xb_poq0_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by PIQ0. Note that the PIQ/PI interface * + * precludes PIQ underflow. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_piq0_error_u { + bdrkreg_t xb_piq0_error_regval; + struct { + bdrkreg_t pe_overflow : 2; + bdrkreg_t pe_rsrvd_1 : 2; + bdrkreg_t pe_deadlock_timeout : 2; + bdrkreg_t pe_rsrvd : 58; + } xb_piq0_error_fld_s; +} xb_piq0_error_u_t; + +#else + +typedef union xb_piq0_error_u { + bdrkreg_t xb_piq0_error_regval; + struct { + bdrkreg_t pe_rsrvd : 58; + bdrkreg_t pe_deadlock_timeout : 2; + bdrkreg_t pe_rsrvd_1 : 2; + bdrkreg_t pe_overflow : 2; + } xb_piq0_error_fld_s; +} xb_piq0_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by MP0 queue (the MOQ for processor 0). Since * + * the xselect is decoded on the MD/MOQ interface, no invalid xselect * + * errors are possible. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_mp0_error_u { + bdrkreg_t xb_mp0_error_regval; + struct { + bdrkreg_t me_rsrvd_3 : 4; + bdrkreg_t me_overflow : 2; + bdrkreg_t me_rsrvd_2 : 2; + bdrkreg_t me_underflow : 2; + bdrkreg_t me_rsrvd_1 : 2; + bdrkreg_t me_tail_timeout : 2; + bdrkreg_t me_rsrvd : 50; + } xb_mp0_error_fld_s; +} xb_mp0_error_u_t; + +#else + +typedef union xb_mp0_error_u { + bdrkreg_t xb_mp0_error_regval; + struct { + bdrkreg_t me_rsrvd : 50; + bdrkreg_t me_tail_timeout : 2; + bdrkreg_t me_rsrvd_1 : 2; + bdrkreg_t me_underflow : 2; + bdrkreg_t me_rsrvd_2 : 2; + bdrkreg_t me_overflow : 2; + bdrkreg_t me_rsrvd_3 : 4; + } xb_mp0_error_fld_s; +} xb_mp0_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by MIQ. * + * * + ************************************************************************/ + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_miq_error_u { + bdrkreg_t xb_miq_error_regval; + struct { + bdrkreg_t me_rsrvd_1 : 4; + bdrkreg_t me_deadlock_timeout : 4; + bdrkreg_t me_rsrvd : 56; + } xb_miq_error_fld_s; +} xb_miq_error_u_t; + +#else + +typedef union xb_miq_error_u { + bdrkreg_t xb_miq_error_regval; + struct { + bdrkreg_t me_rsrvd : 56; + bdrkreg_t me_deadlock_timeout : 4; + bdrkreg_t me_rsrvd_1 : 4; + } xb_miq_error_fld_s; +} xb_miq_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by NOQ. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_noq_error_u { + bdrkreg_t xb_noq_error_regval; + struct { + bdrkreg_t ne_rsvd : 4; + bdrkreg_t ne_overflow : 4; + bdrkreg_t ne_underflow : 4; + bdrkreg_t ne_tail_timeout : 4; + bdrkreg_t ne_rsrvd : 48; + } xb_noq_error_fld_s; +} xb_noq_error_u_t; + +#else + +typedef union xb_noq_error_u { + bdrkreg_t xb_noq_error_regval; + struct { + bdrkreg_t ne_rsrvd : 48; + bdrkreg_t ne_tail_timeout : 4; + bdrkreg_t ne_underflow : 4; + bdrkreg_t ne_overflow : 4; + bdrkreg_t ne_rsvd : 4; + } xb_noq_error_fld_s; +} xb_noq_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by LOQ. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_loq_error_u { + bdrkreg_t xb_loq_error_regval; + struct { + bdrkreg_t le_invalid_xsel : 2; + bdrkreg_t le_rsrvd_1 : 6; + bdrkreg_t le_underflow : 2; + bdrkreg_t le_rsvd : 2; + bdrkreg_t le_tail_timeout : 2; + bdrkreg_t le_rsrvd : 50; + } xb_loq_error_fld_s; +} xb_loq_error_u_t; + +#else + +typedef union xb_loq_error_u { + bdrkreg_t xb_loq_error_regval; + struct { + bdrkreg_t le_rsrvd : 50; + bdrkreg_t le_tail_timeout : 2; + bdrkreg_t le_rsvd : 2; + bdrkreg_t le_underflow : 2; + bdrkreg_t le_rsrvd_1 : 6; + bdrkreg_t le_invalid_xsel : 2; + } xb_loq_error_fld_s; +} xb_loq_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by LIQ. Note that the LIQ only records errors * + * for the request channel. The reply channel can never deadlock or * + * overflow because it does not have hardware flow control. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_liq_error_u { + bdrkreg_t xb_liq_error_regval; + struct { + bdrkreg_t le_overflow : 1; + bdrkreg_t le_rsrvd_1 : 3; + bdrkreg_t le_deadlock_timeout : 1; + bdrkreg_t le_rsrvd : 59; + } xb_liq_error_fld_s; +} xb_liq_error_u_t; + +#else + +typedef union xb_liq_error_u { + bdrkreg_t xb_liq_error_regval; + struct { + bdrkreg_t le_rsrvd : 59; + bdrkreg_t le_deadlock_timeout : 1; + bdrkreg_t le_rsrvd_1 : 3; + bdrkreg_t le_overflow : 1; + } xb_liq_error_fld_s; +} xb_liq_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * First error is latched whenever the Valid bit is clear and an * + * error occurs. Any valid bit on in this register causes an * + * interrupt to PI0 and PI1. This interrupt bit will persist until * + * the specific error register to capture the error is cleared, then * + * the FIRST_ERROR register is cleared (in that oder.) The * + * FIRST_ERROR register is not writable, but will be set when any of * + * the corresponding error registers are written by software. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_first_error_u { + bdrkreg_t xb_first_error_regval; + struct { + bdrkreg_t fe_type : 4; + bdrkreg_t fe_channel : 4; + bdrkreg_t fe_source : 4; + bdrkreg_t fe_valid : 1; + bdrkreg_t fe_rsrvd : 51; + } xb_first_error_fld_s; +} xb_first_error_u_t; + +#else + +typedef union xb_first_error_u { + bdrkreg_t xb_first_error_regval; + struct { + bdrkreg_t fe_rsrvd : 51; + bdrkreg_t fe_valid : 1; + bdrkreg_t fe_source : 4; + bdrkreg_t fe_channel : 4; + bdrkreg_t fe_type : 4; + } xb_first_error_fld_s; +} xb_first_error_u_t; + +#endif + + + + +/************************************************************************ + * * + * Controls DEBUG_DATA mux setting. Allows user to watch the output * + * of any OQ or input of any IQ on the DEBUG port. Note that bits * + * 13:0 are one-hot. If more than one bit is set in [13:0], the debug * + * output is undefined. Details on the debug output lines can be * + * found in the XB chapter of the Bedrock Interface Specification. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_debug_data_ctl_u { + bdrkreg_t xb_debug_data_ctl_regval; + struct { + bdrkreg_t ddc_observe_liq_traffic : 1; + bdrkreg_t ddc_observe_iiq_traffic : 1; + bdrkreg_t ddc_observe_niq_traffic : 1; + bdrkreg_t ddc_observe_miq_traffic : 1; + bdrkreg_t ddc_observe_piq1_traffic : 1; + bdrkreg_t ddc_observe_piq0_traffic : 1; + bdrkreg_t ddc_observe_loq_traffic : 1; + bdrkreg_t ddc_observe_ioq_traffic : 1; + bdrkreg_t ddc_observe_noq_traffic : 1; + bdrkreg_t ddc_observe_mp1_traffic : 1; + bdrkreg_t ddc_observe_mp0_traffic : 1; + bdrkreg_t ddc_observe_mmq_traffic : 1; + bdrkreg_t ddc_observe_poq1_traffic : 1; + bdrkreg_t ddc_observe_poq0_traffic : 1; + bdrkreg_t ddc_observe_source_field : 1; + bdrkreg_t ddc_observe_lodata : 1; + bdrkreg_t ddc_rsrvd : 48; + } xb_debug_data_ctl_fld_s; +} xb_debug_data_ctl_u_t; + +#else + +typedef union xb_debug_data_ctl_u { + bdrkreg_t xb_debug_data_ctl_regval; + struct { + bdrkreg_t ddc_rsrvd : 48; + bdrkreg_t ddc_observe_lodata : 1; + bdrkreg_t ddc_observe_source_field : 1; + bdrkreg_t ddc_observe_poq0_traffic : 1; + bdrkreg_t ddc_observe_poq1_traffic : 1; + bdrkreg_t ddc_observe_mmq_traffic : 1; + bdrkreg_t ddc_observe_mp0_traffic : 1; + bdrkreg_t ddc_observe_mp1_traffic : 1; + bdrkreg_t ddc_observe_noq_traffic : 1; + bdrkreg_t ddc_observe_ioq_traffic : 1; + bdrkreg_t ddc_observe_loq_traffic : 1; + bdrkreg_t ddc_observe_piq0_traffic : 1; + bdrkreg_t ddc_observe_piq1_traffic : 1; + bdrkreg_t ddc_observe_miq_traffic : 1; + bdrkreg_t ddc_observe_niq_traffic : 1; + bdrkreg_t ddc_observe_iiq_traffic : 1; + bdrkreg_t ddc_observe_liq_traffic : 1; + } xb_debug_data_ctl_fld_s; +} xb_debug_data_ctl_u_t; + +#endif + + + + +/************************************************************************ + * * + * Controls debug mux setting for XB Input/Output Queues and * + * Arbiter. Can select one of the following values. Details on the * + * debug output lines can be found in the XB chapter of the Bedrock * + * Interface Specification. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_debug_arb_ctl_u { + bdrkreg_t xb_debug_arb_ctl_regval; + struct { + bdrkreg_t dac_xb_debug_select : 3; + bdrkreg_t dac_rsrvd : 61; + } xb_debug_arb_ctl_fld_s; +} xb_debug_arb_ctl_u_t; + +#else + +typedef union xb_debug_arb_ctl_u { + bdrkreg_t xb_debug_arb_ctl_regval; + struct { + bdrkreg_t dac_rsrvd : 61; + bdrkreg_t dac_xb_debug_select : 3; + } xb_debug_arb_ctl_fld_s; +} xb_debug_arb_ctl_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by POQ0.Can be written to test software, will * + * cause an interrupt. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_poq0_error_clear_u { + bdrkreg_t xb_poq0_error_clear_regval; + struct { + bdrkreg_t pec_invalid_xsel : 2; + bdrkreg_t pec_rsrvd_3 : 2; + bdrkreg_t pec_overflow : 2; + bdrkreg_t pec_rsrvd_2 : 2; + bdrkreg_t pec_underflow : 2; + bdrkreg_t pec_rsrvd_1 : 2; + bdrkreg_t pec_tail_timeout : 2; + bdrkreg_t pec_unused : 6; + bdrkreg_t pec_rsrvd : 44; + } xb_poq0_error_clear_fld_s; +} xb_poq0_error_clear_u_t; + +#else + +typedef union xb_poq0_error_clear_u { + bdrkreg_t xb_poq0_error_clear_regval; + struct { + bdrkreg_t pec_rsrvd : 44; + bdrkreg_t pec_unused : 6; + bdrkreg_t pec_tail_timeout : 2; + bdrkreg_t pec_rsrvd_1 : 2; + bdrkreg_t pec_underflow : 2; + bdrkreg_t pec_rsrvd_2 : 2; + bdrkreg_t pec_overflow : 2; + bdrkreg_t pec_rsrvd_3 : 2; + bdrkreg_t pec_invalid_xsel : 2; + } xb_poq0_error_clear_fld_s; +} xb_poq0_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by PIQ0. Note that the PIQ/PI interface * + * precludes PIQ underflow. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_piq0_error_clear_u { + bdrkreg_t xb_piq0_error_clear_regval; + struct { + bdrkreg_t pec_overflow : 2; + bdrkreg_t pec_rsrvd_1 : 2; + bdrkreg_t pec_deadlock_timeout : 2; + bdrkreg_t pec_rsrvd : 58; + } xb_piq0_error_clear_fld_s; +} xb_piq0_error_clear_u_t; + +#else + +typedef union xb_piq0_error_clear_u { + bdrkreg_t xb_piq0_error_clear_regval; + struct { + bdrkreg_t pec_rsrvd : 58; + bdrkreg_t pec_deadlock_timeout : 2; + bdrkreg_t pec_rsrvd_1 : 2; + bdrkreg_t pec_overflow : 2; + } xb_piq0_error_clear_fld_s; +} xb_piq0_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by MP0 queue (the MOQ for processor 0). Since * + * the xselect is decoded on the MD/MOQ interface, no invalid xselect * + * errors are possible. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_mp0_error_clear_u { + bdrkreg_t xb_mp0_error_clear_regval; + struct { + bdrkreg_t mec_rsrvd_3 : 4; + bdrkreg_t mec_overflow : 2; + bdrkreg_t mec_rsrvd_2 : 2; + bdrkreg_t mec_underflow : 2; + bdrkreg_t mec_rsrvd_1 : 2; + bdrkreg_t mec_tail_timeout : 2; + bdrkreg_t mec_rsrvd : 50; + } xb_mp0_error_clear_fld_s; +} xb_mp0_error_clear_u_t; + +#else + +typedef union xb_mp0_error_clear_u { + bdrkreg_t xb_mp0_error_clear_regval; + struct { + bdrkreg_t mec_rsrvd : 50; + bdrkreg_t mec_tail_timeout : 2; + bdrkreg_t mec_rsrvd_1 : 2; + bdrkreg_t mec_underflow : 2; + bdrkreg_t mec_rsrvd_2 : 2; + bdrkreg_t mec_overflow : 2; + bdrkreg_t mec_rsrvd_3 : 4; + } xb_mp0_error_clear_fld_s; +} xb_mp0_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by MIQ. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_xm_miq_error_clear_u { + bdrkreg_t xb_xm_miq_error_clear_regval; + struct { + bdrkreg_t xmec_rsrvd_1 : 4; + bdrkreg_t xmec_deadlock_timeout : 4; + bdrkreg_t xmec_rsrvd : 56; + } xb_xm_miq_error_clear_fld_s; +} xb_xm_miq_error_clear_u_t; + +#else + +typedef union xb_xm_miq_error_clear_u { + bdrkreg_t xb_xm_miq_error_clear_regval; + struct { + bdrkreg_t xmec_rsrvd : 56; + bdrkreg_t xmec_deadlock_timeout : 4; + bdrkreg_t xmec_rsrvd_1 : 4; + } xb_xm_miq_error_clear_fld_s; +} xb_xm_miq_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by NOQ. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_noq_error_clear_u { + bdrkreg_t xb_noq_error_clear_regval; + struct { + bdrkreg_t nec_rsvd : 4; + bdrkreg_t nec_overflow : 4; + bdrkreg_t nec_underflow : 4; + bdrkreg_t nec_tail_timeout : 4; + bdrkreg_t nec_rsrvd : 48; + } xb_noq_error_clear_fld_s; +} xb_noq_error_clear_u_t; + +#else + +typedef union xb_noq_error_clear_u { + bdrkreg_t xb_noq_error_clear_regval; + struct { + bdrkreg_t nec_rsrvd : 48; + bdrkreg_t nec_tail_timeout : 4; + bdrkreg_t nec_underflow : 4; + bdrkreg_t nec_overflow : 4; + bdrkreg_t nec_rsvd : 4; + } xb_noq_error_clear_fld_s; +} xb_noq_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by LOQ. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_loq_error_clear_u { + bdrkreg_t xb_loq_error_clear_regval; + struct { + bdrkreg_t lec_invalid_xsel : 2; + bdrkreg_t lec_rsrvd_1 : 6; + bdrkreg_t lec_underflow : 2; + bdrkreg_t lec_rsvd : 2; + bdrkreg_t lec_tail_timeout : 2; + bdrkreg_t lec_rsrvd : 50; + } xb_loq_error_clear_fld_s; +} xb_loq_error_clear_u_t; + +#else + +typedef union xb_loq_error_clear_u { + bdrkreg_t xb_loq_error_clear_regval; + struct { + bdrkreg_t lec_rsrvd : 50; + bdrkreg_t lec_tail_timeout : 2; + bdrkreg_t lec_rsvd : 2; + bdrkreg_t lec_underflow : 2; + bdrkreg_t lec_rsrvd_1 : 6; + bdrkreg_t lec_invalid_xsel : 2; + } xb_loq_error_clear_fld_s; +} xb_loq_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * Records errors seen by LIQ. Note that the LIQ only records errors * + * for the request channel. The reply channel can never deadlock or * + * overflow because it does not have hardware flow control. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_liq_error_clear_u { + bdrkreg_t xb_liq_error_clear_regval; + struct { + bdrkreg_t lec_overflow : 1; + bdrkreg_t lec_rsrvd_1 : 3; + bdrkreg_t lec_deadlock_timeout : 1; + bdrkreg_t lec_rsrvd : 59; + } xb_liq_error_clear_fld_s; +} xb_liq_error_clear_u_t; + +#else + +typedef union xb_liq_error_clear_u { + bdrkreg_t xb_liq_error_clear_regval; + struct { + bdrkreg_t lec_rsrvd : 59; + bdrkreg_t lec_deadlock_timeout : 1; + bdrkreg_t lec_rsrvd_1 : 3; + bdrkreg_t lec_overflow : 1; + } xb_liq_error_clear_fld_s; +} xb_liq_error_clear_u_t; + +#endif + + + + +/************************************************************************ + * * + * First error is latched whenever the Valid bit is clear and an * + * error occurs. Any valid bit on in this register causes an * + * interrupt to PI0 and PI1. This interrupt bit will persist until * + * the specific error register to capture the error is cleared, then * + * the FIRST_ERROR register is cleared (in that oder.) The * + * FIRST_ERROR register is not writable, but will be set when any of * + * the corresponding error registers are written by software. * + * * + ************************************************************************/ + + + + +#ifdef LITTLE_ENDIAN + +typedef union xb_first_error_clear_u { + bdrkreg_t xb_first_error_clear_regval; + struct { + bdrkreg_t fec_type : 4; + bdrkreg_t fec_channel : 4; + bdrkreg_t fec_source : 4; + bdrkreg_t fec_valid : 1; + bdrkreg_t fec_rsrvd : 51; + } xb_first_error_clear_fld_s; +} xb_first_error_clear_u_t; + +#else + +typedef union xb_first_error_clear_u { + bdrkreg_t xb_first_error_clear_regval; + struct { + bdrkreg_t fec_rsrvd : 51; + bdrkreg_t fec_valid : 1; + bdrkreg_t fec_source : 4; + bdrkreg_t fec_channel : 4; + bdrkreg_t fec_type : 4; + } xb_first_error_clear_fld_s; +} xb_first_error_clear_u_t; + +#endif + + + + + + +#endif /* _LANGUAGE_C */ + +/************************************************************************ + * * + * The following defines were not formed into structures * + * * + * This could be because the document did not contain details of the * + * register, or because the automated script did not recognize the * + * register details in the documentation. If these register need * + * structure definition, please create them manually * + * * + * XB_POQ1_ERROR 0x700030 * + * XB_PIQ1_ERROR 0x700038 * + * XB_MP1_ERROR 0x700048 * + * XB_MMQ_ERROR 0x700050 * + * XB_NIQ_ERROR 0x700068 * + * XB_IOQ_ERROR 0x700070 * + * XB_IIQ_ERROR 0x700078 * + * XB_POQ1_ERROR_CLEAR 0x700130 * + * XB_PIQ1_ERROR_CLEAR 0x700138 * + * XB_MP1_ERROR_CLEAR 0x700148 * + * XB_MMQ_ERROR_CLEAR 0x700150 * + * XB_NIQ_ERROR_CLEAR 0x700168 * + * XB_IOQ_ERROR_CLEAR 0x700170 * + * XB_IIQ_ERROR_CLEAR 0x700178 * + * * + ************************************************************************/ + + +/************************************************************************ + * * + * MAKE ALL ADDITIONS AFTER THIS LINE * + * * + ************************************************************************/ + + + + + +#endif /* _ASM_SN_SN1_HUBXB_H */ diff --git a/include/asm-ia64/sn/sn1/hubxb_next.h b/include/asm-ia64/sn/sn1/hubxb_next.h new file mode 100644 index 000000000..ce3fea50c --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubxb_next.h @@ -0,0 +1,32 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_HUBXB_NEXT_H +#define _ASM_SN_SN1_HUBXB_NEXT_H + +/* XB_FIRST_ERROR fe_source field encoding */ +#define XVE_SOURCE_POQ0 0xf /* 1111 */ +#define XVE_SOURCE_PIQ0 0xe /* 1110 */ +#define XVE_SOURCE_POQ1 0xd /* 1101 */ +#define XVE_SOURCE_PIQ1 0xc /* 1100 */ +#define XVE_SOURCE_MP0 0xb /* 1011 */ +#define XVE_SOURCE_MP1 0xa /* 1010 */ +#define XVE_SOURCE_MMQ 0x9 /* 1001 */ +#define XVE_SOURCE_MIQ 0x8 /* 1000 */ +#define XVE_SOURCE_NOQ 0x7 /* 0111 */ +#define XVE_SOURCE_NIQ 0x6 /* 0110 */ +#define XVE_SOURCE_IOQ 0x5 /* 0101 */ +#define XVE_SOURCE_IIQ 0x4 /* 0100 */ +#define XVE_SOURCE_LOQ 0x3 /* 0011 */ +#define XVE_SOURCE_LIQ 0x2 /* 0010 */ + +/* XB_PARMS fields */ +#define XBP_RESET_DEFAULTS 0x0008000080000021LL + +#endif /* _ASM_SN_SN1_HUBXB_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/ip27config.h b/include/asm-ia64/sn/sn1/ip27config.h new file mode 100644 index 000000000..2803ebaff --- /dev/null +++ b/include/asm-ia64/sn/sn1/ip27config.h @@ -0,0 +1,657 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_IP27CONFIG_H +#define _ASM_SN_SN1_IP27CONFIG_H + + +/* + * Structure: ip27config_s + * Typedef: ip27config_t + * Purpose: Maps out the region of the boot prom used to define + * configuration information. + * Notes: Corresponds to ip27config structure found in start.s. + * Fields are ulong where possible to facilitate IP27 PROM fetches. + */ + +#define CONFIG_INFO_OFFSET 0x60 + +#define IP27CONFIG_ADDR (LBOOT_BASE + \ + CONFIG_INFO_OFFSET) +#define IP27CONFIG_ADDR_NODE(n) (NODE_RBOOT_BASE(n) + \ + CONFIG_INFO_OFFSET) + +/* Offset to the config_type field within local ip27config structure */ +#define CONFIG_FLAGS_ADDR (IP27CONFIG_ADDR + 72) +/* Offset to the config_type field in the ip27config structure on + * node with nasid n + */ +#define CONFIG_FLAGS_ADDR_NODE(n) (IP27CONFIG_ADDR_NODE(n) + 72) + +/* Meaning of each valid bit in the config flags + * None are currently defined + */ + +/* Meaning of each mach_type value + */ +#define SN1_MACH_TYPE 0 + +/* + * Since 800 ns works well with various HUB frequencies, (such as 360, + * 380, 390, and 400 MHZ), we now use 800ns rtc cycle time instead of + * 1 microsec. + */ +#define IP27_RTC_FREQ 1250 /* 800ns cycle time */ + +#if _LANGUAGE_C + +typedef struct ip27config_s { /* KEEP IN SYNC w/ start.s & below */ + uint time_const; /* Time constant */ + uint r10k_mode; /* R10k boot mode bits */ + + uint64_t magic; /* CONFIG_MAGIC */ + + uint64_t freq_cpu; /* Hz */ + uint64_t freq_hub; /* Hz */ + uint64_t freq_rtc; /* Hz */ + + uint ecc_enable; /* ECC enable flag */ + uint fprom_cyc; /* FPROM_CYC speed control */ + + uint mach_type; /* Inidicate IP27 (0) or Sn00 (1) */ + + uint check_sum_adj; /* Used after config hdr overlay */ + /* to make the checksum 0 again */ + uint flash_count; /* Value incr'd on each PROM flash */ + uint fprom_wr; /* FPROM_WR speed control */ + + uint pvers_vers; /* Prom version number */ + uint pvers_rev; /* Prom revision number */ + uint config_type; /* To support special configurations + * (none currently defined) + */ +} ip27config_t; + +typedef struct { + uint r10k_mode; /* R10k boot mode bits */ + uint freq_cpu; /* Hz */ + uint freq_hub; /* Hz */ + char fprom_cyc; /* FPROM_CYC speed control */ + char mach_type; /* IP35(0) is only type defined */ + char fprom_wr; /* FPROM_WR speed control */ +} config_modifiable_t; + +#define IP27CONFIG (*(ip27config_t *) IP27CONFIG_ADDR) +#define IP27CONFIG_NODE(n) (*(ip27config_t *) IP27CONFIG_ADDR_NODE(n)) +#define SN00 0 /* IP35 has no Speedo equivalent */ + +/* Get the config flags from local ip27config */ +#define CONFIG_FLAGS (*(uint *) (CONFIG_FLAGS_ADDR)) + +/* Get the config flags from ip27config on the node + * with nasid n + */ +#define CONFIG_FLAGS_NODE(n) (*(uint *) (CONFIG_FLAGS_ADDR_NODE(n))) + +/* Macro to check if the local ip27config indicates a config + * of 12 p 4io + */ +#define CONFIG_12P4I (0) /* IP35 has no 12p4i equivalent */ + +/* Macro to check if the ip27config on node with nasid n + * indicates a config of 12 p 4io + */ +#define CONFIG_12P4I_NODE(n) (0) + +#endif /* _LANGUAGE_C */ + +#if _LANGUAGE_ASSEMBLY + .struct 0 /* KEEP IN SYNC WITH C structure */ + +ip27c_time_const: .word 0 +ip27c_r10k_mode: .word 0 + +ip27c_magic: .dword 0 + +ip27c_freq_cpu: .dword 0 +ip27c_freq_hub: .dword 0 +ip27c_freq_rtc: .dword 0 + +ip27c_ecc_enable: .word 1 +ip27c_fprom_cyc: .word 0 + +ip27c_mach_type: .word 0 +ip27c_check_sum_adj: .word 0 + +ip27c_flash_count: .word 0 +ip27c_fprom_wr: .word 0 + +ip27c_pvers_vers: .word 0 +ip27c_pvers_rev: .word 0 + +ip27c_config_type: .word 0 /* To recognize special configs */ +#endif /* _LANGUAGE_ASSEMBLY */ + +/* + * R10000 Configuration Cycle - These define the SYSAD values used + * during the reset cycle. + */ + +#define IP27C_R10000_KSEG0CA_SHFT 0 +#define IP27C_R10000_KSEG0CA_MASK (7 << IP27C_R10000_KSEG0CA_SHFT) +#define IP27C_R10000_KSEG0CA(_B) ((_B) << IP27C_R10000_KSEG0CA_SHFT) + +#define IP27C_R10000_DEVNUM_SHFT 3 +#define IP27C_R10000_DEVNUM_MASK (3 << IP27C_R10000_DEVNUM_SHFT) +#define IP27C_R10000_DEVNUM(_B) ((_B) << IP27C_R10000_DEVNUM_SHFT) + +#define IP27C_R10000_CRPT_SHFT 5 +#define IP27C_R10000_CRPT_MASK (1 << IP27C_R10000_CRPT_SHFT) +#define IP27C_R10000_CPRT(_B) ((_B)<<IP27C_R10000_CRPT_SHFT) + +#define IP27C_R10000_PER_SHFT 6 +#define IP27C_R10000_PER_MASK (1 << IP27C_R10000_PER_SHFT) +#define IP27C_R10000_PER(_B) ((_B) << IP27C_R10000_PER_SHFT) + +#define IP27C_R10000_PRM_SHFT 7 +#define IP27C_R10000_PRM_MASK (3 << IP27C_R10000_PRM_SHFT) +#define IP27C_R10000_PRM(_B) ((_B) << IP27C_R10000_PRM_SHFT) + +#define IP27C_R10000_SCD_SHFT 9 +#define IP27C_R10000_SCD_MASK (0xf << IP27C_R10000_SCD_MASK) +#define IP27C_R10000_SCD(_B) ((_B) << IP27C_R10000_SCD_SHFT) + +#define IP27C_R10000_SCBS_SHFT 13 +#define IP27C_R10000_SCBS_MASK (1 << IP27C_R10000_SCBS_SHFT) +#define IP27C_R10000_SCBS(_B) (((_B)) << IP27C_R10000_SCBS_SHFT) + +#define IP27C_R10000_SCCE_SHFT 14 +#define IP27C_R10000_SCCE_MASK (1 << IP27C_R10000_SCCE_SHFT) +#define IP27C_R10000_SCCE(_B) ((_B) << IP27C_R10000_SCCE_SHFT) + +#define IP27C_R10000_ME_SHFT 15 +#define IP27C_R10000_ME_MASK (1 << IP27C_R10000_ME_SHFT) +#define IP27C_R10000_ME(_B) ((_B) << IP27C_R10000_ME_SHFT) + +#define IP27C_R10000_SCS_SHFT 16 +#define IP27C_R10000_SCS_MASK (7 << IP27C_R10000_SCS_SHFT) +#define IP27C_R10000_SCS(_B) ((_B) << IP27C_R10000_SCS_SHFT) + +#define IP27C_R10000_SCCD_SHFT 19 +#define IP27C_R10000_SCCD_MASK (7 << IP27C_R10000_SCCD_SHFT) +#define IP27C_R10000_SCCD(_B) ((_B) << IP27C_R10000_SCCD_SHFT) + +#define IP27C_R10000_SCCT_SHFT 25 +#define IP27C_R10000_SCCT_MASK (0xf << IP27C_R10000_SCCT_SHFT) +#define IP27C_R10000_SCCT(_B) ((_B) << IP27C_R10000_SCCT_SHFT) + +#define IP27C_R10000_ODSC_SHFT 29 +#define IP27C_R10000_ODSC_MASK (1 << IP27C_R10000_ODSC_SHFT) +#define IP27C_R10000_ODSC(_B) ((_B) << IP27C_R10000_ODSC_SHFT) + +#define IP27C_R10000_ODSYS_SHFT 30 +#define IP27C_R10000_ODSYS_MASK (1 << IP27C_R10000_ODSYS_SHFT) +#define IP27C_R10000_ODSYS(_B) ((_B) << IP27C_R10000_ODSYS_SHFT) + +#define IP27C_R10000_CTM_SHFT 31 +#define IP27C_R10000_CTM_MASK (1 << IP27C_R10000_CTM_SHFT) +#define IP27C_R10000_CTM(_B) ((_B) << IP27C_R10000_CTM_SHFT) + +#define IP27C_MHZ(x) (1000000 * (x)) +#define IP27C_KHZ(x) (1000 * (x)) +#define IP27C_MB(x) ((x) << 20) + +/* + * PROM Configurations + */ + +#define CONFIG_MAGIC 0x69703237636f6e66 + +/* The high 32 bits of the "mode bits". Bits 7..0 contain one more + * than the number of 5ms clocks in the 100ms "long delay" intervals + * of the TRex reset sequence. Bit 8 is the "synergy mode" bit. + */ +#define CONFIG_TIME_CONST 0x15 + +#define CONFIG_ECC_ENABLE 1 +#define CONFIG_CHECK_SUM_ADJ 0 +#define CONFIG_DEFAULT_FLASH_COUNT 0 + +/* + * Some promICEs have trouble if CONFIG_FPROM_SETUP is too low. + * The nominal value for 100 MHz hub is 5, for 200MHz bedrock is 16. + * any update to the below should also reflected in the logic in + * IO7prom/flashprom.c function _verify_config_info and _fill_in_config_info + */ + +/* default junk bus timing values to use */ +#define CONFIG_SYNERGY_ENABLE 0xff +#define CONFIG_SYNERGY_SETUP 0xff +#define CONFIG_UART_ENABLE 0x0c +#define CONFIG_UART_SETUP 0x02 +#define CONFIG_FPROM_ENABLE 0x10 +#define CONFIG_FPROM_SETUP 0x10 + +#define CONFIG_FREQ_RTC IP27C_KHZ(IP27_RTC_FREQ) + +#if _LANGUAGE_C + +/* we are going to define all the known configs is a table + * for building hex images we will pull out the particular + * slice we care about by using the IP27_CONFIG_XX_XX as + * entries into the table + * to keep the table of reasonable size we only include the + * values that differ across configurations + * please note then that this makes assumptions about what + * will and will not change across configurations + */ + +/* these numbers are as the are ordered in the table below */ +#define IP27_CONFIG_UNKNOWN -1 +#define IP27_CONFIG_SN1_1MB_200_400_200_TABLE 0 +#define IP27_CONFIG_SN00_4MB_100_200_133_TABLE 1 +#define IP27_CONFIG_SN1_4MB_200_400_267_TABLE 2 +#define IP27_CONFIG_SN1_8MB_200_500_250_TABLE 3 +#define IP27_CONFIG_SN1_8MB_200_400_267_TABLE 4 +#define IP27_CONFIG_SN1_4MB_180_360_240_TABLE 5 +#define NUMB_IP_CONFIGS 6 + +#ifdef DEF_IP_CONFIG_TABLE +/* + * N.B.: A new entry needs to be added here everytime a new config is added + * The table is indexed by the PIMM PSC value + */ + +static int psc_to_flash_config[] = { + IP27_CONFIG_SN1_4MB_200_400_267_TABLE, /* 0x0 */ + IP27_CONFIG_SN1_8MB_200_500_250_TABLE, /* 0x1 */ + IP27_CONFIG_SN1_8MB_200_400_267_TABLE, /* 0x2 */ + IP27_CONFIG_UNKNOWN, /* 0x3 */ + IP27_CONFIG_UNKNOWN, /* 0x4 */ + IP27_CONFIG_UNKNOWN, /* 0x5 */ + IP27_CONFIG_UNKNOWN, /* 0x6 */ + IP27_CONFIG_UNKNOWN, /* 0x7 */ + IP27_CONFIG_SN1_4MB_180_360_240_TABLE, /* 0x8 */ + IP27_CONFIG_UNKNOWN, /* 0x9 */ + IP27_CONFIG_UNKNOWN, /* 0xa */ + IP27_CONFIG_UNKNOWN, /* 0xb */ + IP27_CONFIG_UNKNOWN, /* 0xc */ + IP27_CONFIG_UNKNOWN, /* 0xd */ + IP27_CONFIG_SN00_4MB_100_200_133_TABLE, /* 0xe O200 PIMM for bringup */ + IP27_CONFIG_UNKNOWN /* 0xf == PIMM not installed */ +}; + +static config_modifiable_t ip_config_table[NUMB_IP_CONFIGS] = { +/* the 1MB_200_400_200 values (Generic settings, will work for any config.) */ +{ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(1) + \ + IP27C_R10000_SCCD(3) + \ + IP27C_R10000_SCCT(9) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)), + IP27C_MHZ(400), + IP27C_MHZ(200), + CONFIG_FPROM_SETUP, + SN1_MACH_TYPE, + CONFIG_FPROM_ENABLE +}, + +/* the 4MB_100_200_133 values (O200 PIMM w/translation board, PSC 0xe) + * (SysAD at 100MHz (SCD=3), and bedrock core at 200 MHz) */ +{ + /* ODSYS == 0 means HSTL1 on SysAD bus; other PIMMs use HSTL2 */ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(3) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(9) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(0) + \ + IP27C_R10000_CTM(0)), + IP27C_MHZ(200), + IP27C_MHZ(200), + CONFIG_FPROM_SETUP, + SN1_MACH_TYPE, + CONFIG_FPROM_ENABLE +}, + +/* 4MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1602-001, PSC 0x0) */ +{ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(3) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(0xa) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)), + IP27C_MHZ(400), + IP27C_MHZ(200), + CONFIG_FPROM_SETUP, + SN1_MACH_TYPE, + CONFIG_FPROM_ENABLE +}, + +/* 8MB_200_500_250 values (R14K, 4.0ns, DDR1, 030-1520-001, PSC 0x1) */ +{ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(4) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(4) + \ + IP27C_R10000_SCCD(3) + \ + IP27C_R10000_SCCT(0xa) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)), + IP27C_MHZ(500), + IP27C_MHZ(200), + CONFIG_FPROM_SETUP, + SN1_MACH_TYPE, + CONFIG_FPROM_ENABLE +}, + +/* 8MB_200_400_267 values (R12KS, 3.7ns, LWR, 030-1616-001, PSC 0x2) */ +{ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(4) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(0xa) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)), + IP27C_MHZ(400), + IP27C_MHZ(200), + CONFIG_FPROM_SETUP, + SN1_MACH_TYPE, + CONFIG_FPROM_ENABLE +}, + +/* 4MB_180_360_240 values (R12KS, 3.7ns, LWR, 030-1627-001, PSC 0x8) + * (SysAD at 180 MHz (SCD=3, the fastest possible), bedrock core at 200MHz) */ +{ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(3) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(9) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)), + IP27C_MHZ(360), + IP27C_MHZ(200), + CONFIG_FPROM_SETUP, + SN1_MACH_TYPE, + CONFIG_FPROM_ENABLE +}, + +}; +#else +extern config_modifiable_t ip_config_table[]; +#endif /* DEF_IP27_CONFIG_TABLE */ + +#ifdef IP27_CONFIG_SN00_4MB_100_200_133 +#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].r10k_mode +#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_cpu +#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].freq_hub +#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_cyc +#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].mach_type +#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN00_4MB_100_200_133_TABLE].fprom_wr +#endif /* IP27_CONFIG_SN00_4MB_100_200_133 */ + +#ifdef IP27_CONFIG_SN1_1MB_200_400_200 +#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].r10k_mode +#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_cpu +#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].freq_hub +#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_cyc +#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].mach_type +#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_1MB_200_400_200_TABLE].fprom_wr +#endif /* IP27_CONFIG_SN1_1MB_200_400_200 */ + +#ifdef IP27_CONFIG_SN1_4MB_200_400_267 +#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].r10k_mode +#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_cpu +#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].freq_hub +#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_cyc +#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].mach_type +#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_200_400_267_TABLE].fprom_wr +#endif /* IP27_CONFIG_SN1_4MB_200_400_267 */ + +#ifdef IP27_CONFIG_SN1_8MB_200_500_250 +#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].r10k_mode +#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_cpu +#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].freq_hub +#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_cyc +#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].mach_type +#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_500_250_TABLE].fprom_wr +#endif /* IP27_CONFIG_SN1_8MB_200_500_250 */ + +#ifdef IP27_CONFIG_SN1_8MB_200_400_267 +#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].r10k_mode +#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_cpu +#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].freq_hub +#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_cyc +#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].mach_type +#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_8MB_200_400_267_TABLE].fprom_wr +#endif /* IP27_CONFIG_SN1_8MB_200_400_267 */ + +#ifdef IP27_CONFIG_SN1_4MB_180_360_240 +#define CONFIG_CPU_MODE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].r10k_mode +#define CONFIG_FREQ_CPU ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_cpu +#define CONFIG_FREQ_HUB ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].freq_hub +#define CONFIG_FPROM_CYC ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_cyc +#define CONFIG_MACH_TYPE ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].mach_type +#define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr +#endif /* IP27_CONFIG_SN1_4MB_180_360_240 */ + +#endif /* _LANGUAGE_C */ + +#if _LANGUAGE_ASSEMBLY + +/* these need to be in here since we need assembly definitions + * for building hex images (as required by start.s) + */ +#ifdef IP27_CONFIG_SN00_4MB_100_200_133 +#ifdef IRIX +/* Set PrcReqMax to 0 to reduce memory problems */ +#define BRINGUP_PRM_VAL 0 +#else +#define BRINGUP_PRM_VAL 3 +#endif +#define CONFIG_CPU_MODE \ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(BRINGUP_PRM_VAL) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(3) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(9) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(0) + \ + IP27C_R10000_CTM(0)) +#define CONFIG_FREQ_CPU IP27C_MHZ(200) +#define CONFIG_FREQ_HUB IP27C_MHZ(200) +#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP +#define CONFIG_MACH_TYPE SN1_MACH_TYPE +#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE +#endif /* IP27_CONFIG_SN00_4MB_100_200_133 */ + +#ifdef IP27_CONFIG_SN1_1MB_200_400_200 +#define CONFIG_CPU_MODE \ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(1) + \ + IP27C_R10000_SCCD(3) + \ + IP27C_R10000_SCCT(9) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)) +#define CONFIG_FREQ_CPU IP27C_MHZ(400) +#define CONFIG_FREQ_HUB IP27C_MHZ(200) +#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP +#define CONFIG_MACH_TYPE SN1_MACH_TYPE +#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE +#endif /* IP27_CONFIG_SN1_1MB_200_400_200 */ + +#ifdef IP27_CONFIG_SN1_4MB_200_400_267 +#define CONFIG_CPU_MODE \ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(3) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(0xa) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)) +#define CONFIG_FREQ_CPU IP27C_MHZ(400) +#define CONFIG_FREQ_HUB IP27C_MHZ(200) +#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP +#define CONFIG_MACH_TYPE SN1_MACH_TYPE +#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE +#endif /* IP27_CONFIG_SN1_4MB_200_400_267 */ + +#ifdef IP27_CONFIG_SN1_8MB_200_500_250 +#define CONFIG_CPU_MODE \ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(4) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(4) + \ + IP27C_R10000_SCCD(3) + \ + IP27C_R10000_SCCT(0xa) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)) +#define CONFIG_FREQ_CPU IP27C_MHZ(500) +#define CONFIG_FREQ_HUB IP27C_MHZ(200) +#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP +#define CONFIG_MACH_TYPE SN1_MACH_TYPE +#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE +#endif /* IP27_CONFIG_SN1_8MB_200_500_250 */ + +#ifdef IP27_CONFIG_SN1_8MB_200_400_267 +#define CONFIG_CPU_MODE \ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(4) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(0xa) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)) +#define CONFIG_FREQ_CPU IP27C_MHZ(400) +#define CONFIG_FREQ_HUB IP27C_MHZ(200) +#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP +#define CONFIG_MACH_TYPE SN1_MACH_TYPE +#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE +#endif /* IP27_CONFIG_SN1_8MB_200_400_267 */ + +#ifdef IP27_CONFIG_SN1_4MB_180_360_240 +#define CONFIG_CPU_MODE \ + (IP27C_R10000_KSEG0CA(5) + \ + IP27C_R10000_DEVNUM(0) + \ + IP27C_R10000_CPRT(0) + \ + IP27C_R10000_PER(0) + \ + IP27C_R10000_PRM(3) + \ + IP27C_R10000_SCD(3) + \ + IP27C_R10000_SCBS(1) + \ + IP27C_R10000_SCCE(0) + \ + IP27C_R10000_ME(1) + \ + IP27C_R10000_SCS(3) + \ + IP27C_R10000_SCCD(2) + \ + IP27C_R10000_SCCT(9) + \ + IP27C_R10000_ODSC(0) + \ + IP27C_R10000_ODSYS(1) + \ + IP27C_R10000_CTM(0)) +#define CONFIG_FREQ_CPU IP27C_MHZ(360) +#define CONFIG_FREQ_HUB IP27C_MHZ(200) +#define CONFIG_FPROM_CYC CONFIG_FPROM_SETUP +#define CONFIG_MACH_TYPE SN1_MACH_TYPE +#define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE +#endif /* IP27_CONFIG_SN1_4MB_180_360_240 */ + +#endif /* _LANGUAGE_C */ + +#endif /* _ASM_SN_SN1_IP27CONFIG_H */ diff --git a/include/asm-ia64/sn/sn1/kldir.h b/include/asm-ia64/sn/sn1/kldir.h new file mode 100644 index 000000000..e8d4935d8 --- /dev/null +++ b/include/asm-ia64/sn/sn1/kldir.h @@ -0,0 +1,222 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_KLDIR_H +#define _ASM_SN_SN1_KLDIR_H + +/* + * The upper portion of the memory map applies during boot + * only and is overwritten by IRIX/SYMMON. The minimum memory bank + * size on IP35 is 64M, which provides a limit on the amount of space + * the PROM can assume it has available. + * + * Most of the addresses below are defined as macros in this file, or + * in SN/addrs.h or SN/SN1/addrs.h. + * + * MEMORY MAP PER NODE + * + * 0x4000000 (64M) +-----------------------------------------+ + * | | + * | | + * | IO7 TEXT/DATA/BSS/stack | + * 0x3000000 (48M) +-----------------------------------------+ + * | Free | + * 0x2102000 (>33M) +-----------------------------------------+ + * | IP35 Topology (PCFG) + misc data | + * 0x2000000 (32M) +-----------------------------------------+ + * | IO7 BUFFERS FOR FLASH ENET IOC3 | + * 0x1F80000 (31.5M) +-----------------------------------------+ + * | Free | + * 0x1C00000 (28M) +-----------------------------------------+ + * | IP35 PROM TEXT/DATA/BSS/stack | + * 0x1A00000 (26M) +-----------------------------------------+ + * | Routing temp. space | + * 0x1800000 (24M) +-----------------------------------------+ + * | Diagnostics temp. space | + * 0x1500000 (21M) +-----------------------------------------+ + * | Free | + * 0x1400000 (20M) +-----------------------------------------+ + * | IO7 PROM temporary copy | + * 0x1300000 (19M) +-----------------------------------------+ + * | | + * | Free | + * | (UNIX DATA starts above 0x1000000) | + * | | + * +-----------------------------------------+ + * | UNIX DEBUG Version | + * 0x0310000 (3.1M) +-----------------------------------------+ + * | SYMMON, loaded just below UNIX | + * | (For UNIX Debug only) | + * | | + * | | + * 0x006C000 (432K) +-----------------------------------------+ + * | SYMMON STACK [NUM_CPU_PER_NODE] | + * | (For UNIX Debug only) | + * 0x004C000 (304K) +-----------------------------------------+ + * | | + * | | + * | UNIX NON-DEBUG Version | + * 0x0040000 (256K) +-----------------------------------------+ + * + * + * The lower portion of the memory map contains information that is + * permanent and is used by the IP35PROM, IO7PROM and IRIX. + * + * 0x40000 (256K) +-----------------------------------------+ + * | | + * | KLCONFIG (64K) | + * | | + * 0x30000 (192K) +-----------------------------------------+ + * | | + * | PI Error Spools (64K) | + * | | + * 0x20000 (128K) +-----------------------------------------+ + * | | + * | Unused | + * | | + * 0x19000 (100K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 3)| + * 0x18800 (98K) +-----------------------------------------+ + * | cache error eframe (CPU 3) | + * 0x18400 (97K) +-----------------------------------------+ + * | Exception Handlers (CPU 3) | + * 0x18000 (96K) +-----------------------------------------+ + * | | + * | Unused | + * | | + * 0x13c00 (79K) +-----------------------------------------+ + * | GPDA (8k) | + * 0x11c00 (71K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 2)| + * 0x10800 (66k) +-----------------------------------------+ + * | cache error eframe (CPU 2) | + * 0x10400 (65K) +-----------------------------------------+ + * | Exception Handlers (CPU 2) | + * 0x10000 (64K) +-----------------------------------------+ + * | | + * | Unused | + * | | + * 0x0b400 (45K) +-----------------------------------------+ + * | GDA (1k) | + * 0x0b000 (44K) +-----------------------------------------+ + * | NMI Eframe areas (4) | + * 0x0a000 (40K) +-----------------------------------------+ + * | NMI Register save areas (4) | + * 0x09000 (36K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 1)| + * 0x08800 (34K) +-----------------------------------------+ + * | cache error eframe (CPU 1) | + * 0x08400 (33K) +-----------------------------------------+ + * | Exception Handlers (CPU 1) | + * 0x08000 (32K) +-----------------------------------------+ + * | | + * | | + * | Unused | + * | | + * | | + * 0x04000 (16K) +-----------------------------------------+ + * | NMI Handler (Protected Page) | + * 0x03000 (12K) +-----------------------------------------+ + * | ARCS PVECTORS (master node only) | + * 0x02c00 (11K) +-----------------------------------------+ + * | ARCS TVECTORS (master node only) | + * 0x02800 (10K) +-----------------------------------------+ + * | LAUNCH [NUM_CPU] | + * 0x02400 (9K) +-----------------------------------------+ + * | Low memory directory (KLDIR) | + * 0x02000 (8K) +-----------------------------------------+ + * | ARCS SPB (1K) | + * 0x01000 (4K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 0)| + * 0x00800 (2k) +-----------------------------------------+ + * | cache error eframe (CPU 0) | + * 0x00400 (1K) +-----------------------------------------+ + * | Exception Handlers (CPU 0) | + * 0x00000 (0K) +-----------------------------------------+ + */ + +/* + * NOTE: To change the kernel load address, you must update: + * - the appropriate elspec files in irix/kern/master.d + * - NODEBUGUNIX_ADDR in SN/SN1/addrs.h + * - IP27_FREEMEM_OFFSET below + * - KERNEL_START_OFFSET below (if supporting cells) + */ + + +/* + * This is defined here because IP27_SYMMON_STK_SIZE must be at least what + * we define here. Since it's set up in the prom. We can't redefine it later + * and expect more space to be allocated. The way to find out the true size + * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE + * for a particular node. + */ +#define SYMMON_STACK_SIZE 0x8000 + +#if defined (PROM) || defined (SABLE) + +/* + * These defines are prom version dependent. No code other than the IP35 + * prom should attempt to use these values. + */ +#define IP27_LAUNCH_OFFSET 0x2400 +#define IP27_LAUNCH_SIZE 0x400 +#define IP27_LAUNCH_COUNT 4 +#define IP27_LAUNCH_STRIDE 0x100 /* could be as small as 0x80 */ + +#define IP27_KLCONFIG_OFFSET 0x30000 +#define IP27_KLCONFIG_SIZE 0x10000 +#define IP27_KLCONFIG_COUNT 1 +#define IP27_KLCONFIG_STRIDE 0 + +#define IP27_NMI_OFFSET 0x3000 +#define IP27_NMI_SIZE 0x100 +#define IP27_NMI_COUNT 4 +#define IP27_NMI_STRIDE 0x40 + +#define IP27_PI_ERROR_OFFSET 0x20000 +#define IP27_PI_ERROR_SIZE 0x10000 +#define IP27_PI_ERROR_COUNT 1 +#define IP27_PI_ERROR_STRIDE 0 + +#define IP27_SYMMON_STK_OFFSET 0x4c000 +#define IP27_SYMMON_STK_SIZE 0x20000 +#define IP27_SYMMON_STK_COUNT 4 +/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */ +#define IP27_SYMMON_STK_STRIDE 0x8000 + +#define IP27_FREEMEM_OFFSET 0x40000 +#define IP27_FREEMEM_SIZE -1 +#define IP27_FREEMEM_COUNT 1 +#define IP27_FREEMEM_STRIDE 0 + +#endif /* PROM || SABLE*/ +/* + * There will be only one of these in a partition so the IO7 must set it up. + */ +#define IO6_GDA_OFFSET 0xb000 +#define IO6_GDA_SIZE 0x400 +#define IO6_GDA_COUNT 1 +#define IO6_GDA_STRIDE 0 + +/* + * save area of kernel nmi regs in the prom format + */ +#define IP27_NMI_KREGS_OFFSET 0x9000 +#define IP27_NMI_KREGS_CPU_SIZE 0x400 +/* + * save area of kernel nmi regs in eframe format + */ +#define IP27_NMI_EFRAME_OFFSET 0xa000 +#define IP27_NMI_EFRAME_SIZE 0x400 + +#define GPDA_OFFSET 0x11c00 + +#endif /* _ASM_SN_SN1_KLDIR_H */ diff --git a/include/asm-ia64/sn/sn1/leds.h b/include/asm-ia64/sn/sn1/leds.h new file mode 100644 index 000000000..85eb645ca --- /dev/null +++ b/include/asm-ia64/sn/sn1/leds.h @@ -0,0 +1,35 @@ +#ifndef _ASM_SN_SN1_LED_H +#define _ASM_SN_SN1_LED_H + +/* + * Copyright (C) 2000 Silicon Graphics, Inc + * Copyright (C) 2000 Jack Steiner (steiner@sgi.com) + */ + +#include <asm/smp.h> + +#define LED0 0xc0000b00100000c0LL /* ZZZ fixme */ + + + +#define LED_AP_START 0x01 /* AP processor started */ +#define LED_AP_IDLE 0x01 + +/* + * Basic macros for flashing the LEDS on an SGI, SN1. + */ + +extern __inline__ void +HUB_SET_LED(int val) +{ + long *ledp; + int eid; + + eid = hard_processor_sapicid() & 3; + ledp = (long*) (LED0 + (eid<<3)); + *ledp = val; +} + + +#endif /* _ASM_SN_SN1_LED_H */ + diff --git a/include/asm-ia64/sn/sn1/promlog.h b/include/asm-ia64/sn/sn1/promlog.h new file mode 100644 index 000000000..4c4b9f2e9 --- /dev/null +++ b/include/asm-ia64/sn/sn1/promlog.h @@ -0,0 +1,85 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_PROMLOG_H +#define _ASM_SN_SN1_PROMLOG_H + +#include <asm/sn/fprom.h> + +#define PROMLOG_MAGIC 0x504c4f49 +#define PROMLOG_VERSION 1 + +#define PROMLOG_OFFSET_MAGIC 0x10 +#define PROMLOG_OFFSET_VERSION 0x14 +#define PROMLOG_OFFSET_SEQUENCE 0x18 +#define PROMLOG_OFFSET_ENTRY0 0x100 + +#define PROMLOG_ERROR_NONE 0 +#define PROMLOG_ERROR_PROM -1 +#define PROMLOG_ERROR_MAGIC -2 +#define PROMLOG_ERROR_CORRUPT -3 +#define PROMLOG_ERROR_BOL -4 +#define PROMLOG_ERROR_EOL -5 +#define PROMLOG_ERROR_POS -6 +#define PROMLOG_ERROR_REPLACE -7 +#define PROMLOG_ERROR_COMPACT -8 +#define PROMLOG_ERROR_FULL -9 +#define PROMLOG_ERROR_ARG -10 +#define PROMLOG_ERROR_UNUSED -11 + +#define PROMLOG_TYPE_UNUSED 0xf +#define PROMLOG_TYPE_LOG 3 +#define PROMLOG_TYPE_LIST 2 +#define PROMLOG_TYPE_VAR 1 +#define PROMLOG_TYPE_DELETED 0 + +#define PROMLOG_TYPE_ANY 98 +#define PROMLOG_TYPE_INVALID 99 + +#define PROMLOG_KEY_MAX 14 +#define PROMLOG_VALUE_MAX 47 +#define PROMLOG_CPU_MAX 4 + +typedef struct promlog_header_s { + unsigned int unused[4]; + unsigned int magic; + unsigned int version; + unsigned int sequence; +} promlog_header_t; + +typedef unsigned int promlog_pos_t; + +typedef struct promlog_ent_s { /* PROM individual entry */ + uint type : 4; + uint cpu_num : 4; + char key[PROMLOG_KEY_MAX + 1]; + + char value[PROMLOG_VALUE_MAX + 1]; + +} promlog_ent_t; + +typedef struct promlog_s { /* Activation handle */ + fprom_t f; + int sector_base; + int cpu_num; + + int active; /* Active sector, 0 or 1 */ + + promlog_pos_t log_start; + promlog_pos_t log_end; + + promlog_pos_t alt_start; + promlog_pos_t alt_end; + + promlog_pos_t pos; + promlog_ent_t ent; +} promlog_t; + +#endif /* _ASM_SN_SN1_PROMLOG_H */ diff --git a/include/asm-ia64/sn/sn1/router.h b/include/asm-ia64/sn/sn1/router.h new file mode 100644 index 000000000..9ae47bc12 --- /dev/null +++ b/include/asm-ia64/sn/sn1/router.h @@ -0,0 +1,669 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_ROUTER_H +#define _ASM_SN_SN1_ROUTER_H + +/* + * Router Register definitions + * + * Macro argument _L always stands for a link number (1 to 8, inclusive). + */ + +#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) + +#include <asm/sn/vector.h> +#include <asm/sn/slotnum.h> +#include <asm/sn/arch.h> + +typedef uint64_t router_reg_t; + +#define MAX_ROUTERS 64 + +#define MAX_ROUTER_PATH 80 + +#define ROUTER_REG_CAST (volatile router_reg_t *) +#define PS_UINT_CAST (__psunsigned_t) +#define UINT64_CAST (uint64_t) +typedef signed char port_no_t; /* Type for router port number */ + +#elif _LANGUAGE_ASSEMBLY + +#define ROUTERREG_CAST +#define PS_UINT_CAST +#define UINT64_CAST + +#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ + +#define MAX_ROUTER_PORTS (8) /* Max. number of ports on a router */ + +#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1) /* for 0 based references */ + +#define PORT_INVALID (-1) /* Invalid port number */ + +#define IS_META(_rp) ((_rp)->flags & PCFG_ROUTER_META) + +#define IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER) + +/* + * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport + * port to generate an output port. + * + * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from + * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8). + * + * These are written to work on unsigned data. + */ + +#define RR_TURN(_L, count) ((_L) + (count) > MAX_ROUTER_PORTS ? \ + (_L) + (count) - MAX_ROUTER_PORTS : \ + (_L) + (count)) + +#define RR_DISTANCE(_LS, _LD) ((_LD) >= (_LS) ? \ + (_LD) - (_LS) : \ + (_LD) + MAX_ROUTER_PORTS - (_LS)) + +/* Router register addresses */ + +#define RR_STATUS_REV_ID 0x00000 /* Status register and Revision ID */ +#define RR_PORT_RESET 0x00008 /* Multiple port reset */ +#define RR_PROT_CONF 0x00010 /* Inter-partition protection conf. */ +#define RR_GLOBAL_PORT_DEF 0x00018 /* Global Port definitions */ +#define RR_GLOBAL_PARMS0 0x00020 /* Parameters shared by all 8 ports */ +#define RR_GLOBAL_PARMS1 0x00028 /* Parameters shared by all 8 ports */ +#define RR_DIAG_PARMS 0x00030 /* Parameters for diag. testing */ +#define RR_DEBUG_ADDR 0x00038 /* Debug address select - debug port*/ +#define RR_LB_TO_L2 0x00040 /* Local Block to L2 cntrl intf reg */ +#define RR_L2_TO_LB 0x00048 /* L2 cntrl intf to Local Block reg */ +#define RR_JBUS_CONTROL 0x00050 /* read/write timing for JBUS intf */ + +#define RR_SCRATCH_REG0 0x00100 /* Scratch 0 is 64 bits */ +#define RR_SCRATCH_REG1 0x00108 /* Scratch 1 is 64 bits */ +#define RR_SCRATCH_REG2 0x00110 /* Scratch 2 is 64 bits */ +#define RR_SCRATCH_REG3 0x00118 /* Scratch 3 is 1 bit */ +#define RR_SCRATCH_REG4 0x00120 /* Scratch 4 is 1 bit */ + +#define RR_JBUS0(_D) (((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses */ +#define RR_JBUS1(_D) (((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses */ + +#define RR_SCRATCH_REG0_WZ 0x00500 /* Scratch 0 is 64 bits */ +#define RR_SCRATCH_REG1_WZ 0x00508 /* Scratch 1 is 64 bits */ +#define RR_SCRATCH_REG2_WZ 0x00510 /* Scratch 2 is 64 bits */ +#define RR_SCRATCH_REG3_SZ 0x00518 /* Scratch 3 is 1 bit */ +#define RR_SCRATCH_REG4_SZ 0x00520 /* Scratch 4 is 1 bit */ + +#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */ +/* Port-specific registers (_L is the link number from 1 to 8) */ + +#define RR_PORT_PARMS(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters */ +#define RR_STATUS_ERROR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs */ +#define RR_CHANNEL_TEST(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */ +#define RR_RESET_MASK(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask */ +#define RR_HISTOGRAM0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */ +#define RR_HISTOGRAM1(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */ +#define RR_HISTOGRAM0_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */ +#define RR_HISTOGRAM1_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */ +#define RR_ERROR_CLEAR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors */ +#define RR_GLOBAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */ +#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3)) +#define RR_LOCAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */ +#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3)) + +#define RR_META_ENTRIES 16 + +#define RR_LOCAL_ENTRIES 128 + +/* + * RR_STATUS_REV_ID mask and shift definitions + */ + +#define RSRI_INPORT_SHFT 52 +#define RSRI_INPORT_MASK (UINT64_CAST 0xf << 52) +#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L)) +#define RSRI_LINKWORKING(_L) (UINT64_CAST 1 << (35 + 2 * (_L))) +#define RSRI_LINKRESETFAIL(_L) (UINT64_CAST 1 << (34 + 2 * (_L))) +#define RSRI_LSTAT_SHFT(_L) (34 + 2 * (_L)) +#define RSRI_LSTAT_MASK(_L) (UINT64_CAST 0x3 << 34 + 2 * (_L)) +#define RSRI_LOCALSBERROR (UINT64_CAST 1 << 35) +#define RSRI_LOCALSTUCK (UINT64_CAST 1 << 34) +#define RSRI_LOCALBADVEC (UINT64_CAST 1 << 33) +#define RSRI_LOCALTAILERR (UINT64_CAST 1 << 32) +#define RSRI_LOCAL_SHFT 32 +#define RSRI_LOCAL_MASK (UINT64_CAST 0xf << 32) +#define RSRI_CHIPREV_SHFT 28 +#define RSRI_CHIPREV_MASK (UINT64_CAST 0xf << 28) +#define RSRI_CHIPID_SHFT 12 +#define RSRI_CHIPID_MASK (UINT64_CAST 0xffff << 12) +#define RSRI_MFGID_SHFT 1 +#define RSRI_MFGID_MASK (UINT64_CAST 0x7ff << 1) + +#define RSRI_LSTAT_WENTDOWN 0 +#define RSRI_LSTAT_RESETFAIL 1 +#define RSRI_LSTAT_LINKUP 2 +#define RSRI_LSTAT_NOTUSED 3 + +/* + * RR_PORT_RESET mask definitions + */ + +#define RPRESET_WARM (UINT64_CAST 1 << 9) +#define RPRESET_LINK(_L) (UINT64_CAST 1 << (_L)) +#define RPRESET_LOCAL (UINT64_CAST 1) + +/* + * RR_PROT_CONF mask and shift definitions + */ + +#define RPCONF_DIRCMPDIS_SHFT 13 +#define RPCONF_DIRCMPDIS_MASK (UINT64_CAST 1 << 13) +#define RPCONF_FORCELOCAL (UINT64_CAST 1 << 12) +#define RPCONF_FLOCAL_SHFT 12 +#define RPCONF_METAID_SHFT 8 +#define RPCONF_METAID_MASK (UINT64_CAST 0xf << 8) +#define RPCONF_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) + +/* + * RR_GLOBAL_PORT_DEF mask and shift definitions + */ + +#define RGPD_MGLBLNHBR_ID_SHFT 12 /* -global neighbor ID */ +#define RGPD_MGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 12) +#define RGPD_MGLBLNHBR_VLD_SHFT 11 /* -global neighbor Valid */ +#define RGPD_MGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 11) +#define RGPD_MGLBLPORT_SHFT 8 /* -global neighbor Port */ +#define RGPD_MGLBLPORT_MASK (UINT64_CAST 0x7 << 8) +#define RGPD_PGLBLNHBR_ID_SHFT 4 /* +global neighbor ID */ +#define RGPD_PGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 4) +#define RGPD_PGLBLNHBR_VLD_SHFT 3 /* +global neighbor Valid */ +#define RGPD_PGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 3) +#define RGPD_PGLBLPORT_SHFT 0 /* +global neighbor Port */ +#define RGPD_PGLBLPORT_MASK (UINT64_CAST 0x7 << 0) + +#define GLBL_PARMS_REGS 2 /* Two Global Parms registers */ + +/* + * RR_GLOBAL_PARMS0 mask and shift definitions + */ + +#define RGPARM0_ARB_VALUE_SHFT 54 /* Local Block Arbitration State */ +#define RGPARM0_ARB_VALUE_MASK (UINT64_CAST 0x7 << 54) +#define RGPARM0_ROTATEARB_SHFT 53 /* Rotate Local Block Arbitration */ +#define RGPARM0_ROTATEARB_MASK (UINT64_CAST 0x1 << 53) +#define RGPARM0_FAIREN_SHFT 52 /* Fairness logic Enable */ +#define RGPARM0_FAIREN_MASK (UINT64_CAST 0x1 << 52) +#define RGPARM0_LOCGNTTO_SHFT 40 /* Local grant timeout */ +#define RGPARM0_LOCGNTTO_MASK (UINT64_CAST 0xfff << 40) +#define RGPARM0_DATELINE_SHFT 38 /* Dateline crossing router */ +#define RGPARM0_DATELINE_MASK (UINT64_CAST 0x1 << 38) +#define RGPARM0_MAXRETRY_SHFT 28 /* Max retry count */ +#define RGPARM0_MAXRETRY_MASK (UINT64_CAST 0x3ff << 28) +#define RGPARM0_URGWRAP_SHFT 20 /* Urgent wrap */ +#define RGPARM0_URGWRAP_MASK (UINT64_CAST 0xff << 20) +#define RGPARM0_DEADLKTO_SHFT 16 /* Deadlock timeout */ +#define RGPARM0_DEADLKTO_MASK (UINT64_CAST 0xf << 16) +#define RGPARM0_URGVAL_SHFT 12 /* Urgent value */ +#define RGPARM0_URGVAL_MASK (UINT64_CAST 0xf << 12) +#define RGPARM0_VCHSELEN_SHFT 11 /* VCH_SEL_EN */ +#define RGPARM0_VCHSELEN_MASK (UINT64_CAST 0x1 << 11) +#define RGPARM0_LOCURGTO_SHFT 9 /* Local urgent timeout */ +#define RGPARM0_LOCURGTO_MASK (UINT64_CAST 0x3 << 9) +#define RGPARM0_TAILVAL_SHFT 5 /* Tail value */ +#define RGPARM0_TAILVAL_MASK (UINT64_CAST 0xf << 5) +#define RGPARM0_CLOCK_SHFT 1 /* Global clock select */ +#define RGPARM0_CLOCK_MASK (UINT64_CAST 0xf << 1) +#define RGPARM0_BYPEN_SHFT 0 +#define RGPARM0_BYPEN_MASK (UINT64_CAST 1) /* Bypass enable */ + +/* + * RR_GLOBAL_PARMS1 shift and mask definitions + */ + +#define RGPARM1_TTOWRAP_SHFT 12 /* Tail timeout wrap */ +#define RGPARM1_TTOWRAP_MASK (UINT64_CAST 0xfffff << 12) +#define RGPARM1_AGERATE_SHFT 8 /* Age rate */ +#define RGPARM1_AGERATE_MASK (UINT64_CAST 0xf << 8) +#define RGPARM1_JSWSTAT_SHFT 0 /* JTAG Sw Register bits */ +#define RGPARM1_JSWSTAT_MASK (UINT64_CAST 0xff << 0) + +/* + * RR_DIAG_PARMS mask and shift definitions + */ + +#define RDPARM_ABSHISTOGRAM (UINT64_CAST 1 << 17) /* Absolute histgrm */ +#define RDPARM_DEADLOCKRESET (UINT64_CAST 1 << 16) /* Reset on deadlck */ +#define RDPARM_DISABLE(_L) (UINT64_CAST 1 << ((_L) + 7)) +#define RDPARM_SENDERROR(_L) (UINT64_CAST 1 << ((_L) - 1)) + +/* + * RR_DEBUG_ADDR mask and shift definitions + */ + +#define RDA_DATA_SHFT 10 /* Observed debug data */ +#define RDA_DATA_MASK (UINT64_CAST 0xffff << 10) +#define RDA_ADDR_SHFT 0 /* debug address for data */ +#define RDA_ADDR_MASK (UINT64_CAST 0x3ff << 0) + +/* + * RR_LB_TO_L2 mask and shift definitions + */ + +#define RLBTOL2_DATA_VLD_SHFT 32 /* data is valid for JTAG controller */ +#define RLBTOL2_DATA_VLD_MASK (UINT64_CAST 0x1 << 32) +#define RLBTOL2_DATA_SHFT 0 /* data bits for JTAG controller */ +#define RLBTOL2_DATA_MASK (UINT64_CAST 0xffffffff) + +/* + * RR_L2_TO_LB mask and shift definitions + */ + +#define RL2TOLB_DATA_VLD_SHFT 33 /* data is valid from JTAG controller */ +#define RL2TOLB_DATA_VLD_MASK (UINT64_CAST 0x1 << 33) +#define RL2TOLB_PARITY_SHFT 32 /* sw implemented parity for data */ +#define RL2TOLB_PARITY_MASK (UINT64_CAST 0x1 << 32) +#define RL2TOLB_DATA_SHFT 0 /* data bits from JTAG controller */ +#define RL2TOLB_DATA_MASK (UINT64_CAST 0xffffffff) + +/* + * RR_JBUS_CONTROL mask and shift definitions + */ + +#define RJC_POS_BITS_SHFT 20 /* Router position bits */ +#define RJC_POS_BITS_MASK (UINT64_CAST 0xf << 20) +#define RJC_RD_DATA_STROBE_SHFT 16 /* count when read data is strobed in */ +#define RJC_RD_DATA_STROBE_MASK (UINT64_CAST 0xf << 16) +#define RJC_WE_OE_HOLD_SHFT 8 /* time OE or WE is held */ +#define RJC_WE_OE_HOLD_MASK (UINT64_CAST 0xff << 8) +#define RJC_ADDR_SET_HLD_SHFT 0 /* time address driven around OE/WE */ +#define RJC_ADDR_SET_HLD_MASK (UINT64_CAST 0xff) + +/* + * RR_SCRATCH_REGx mask and shift definitions + * note: these fields represent a software convention, and are not + * understood/interpreted by the hardware. + */ + +#define RSCR0_BOOTED_SHFT 63 +#define RSCR0_BOOTED_MASK (UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT) +#define RSCR0_LOCALID_SHFT 56 +#define RSCR0_LOCALID_MASK (UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT) +#define RSCR0_UNUSED_SHFT 48 +#define RSCR0_UNUSED_MASK (UINT64_CAST 0xff << RSCR0_UNUSED_SHFT) +#define RSCR0_NIC_SHFT 0 +#define RSCR0_NIC_MASK (UINT64_CAST 0xffffffffffff) + +#define RSCR1_MODID_SHFT 0 +#define RSCR1_MODID_MASK (UINT64_CAST 0xffff) + +/* + * RR_VECTOR_HW_BAR mask and shift definitions + */ + +#define BAR_TX_SHFT 27 /* Barrier in trans(m)it when read */ +#define BAR_TX_MASK (UINT64_CAST 1 << BAR_TX_SHFT) +#define BAR_VLD_SHFT 26 /* Valid Configuration */ +#define BAR_VLD_MASK (UINT64_CAST 1 << BAR_VLD_SHFT) +#define BAR_SEQ_SHFT 24 /* Sequence number */ +#define BAR_SEQ_MASK (UINT64_CAST 3 << BAR_SEQ_SHFT) +#define BAR_LEAFSTATE_SHFT 18 /* Leaf State */ +#define BAR_LEAFSTATE_MASK (UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT) +#define BAR_PARENT_SHFT 14 /* Parent Port */ +#define BAR_PARENT_MASK (UINT64_CAST 0xf << BAR_PARENT_SHFT) +#define BAR_CHILDREN_SHFT 6 /* Child Select port bits */ +#define BAR_CHILDREN_MASK (UINT64_CAST 0xff << BAR_CHILDREN_SHFT) +#define BAR_LEAFCOUNT_SHFT 0 /* Leaf Count to trigger parent */ +#define BAR_LEAFCOUNT_MASK (UINT64_CAST 0x3f) + +/* + * RR_PORT_PARMS(_L) mask and shift definitions + */ + +#define RPPARM_MIPRESETEN_SHFT 29 /* Message In Progress reset enable */ +#define RPPARM_MIPRESETEN_MASK (UINT64_CAST 0x1 << 29) +#define RPPARM_UBAREN_SHFT 28 /* Enable user barrier requests */ +#define RPPARM_UBAREN_MASK (UINT64_CAST 0x1 << 28) +#define RPPARM_OUTPDTO_SHFT 24 /* Output Port Deadlock TO value */ +#define RPPARM_OUTPDTO_MASK (UINT64_CAST 0xf << 24) +#define RPPARM_PORTMATE_SHFT 21 /* Port Mate for the port */ +#define RPPARM_PORTMATE_MASK (UINT64_CAST 0x7 << 21) +#define RPPARM_HISTEN_SHFT 20 /* Histogram counter enable */ +#define RPPARM_HISTEN_MASK (UINT64_CAST 0x1 << 20) +#define RPPARM_HISTSEL_SHFT 18 +#define RPPARM_HISTSEL_MASK (UINT64_CAST 0x3 << 18) +#define RPPARM_DAMQHS_SHFT 16 +#define RPPARM_DAMQHS_MASK (UINT64_CAST 0x3 << 16) +#define RPPARM_NULLTO_SHFT 10 +#define RPPARM_NULLTO_MASK (UINT64_CAST 0x3f << 10) +#define RPPARM_MAXBURST_SHFT 0 +#define RPPARM_MAXBURST_MASK (UINT64_CAST 0x3ff) + +/* + * NOTE: Normally the kernel tracks only UTILIZATION statistics. + * The other 2 should not be used, except during any experimentation + * with the router. + */ +#define RPPARM_HISTSEL_AGE 0 /* Histogram age characterization. */ +#define RPPARM_HISTSEL_UTIL 1 /* Histogram link utilization */ +#define RPPARM_HISTSEL_DAMQ 2 /* Histogram DAMQ characterization. */ + +/* + * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions + */ +#define RSERR_POWERNOK (UINT64_CAST 1 << 38) +#define RSERR_PORT_DEADLOCK (UINT64_CAST 1 << 37) +#define RSERR_WARMRESET (UINT64_CAST 1 << 36) +#define RSERR_LINKRESET (UINT64_CAST 1 << 35) +#define RSERR_RETRYTIMEOUT (UINT64_CAST 1 << 34) +#define RSERR_FIFOOVERFLOW (UINT64_CAST 1 << 33) +#define RSERR_ILLEGALPORT (UINT64_CAST 1 << 32) +#define RSERR_DEADLOCKTO_SHFT 28 +#define RSERR_DEADLOCKTO_MASK (UINT64_CAST 0xf << 28) +#define RSERR_RECVTAILTO_SHFT 24 +#define RSERR_RECVTAILTO_MASK (UINT64_CAST 0xf << 24) +#define RSERR_RETRYCNT_SHFT 16 +#define RSERR_RETRYCNT_MASK (UINT64_CAST 0xff << 16) +#define RSERR_CBERRCNT_SHFT 8 +#define RSERR_CBERRCNT_MASK (UINT64_CAST 0xff << 8) +#define RSERR_SNERRCNT_SHFT 0 +#define RSERR_SNERRCNT_MASK (UINT64_CAST 0xff << 0) + + +#define PORT_STATUS_UP (1 << 0) /* Router link up */ +#define PORT_STATUS_FENCE (1 << 1) /* Router link fenced */ +#define PORT_STATUS_RESETFAIL (1 << 2) /* Router link didnot + * come out of reset */ +#define PORT_STATUS_DISCFAIL (1 << 3) /* Router link failed after + * out of reset but before + * router tables were + * programmed + */ +#define PORT_STATUS_KERNFAIL (1 << 4) /* Router link failed + * after reset and the + * router tables were + * programmed + */ +#define PORT_STATUS_UNDEF (1 << 5) /* Unable to pinpoint + * why the router link + * went down + */ +#define PROBE_RESULT_BAD (-1) /* Set if any of the router + * links failed after reset + */ +#define PROBE_RESULT_GOOD (0) /* Set if all the router links + * which came out of reset + * are up + */ + +/* Should be enough for 256 CPUs */ +#define MAX_RTR_BREADTH 64 /* Max # of routers possible */ + +/* Get the require set of bits in a var. corr to a sequence of bits */ +#define GET_FIELD(var, fname) \ + ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT) +/* Set the require set of bits in a var. corr to a sequence of bits */ +#define SET_FIELD(var, fname, fval) \ + ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT) + + +#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) + +typedef struct router_map_ent_s { + uint64_t nic; + moduleid_t module; + slotid_t slot; +} router_map_ent_t; + +struct rr_status_error_fmt { + uint64_t rserr_unused : 30, + rserr_fifooverflow : 1, + rserr_illegalport : 1, + rserr_deadlockto : 4, + rserr_recvtailto : 4, + rserr_retrycnt : 8, + rserr_cberrcnt : 8, + rserr_snerrcnt : 8; +}; + +/* + * This type is used to store "absolute" counts of router events + */ +typedef int router_count_t; + +/* All utilizations are on a scale from 0 - 1023. */ +#define RP_BYPASS_UTIL 0 +#define RP_RCV_UTIL 1 +#define RP_SEND_UTIL 2 +#define RP_TOTAL_PKTS 3 /* Free running clock/packet counter */ + +#define RP_NUM_UTILS 3 + +#define RP_HIST_REGS 2 +#define RP_NUM_BUCKETS 4 +#define RP_HIST_TYPES 3 + +#define RP_AGE0 0 +#define RP_AGE1 1 +#define RP_AGE2 2 +#define RP_AGE3 3 + + +#define RR_UTIL_SCALE 1024 + +/* + * Router port-oriented information + */ +typedef struct router_port_info_s { + router_reg_t rp_histograms[RP_HIST_REGS];/* Port usage info */ + router_reg_t rp_port_error; /* Port error info */ + router_count_t rp_retry_errors; /* Total retry errors */ + router_count_t rp_sn_errors; /* Total sn errors */ + router_count_t rp_cb_errors; /* Total cb errors */ + int rp_overflows; /* Total count overflows */ + int rp_excess_err; /* Port has excessive errors */ + ushort rp_util[RP_NUM_BUCKETS];/* Port utilization */ +} router_port_info_t; + +#define ROUTER_INFO_VERSION 7 + +struct lboard_s; + +/* + * Router information + */ +typedef struct router_info_s { + char ri_version; /* structure version */ + cnodeid_t ri_cnode; /* cnode of its legal guardian hub */ + nasid_t ri_nasid; /* Nasid of same */ + char ri_ledcache; /* Last LED bitmap */ + char ri_leds; /* Current LED bitmap */ + char ri_portmask; /* Active port bitmap */ + router_reg_t ri_stat_rev_id; /* Status rev ID value */ + net_vec_t ri_vector; /* vector from guardian to router */ + int ri_writeid; /* router's vector write ID */ + int64_t ri_timebase; /* Time of first sample */ + int64_t ri_timestamp; /* Time of last sample */ + router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info */ + moduleid_t ri_module; /* Which module are we in? */ + slotid_t ri_slotnum; /* Which slot are we in? */ + router_reg_t ri_glbl_parms[GLBL_PARMS_REGS]; + /* Global parms0&1 register contents*/ + devfs_handle_t ri_vertex; /* hardware graph vertex */ + router_reg_t ri_prot_conf; /* protection config. register */ + int64_t ri_per_minute; /* Ticks per minute */ + + /* + * Everything below here is for kernel use only and may change at + * at any time with or without a change in teh revision number + * + * Any pointers or things that come and go with DEBUG must go at + * the bottom of the structure, below the user stuff. + */ + char ri_hist_type; /* histogram type */ + devfs_handle_t ri_guardian; /* guardian node for the router */ + int64_t ri_last_print; /* When did we last print */ + char ri_print; /* Should we print */ + char ri_just_blink; /* Should we blink the LEDs */ + +#ifdef DEBUG + int64_t ri_deltatime; /* Time it took to sample */ +#endif + lock_t ri_lock; /* Lock for access to router info */ + net_vec_t *ri_vecarray; /* Pointer to array of vectors */ + struct lboard_s *ri_brd; /* Pointer to board structure */ + char * ri_name; /* This board's hwg path */ + unsigned char ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a + message to availmon */ +} router_info_t; + + +/* Router info location specifiers */ + +#define RIP_PROMLOG 2 /* Router info in promlog */ +#define RIP_CONSOLE 4 /* Router info on console */ + +#define ROUTER_INFO_PRINT(_rip,_where) (_rip->ri_print |= _where) + /* Set the field used to check if a + * router info can be printed + */ +#define IS_ROUTER_INFO_PRINTED(_rip,_where) \ + (_rip->ri_print & _where) + /* Was the router info printed to + * the given location (_where) ? + * Mainly used to prevent duplicate + * router error states. + */ +#define ROUTER_INFO_LOCK(_rip,_s) _s = mutex_spinlock(&(_rip->ri_lock)) + /* Take the lock on router info + * to gain exclusive access + */ +#define ROUTER_INFO_UNLOCK(_rip,_s) mutex_spinunlock(&(_rip->ri_lock),_s) + /* Release the lock on router info */ +/* + * Router info hanging in the nodepda + */ +typedef struct nodepda_router_info_s { + devfs_handle_t router_vhdl; /* vertex handle of the router */ + short router_port; /* port thru which we entered */ + short router_portmask; + moduleid_t router_module; /* module in which router is there */ + slotid_t router_slot; /* router slot */ + unsigned char router_type; /* kind of router */ + net_vec_t router_vector; /* vector from the guardian node */ + + router_info_t *router_infop; /* info hanging off the hwg vertex */ + struct nodepda_router_info_s *router_next; + /* pointer to next element */ +} nodepda_router_info_t; + +#define ROUTER_NAME_SIZE 20 /* Max size of a router name */ + +#define NORMAL_ROUTER_NAME "normal_router" +#define NULL_ROUTER_NAME "null_router" +#define META_ROUTER_NAME "meta_router" +#define UNKNOWN_ROUTER_NAME "unknown_router" + +/* The following definitions are needed by the router traversing + * code either using the hardware graph or using vector operations. + */ +/* Structure of the router queue element */ +typedef struct router_elt_s { + union { + /* queue element structure during router probing */ + struct { + /* number-in-a-can (unique) for the router */ + nic_t nic; + /* vector route from the master hub to + * this router. + */ + net_vec_t vec; + /* port status */ + uint64_t status; + char port_status[MAX_ROUTER_PORTS + 1]; + } r_elt; + /* queue element structure during router guardian + * assignment + */ + struct { + /* vertex handle for the router */ + devfs_handle_t vhdl; + /* guardian for this router */ + devfs_handle_t guard; + /* vector router from the guardian to the router */ + net_vec_t vec; + } k_elt; + } u; + /* easy to use port status interpretation */ +} router_elt_t; + +/* structure of the router queue */ + +typedef struct router_queue_s { + char head; /* Point where a queue element is inserted */ + char tail; /* Point where a queue element is removed */ + int type; + router_elt_t array[MAX_RTR_BREADTH]; + /* Entries for queue elements */ +} router_queue_t; + + +#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ + +/* + * RR_HISTOGRAM(_L) mask and shift definitions + * There are two 64 bit histogram registers, so the following macros take + * into account dealing with an array of 4 32 bit values indexed by _x + */ + +#define RHIST_BUCKET_SHFT(_x) (32 * ((_x) & 0x1)) +#define RHIST_BUCKET_MASK(_x) (UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1)) +#define RHIST_GET_BUCKET(_x, _reg) \ + ((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x)) + +/* + * RR_RESET_MASK(_L) mask and shift definitions + */ + +#define RRM_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RRM_RESETOK_ALL (UINT64_CAST 0x3f) + +/* + * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions + */ + +#define RTABLE_SHFT(_L) (4 * ((_L) - 1)) +#define RTABLE_MASK(_L) (UINT64_CAST 0x7 << RTABLE_SHFT(_L)) + + +#define ROUTERINFO_STKSZ 4096 + +#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) +#if defined(_LANGUAGE_C_PLUS_PLUS) +extern "C" { +#endif + +int router_reg_read(router_info_t *rip, int regno, router_reg_t *val); +int router_reg_write(router_info_t *rip, int regno, router_reg_t val); +int router_get_info(devfs_handle_t routerv, router_info_t *, int); +int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip); +int router_set_leds(router_info_t *rip); +void router_print_state(router_info_t *rip, int level, + void (*pf)(int, char *, ...),int print_where); +void capture_router_stats(router_info_t *rip); + + +int probe_routers(void); +void get_routername(unsigned char brd_type,char *rtrname); +void router_guardians_set(devfs_handle_t hwgraph_root); +int router_hist_reselect(router_info_t *, int64_t); +#if defined(_LANGUAGE_C_PLUS_PLUS) +} +#endif +#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ + +#endif /* _ASM_SN_SN1_ROUTER_H */ diff --git a/include/asm-ia64/sn/sn1/slotnum.h b/include/asm-ia64/sn/sn1/slotnum.h new file mode 100644 index 000000000..e814d546a --- /dev/null +++ b/include/asm-ia64/sn/sn1/slotnum.h @@ -0,0 +1,86 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +#ifndef _ASM_SN_SN1_SLOTNUM_H +#define _ASM_SN_SN1_SLOTNUM_H + +#define SLOTNUM_MAXLENGTH 16 + +/* + * This file attempts to define a slot number space across all slots + * a IP27 module. Here, we deal with the top level slots. + * + * Node slots + * Router slots + * Crosstalk slots + * + * Other slots are children of their parent crosstalk slot: + * PCI slots + * VME slots + */ +// #include <slotnum.h> + +// #ifdef NOTDEF /* moved to sys/slotnum.h */ +#define SLOTNUM_NODE_CLASS 0x00 /* Node */ +#define SLOTNUM_ROUTER_CLASS 0x10 /* Router */ +#define SLOTNUM_XTALK_CLASS 0x20 /* Xtalk */ +#define SLOTNUM_MIDPLANE_CLASS 0x30 /* Midplane */ +#define SLOTNUM_XBOW_CLASS 0x40 /* Xbow */ +#define SLOTNUM_KNODE_CLASS 0x50 /* Kego node */ +#define SLOTNUM_INVALID_CLASS 0xf0 /* Invalid */ + +#define SLOTNUM_CLASS_MASK 0xf0 +#define SLOTNUM_SLOT_MASK 0x0f + +#define SLOTNUM_GETCLASS(_sn) ((_sn) & SLOTNUM_CLASS_MASK) +#define SLOTNUM_GETSLOT(_sn) ((_sn) & SLOTNUM_SLOT_MASK) +// #endif /* NOTDEF */ + +/* This determines module to pnode mapping. */ +/* NODESLOTS_PER_MODULE has changed from 4 to 6 + * to support the 12P 4IO configuration. This change + * helps in minimum number of changes to code which + * depend on the number of node boards within a module. + */ +#define NODESLOTS_PER_MODULE 6 +#define NODESLOTS_PER_MODULE_SHFT 2 + +#define HIGHEST_I2C_VISIBLE_NODESLOT 4 +#define RTRSLOTS_PER_MODULE 2 + +#if __KERNEL__ +#include <asm/sn/xtalk/xtalk.h> + +extern slotid_t xbwidget_to_xtslot(int crossbow, int widget); +extern slotid_t hub_slotbits_to_slot(slotid_t slotbits); +extern slotid_t hub_slot_to_crossbow(slotid_t hub_slot); +extern slotid_t router_slotbits_to_slot(slotid_t slotbits); +extern slotid_t get_node_slotid(nasid_t nasid); +extern slotid_t get_my_slotid(void); +extern slotid_t get_node_crossbow(nasid_t); +extern xwidgetnum_t hub_slot_to_widget(slotid_t); +extern void get_slotname(slotid_t, char *); +extern void get_my_slotname(char *); +extern slotid_t get_widget_slotnum(int xbow, int widget); +extern void get_widget_slotname(int, int, char *); +extern void router_slotbits_to_slotname(int, char *); +extern slotid_t meta_router_slotbits_to_slot(slotid_t) ; +extern slotid_t hub_slot_get(void); + +extern int node_can_talk_to_elsc(void); + +extern int slot_to_widget(int) ; +#define MAX_IO_SLOT_NUM 12 +#define MAX_NODE_SLOT_NUM 4 +#define MAX_ROUTER_SLOTNUM 2 + +#endif /* __KERNEL__ */ + +#endif /* _ASM_SN_SN1_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn1/sn1.h b/include/asm-ia64/sn/sn1/sn1.h new file mode 100644 index 000000000..e03c2847a --- /dev/null +++ b/include/asm-ia64/sn/sn1/sn1.h @@ -0,0 +1,34 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ + +/* + * sn1.h -- hardware specific defines for sn1 boards + * The defines used here are used to limit the size of + * various datastructures in the PROM. eg. KLCFGINFO, MPCONF etc. + */ + +#ifndef _ASM_SN_SN1_SN1_H +#define _ASM_SN_SN1_SN1_H + +extern xwidgetnum_t hub_widget_id(nasid_t); +extern nasid_t get_nasid(void); +extern int get_slice(void); +extern int is_fine_dirmode(void); +extern hubreg_t get_hub_chiprev(nasid_t nasid); +extern hubreg_t get_region(cnodeid_t); +extern hubreg_t nasid_to_region(nasid_t); +extern int verify_snchip_rev(void); +extern void ni_reset_port(void); + +#ifdef SN1_USE_POISON_BITS +extern int hub_bte_poison_ok(void); +#endif /* SN1_USE_POISON_BITS */ + +#endif /* _ASM_SN_SN1_SN1_H */ diff --git a/include/asm-ia64/sn/sn1/uart16550.h b/include/asm-ia64/sn/sn1/uart16550.h new file mode 100644 index 000000000..128796a8a --- /dev/null +++ b/include/asm-ia64/sn/sn1/uart16550.h @@ -0,0 +1,214 @@ + +/* + * Definitions for 16550 chip + */ + + /* defined as offsets from the data register */ +#define REG_DAT 0 /* receive/transmit data */ +#define REG_ICR 1 /* interrupt control register */ +#define REG_ISR 2 /* interrupt status register */ +#define REG_FCR 2 /* fifo control register */ +#define REG_LCR 3 /* line control register */ +#define REG_MCR 4 /* modem control register */ +#define REG_LSR 5 /* line status register */ +#define REG_MSR 6 /* modem status register */ +#define REG_SCR 7 /* Scratch register */ +#define REG_DLL 0 /* divisor latch (lsb) */ +#define REG_DLH 1 /* divisor latch (msb) */ +#define REG_EFR 2 /* 16650 enhanced feature register */ + +/* + * 16450/16550 Registers Structure. + */ + +/* Line Control Register */ +#define LCR_WLS0 0x01 /*word length select bit 0 */ +#define LCR_WLS1 0x02 /*word length select bit 2 */ +#define LCR_STB 0x04 /* number of stop bits */ +#define LCR_PEN 0x08 /* parity enable */ +#define LCR_EPS 0x10 /* even parity select */ +#define LCR_SETBREAK 0x40 /* break key */ +#define LCR_DLAB 0x80 /* divisor latch access bit */ +#define LCR_RXLEN 0x03 /* # of data bits per received/xmitted char */ +#define LCR_STOP1 0x00 +#define LCR_STOP2 0x04 +#define LCR_PAREN 0x08 +#define LCR_PAREVN 0x10 +#define LCR_PARMARK 0x20 +#define LCR_SNDBRK 0x40 +#define LCR_DLAB 0x80 + + +#define LCR_BITS5 0x00 /* 5 bits per char */ +#define LCR_BITS6 0x01 /* 6 bits per char */ +#define LCR_BITS7 0x02 /* 7 bits per char */ +#define LCR_BITS8 0x03 /* 8 bits per char */ + +#define LCR_MASK_BITS_CHAR 0x03 +#define LCR_MASK_STOP_BITS 0x04 +#define LCR_MASK_PARITY_BITS 0x18 + + +/* Line Status Register */ +#define LSR_RCA 0x01 /* data ready */ +#define LSR_OVRRUN 0x02 /* overrun error */ +#define LSR_PARERR 0x04 /* parity error */ +#define LSR_FRMERR 0x08 /* framing error */ +#define LSR_BRKDET 0x10 /* a break has arrived */ +#define LSR_XHRE 0x20 /* tx hold reg is now empty */ +#define LSR_XSRE 0x40 /* tx shift reg is now empty */ +#define LSR_RFBE 0x80 /* rx FIFO Buffer error */ + +/* Interrupt Status Regisger */ +#define ISR_MSTATUS 0x00 +#define ISR_TxRDY 0x02 +#define ISR_RxRDY 0x04 +#define ISR_ERROR_INTR 0x08 +#define ISR_FFTMOUT 0x0c /* FIFO Timeout */ +#define ISR_RSTATUS 0x06 /* Receiver Line status */ + +/* Interrupt Enable Register */ +#define ICR_RIEN 0x01 /* Received Data Ready */ +#define ICR_TIEN 0x02 /* Tx Hold Register Empty */ +#define ICR_SIEN 0x04 /* Receiver Line Status */ +#define ICR_MIEN 0x08 /* Modem Status */ + +/* Modem Control Register */ +#define MCR_DTR 0x01 /* Data Terminal Ready */ +#define MCR_RTS 0x02 /* Request To Send */ +#define MCR_OUT1 0x04 /* Aux output - not used */ +#define MCR_OUT2 0x08 /* turns intr to 386 on/off */ +#define MCR_LOOP 0x10 /* loopback for diagnostics */ +#define MCR_AFE 0x20 /* Auto flow control enable */ + +/* Modem Status Register */ +#define MSR_DCTS 0x01 /* Delta Clear To Send */ +#define MSR_DDSR 0x02 /* Delta Data Set Ready */ +#define MSR_DRI 0x04 /* Trail Edge Ring Indicator */ +#define MSR_DDCD 0x08 /* Delta Data Carrier Detect */ +#define MSR_CTS 0x10 /* Clear To Send */ +#define MSR_DSR 0x20 /* Data Set Ready */ +#define MSR_RI 0x40 /* Ring Indicator */ +#define MSR_DCD 0x80 /* Data Carrier Detect */ + +#define DELTAS(x) ((x)&(MSR_DCTS|MSR_DDSR|MSR_DRI|MSR_DDCD)) +#define STATES(x) ((x)(MSR_CTS|MSR_DSR|MSR_RI|MSR_DCD)) + + +#define FCR_FIFOEN 0x01 /* enable receive/transmit fifo */ +#define FCR_RxFIFO 0x02 /* enable receive fifo */ +#define FCR_TxFIFO 0x04 /* enable transmit fifo */ +#define FCR_MODE1 0x08 /* change to mode 1 */ +#define RxLVL0 0x00 /* Rx fifo level at 1 */ +#define RxLVL1 0x40 /* Rx fifo level at 4 */ +#define RxLVL2 0x80 /* Rx fifo level at 8 */ +#define RxLVL3 0xc0 /* Rx fifo level at 14 */ + +#define FIFOEN (FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL3 | FCR_MODE1) + +#define FCT_TxMASK 0x30 /* mask for Tx trigger */ +#define FCT_RxMASK 0xc0 /* mask for Rx trigger */ + +/* enhanced festures register */ +#define EFR_SFLOW 0x0f /* various S/w Flow Controls */ +#define EFR_EIC 0x10 /* Enhanced Interrupt Control bit */ +#define EFR_SCD 0x20 /* Special Character Detect */ +#define EFR_RTS 0x40 /* RTS flow control */ +#define EFR_CTS 0x80 /* CTS flow control */ + +/* Rx Tx software flow controls in 16650 enhanced mode */ +#define SFLOW_Tx0 0x00 /* no Xmit flow control */ +#define SFLOW_Tx1 0x08 /* Transmit Xon1, Xoff1 */ +#define SFLOW_Tx2 0x04 /* Transmit Xon2, Xoff2 */ +#define SFLOW_Tx3 0x0c /* Transmit Xon1,Xon2, Xoff1,Xoff2 */ +#define SFLOW_Rx0 0x00 /* no Rcv flow control */ +#define SFLOW_Rx1 0x02 /* Receiver compares Xon1, Xoff1 */ +#define SFLOW_Rx2 0x01 /* Receiver compares Xon2, Xoff2 */ + +#define ASSERT_DTR(x) (x |= MCR_DTR) +#define ASSERT_RTS(x) (x |= MCR_RTS) +#define DU_RTS_ASSERTED(x) (((x) & MCR_RTS) != 0) +#define DU_RTS_ASSERT(x) ((x) |= MCR_RTS) +#define DU_RTS_DEASSERT(x) ((x) &= ~MCR_RTS) + + +/* + * ioctl(fd, I_STR, arg) + * use the SIOC_RS422 and SIOC_EXTCLK combination to support MIDI + */ +#define SIOC ('z' << 8) /* z for z85130 */ +#define SIOC_EXTCLK (SIOC | 1) /* select/de-select external clock */ +#define SIOC_RS422 (SIOC | 2) /* select/de-select RS422 protocol */ +#define SIOC_ITIMER (SIOC | 3) /* upstream timer adjustment */ +#define SIOC_LOOPBACK (SIOC | 4) /* diagnostic loopback test mode */ + + +/* channel control register */ +#define DMA_INT_MASK 0xe0 /* ring intr mask */ +#define DMA_INT_TH25 0x20 /* 25% threshold */ +#define DMA_INT_TH50 0x40 /* 50% threshold */ +#define DMA_INT_TH75 0x60 /* 75% threshold */ +#define DMA_INT_EMPTY 0x80 /* ring buffer empty */ +#define DMA_INT_NEMPTY 0xa0 /* ring buffer not empty */ +#define DMA_INT_FULL 0xc0 /* ring buffer full */ +#define DMA_INT_NFULL 0xe0 /* ring buffer not full */ + +#define DMA_CHANNEL_RESET 0x400 /* reset dma channel */ +#define DMA_ENABLE 0x200 /* enable DMA */ + +/* peripheral controller intr status bits applicable to serial ports */ +#define ISA_SERIAL0_MASK 0x03f00000 /* mask for port #1 intrs */ +#define ISA_SERIAL0_DIR 0x00100000 /* device intr request */ +#define ISA_SERIAL0_Tx_THIR 0x00200000 /* Transmit DMA threshold */ +#define ISA_SERIAL0_Tx_PREQ 0x00400000 /* Transmit DMA pair req */ +#define ISA_SERIAL0_Tx_MEMERR 0x00800000 /* Transmit DMA memory err */ +#define ISA_SERIAL0_Rx_THIR 0x01000000 /* Receive DMA threshold */ +#define ISA_SERIAL0_Rx_OVERRUN 0x02000000 /* Receive DMA over-run */ + +#define ISA_SERIAL1_MASK 0xfc000000 /* mask for port #1 intrs */ +#define ISA_SERIAL1_DIR 0x04000000 /* device intr request */ +#define ISA_SERIAL1_Tx_THIR 0x08000000 /* Transmit DMA threshold */ +#define ISA_SERIAL1_Tx_PREQ 0x10000000 /* Transmit DMA pair req */ +#define ISA_SERIAL1_Tx_MEMERR 0x20000000 /* Transmit DMA memory err */ +#define ISA_SERIAL1_Rx_THIR 0x40000000 /* Receive DMA threshold */ +#define ISA_SERIAL1_Rx_OVERRUN 0x80000000 /* Receive DMA over-run */ + +#define MAX_RING_BLOCKS 128 /* 4096/32 */ +#define MAX_RING_SIZE 4096 + +/* DMA Input Control Byte */ +#define DMA_IC_OVRRUN 0x01 /* overrun error */ +#define DMA_IC_PARERR 0x02 /* parity error */ +#define DMA_IC_FRMERR 0x04 /* framing error */ +#define DMA_IC_BRKDET 0x08 /* a break has arrived */ +#define DMA_IC_VALID 0x80 /* pair is valid */ + +/* DMA Output Control Byte */ +#define DMA_OC_TxINTR 0x20 /* set Tx intr after processing byte */ +#define DMA_OC_INVALID 0x00 /* invalid pair */ +#define DMA_OC_WTHR 0x40 /* Write byte to THR */ +#define DMA_OC_WMCR 0x80 /* Write byte to MCR */ +#define DMA_OC_DELAY 0xc0 /* time delay before next xmit */ + +/* ring id's */ +#define RID_SERIAL0_TX 0x4 /* serial port 0, transmit ring buffer */ +#define RID_SERIAL0_RX 0x5 /* serial port 0, receive ring buffer */ +#define RID_SERIAL1_TX 0x6 /* serial port 1, transmit ring buffer */ +#define RID_SERIAL1_RX 0x7 /* serial port 1, receive ring buffer */ + +#define CLOCK_XIN 22 +#define PRESCALER_DIVISOR 3 +#define CLOCK_ACE 7333333 + +/* + * increment the ring offset. One way to do this would be to add b'100000. + * this would let the offset value roll over automatically when it reaches + * its maximum value (127). However when we use the offset, we must use + * the appropriate bits only by masking with 0xfe0. + * The other option is to shift the offset right by 5 bits and look at its + * value. Then increment if required and shift back + * note: 127 * 2^5 = 4064 + */ +#define INC_RING_POINTER(x) \ + ( ((x & 0xffe0) < 4064) ? (x += 32) : 0 ) + diff --git a/include/asm-ia64/sn/sn1/war.h b/include/asm-ia64/sn/sn1/war.h new file mode 100644 index 000000000..a79bc7f85 --- /dev/null +++ b/include/asm-ia64/sn/sn1/war.h @@ -0,0 +1,25 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_SN1_WAR_H +#define _ASM_SN_SN1_WAR_H + +/**************************************************************************** + * Support macros and defitions for hardware workarounds in * + * early chip versions. * + ****************************************************************************/ + +/* + * This is the bitmap of runtime-switched workarounds. + */ +typedef short warbits_t; + +extern int warbits_override; + +#endif /* _ASM_SN_SN1_WAR_H */ |